root/dev/ic/aic7xxx_inline.h

INCLUDED FROM

DEFINITIONS

1. ahc_pause_bug_fix
2. ahc_is_paused
3. ahc_pause
4. ahc_unpause
5. ahc_freeze_untagged_queues
6. ahc_release_untagged_queues
7. ahc_sg_bus_to_virt
8. ahc_sg_virt_to_bus
9. ahc_hscb_busaddr
10. ahc_sync_scb
11. ahc_targetcmd_offset
12. ahc_name
13. ahc_update_residual
14. ahc_fetch_transinfo
15. ahc_inw
16. ahc_outw
17. ahc_inl
18. ahc_outl
19. ahc_get_scb
20. ahc_free_scb
21. ahc_lookup_scb
22. ahc_swap_with_next_hscb
23. ahc_queue_scb
24. ahc_get_sense_buf
25. ahc_get_sense_bufaddr
26. ahc_sync_qoutfifo
27. ahc_sync_tqinfifo
28. ahc_check_cmdcmpltqueues
29. ahc_intr

    1 /*      $OpenBSD: aic7xxx_inline.h,v 1.14 2007/05/14 01:37:49 deraadt Exp $     */
    2 /*      $NetBSD: aic7xxx_inline.h,v 1.4 2003/11/02 11:07:44 wiz Exp $   */
    4 /*
    5  * Inline routines shareable across OS platforms.
    6  *
    7  * Copyright (c) 1994-2001 Justin T. Gibbs.
    8  * Copyright (c) 2000-2001 Adaptec Inc.
    9  * All rights reserved.
   10  *
   11  * Redistribution and use in source and binary forms, with or without
   12  * modification, are permitted provided that the following conditions
   13  * are met:
   14  * 1. Redistributions of source code must retain the above copyright
   15  *    notice, this list of conditions, and the following disclaimer,
   16  *    without modification.
   17  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
   18  *    substantially similar to the "NO WARRANTY" disclaimer below
   19  *    ("Disclaimer") and any redistribution must be conditioned upon
   20  *    including a substantially similar Disclaimer requirement for further
   21  *    binary redistribution.
   22  * 3. Neither the names of the above-listed copyright holders nor the names
   23  *    of any contributors may be used to endorse or promote products derived
   24  *    from this software without specific prior written permission.
   25  *
   26  * Alternatively, this software may be distributed under the terms of the
   27  * GNU General Public License ("GPL") version 2 as published by the Free
   28  * Software Foundation.
   29  *
   30  * NO WARRANTY
   31  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
   32  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
   33  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
   34  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
   35  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   36  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   37  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   38  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
   39  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
   40  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   41  * POSSIBILITY OF SUCH DAMAGES.
   42  *
   43  * //depot/aic7xxx/aic7xxx/aic7xxx_inline.h#39 $
   44  *
   45  * $FreeBSD: /repoman/r/ncvs/src/sys/dev/aic7xxx/aic7xxx_inline.h,v 1.20 2003/01/20 20:44:55 gibbs Exp $
   46  */
   47 /*
   48  * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003
   49  */
   51 #ifndef _AIC7XXX_INLINE_H_
   52 #define _AIC7XXX_INLINE_H_
   54 #ifdef SMALL_KERNEL
   55 #define IO_INLINE
   56 #else
   57 #define IO_INLINE       static __inline
   58 #define IO_EXPAND
   59 #endif
   61 /************************* Sequencer Execution Control ************************/
IO_INLINE void ahc_pause_bug_fix(struct ahc_softc *ahc);
IO_INLINE int  ahc_is_paused(struct ahc_softc *ahc);
IO_INLINE void ahc_pause(struct ahc_softc *ahc);
IO_INLINE void ahc_unpause(struct ahc_softc *ahc);
   67 #ifdef IO_EXPAND
   68 /*
   69  * Work around any chip bugs related to halting sequencer execution.
   70  * On Ultra2 controllers, we must clear the CIOBUS stretch signal by
   71  * reading a register that will set this signal and deassert it.
   72  * Without this workaround, if the chip is paused, by an interrupt or
   73  * manual pause while accessing scb ram, accesses to certain registers
   74  * will hang the system (infinite pci retries).
   75  */
IO_INLINE void
ahc_pause_bug_fix(struct ahc_softc *ahc)
   78 {
   79         if ((ahc->features & AHC_ULTRA2) != 0)
   80                 (void)ahc_inb(ahc, CCSCBCTL);
   81 }
   83 /*
   84  * Determine whether the sequencer has halted code execution.
   85  * Returns non-zero status if the sequencer is stopped.
   86  */
IO_INLINE int
ahc_is_paused(struct ahc_softc *ahc)
   89 {
   90         return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0);
   91 }
   93 /*
   94  * Request that the sequencer stop and wait, indefinitely, for it
   95  * to stop.  The sequencer will only acknowledge that it is paused
   96  * once it has reached an instruction boundary and PAUSEDIS is
   97  * cleared in the SEQCTL register.  The sequencer may use PAUSEDIS
   98  * for critical sections.
   99  */
IO_INLINE void
ahc_pause(struct ahc_softc *ahc)
  102 {
ahc_outb(ahc, HCNTRL, ahc->pause);
  105         /*
  106          * Since the sequencer can disable pausing in a critical section, we
  107          * must loop until it actually stops.
  108          */
  109         while (ahc_is_paused(ahc) == 0)
  110                 ;
ahc_pause_bug_fix(ahc);
  113 }
  115 /*
  116  * Allow the sequencer to continue program execution.
  117  * We check here to ensure that no additional interrupt
  118  * sources that would cause the sequencer to halt have been
  119  * asserted.  If, for example, a SCSI bus reset is detected
  120  * while we are fielding a different, pausing, interrupt type,
  121  * we don't want to release the sequencer before going back
  122  * into our interrupt handler and dealing with this new
  123  * condition.
  124  */
IO_INLINE void
ahc_unpause(struct ahc_softc *ahc)
  127 {
  128         if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0)
ahc_outb(ahc, HCNTRL, ahc->unpause);
  130 }
  131 #endif /* IO_EXPAND */
  133 /*********************** Untagged Transaction Routines ************************/
IO_INLINE void  ahc_freeze_untagged_queues(struct ahc_softc *ahc);
IO_INLINE void  ahc_release_untagged_queues(struct ahc_softc *ahc);
  137 #ifdef IO_EXPAND
  138 /*
  139  * Block our completion routine from starting the next untagged
  140  * transaction for this target or target lun.
  141  */
IO_INLINE void
ahc_freeze_untagged_queues(struct ahc_softc *ahc)
  144 {
  145         if ((ahc->flags & AHC_SCB_BTT) == 0)
ahc->untagged_queue_lock++;
  147 }
  149 /*
  150  * Allow the next untagged transaction for this target or target lun
  151  * to be executed.  We use a counting semaphore to allow the lock
  152  * to be acquired recursively.  Once the count drops to zero, the
  153  * transaction queues will be run.
  154  */
IO_INLINE void
ahc_release_untagged_queues(struct ahc_softc *ahc)
  157 {
  158         if ((ahc->flags & AHC_SCB_BTT) == 0) {
ahc->untagged_queue_lock--;
  160                 if (ahc->untagged_queue_lock == 0)
ahc_run_untagged_queues(ahc);
  162         }
  163 }
  164 #endif /* IO_EXPAND */
  167 /************************** Memory mapping routines ***************************/
IO_INLINE struct ahc_dma_seg *
ahc_sg_bus_to_virt(struct scb *scb,
uint32_t sg_busaddr);
IO_INLINE uint32_t
ahc_sg_virt_to_bus(struct scb *scb,
  173                                            struct ahc_dma_seg *sg);
IO_INLINE uint32_t
ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index);
IO_INLINE void          ahc_sync_scb(struct ahc_softc *ahc,
  177                                            struct scb *scb, int op);
  178 #ifdef AHC_TARGET_MODE
IO_INLINE uint32_t
ahc_targetcmd_offset(struct ahc_softc *ahc,
u_int index);
  182 #endif
  184 #ifdef IO_EXPAND
IO_INLINE struct ahc_dma_seg *
ahc_sg_bus_to_virt(struct scb *scb, uint32_t sg_busaddr)
  188 {
  189         int sg_index;
sg_index = (sg_busaddr - scb->sg_list_phys)/sizeof(struct ahc_dma_seg);
  192         /* sg_list_phys points to entry 1, not 0 */
sg_index++;
  195         return (&scb->sg_list[sg_index]);
  196 }
IO_INLINE uint32_t
ahc_sg_virt_to_bus(struct scb *scb, struct ahc_dma_seg *sg)
  200 {
  201         int sg_index;
  203         /* sg_list_phys points to entry 1, not 0 */
sg_index = sg - &scb->sg_list[1];
  206         return (scb->sg_list_phys + (sg_index * sizeof(*scb->sg_list)));
  207 }
IO_INLINE uint32_t
ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index)
  211 {
  212         return (ahc->scb_data->hscb_busaddr
  213                 + (sizeof(struct hardware_scb) * index));
  214 }
IO_INLINE void
ahc_sync_scb(struct ahc_softc *ahc, struct scb *scb, int op)
  218 {
ahc_dmamap_sync(ahc, ahc->parent_dmat,
ahc->scb_data->hscb_dmamap,
  221                         /*offset*/(scb->hscb - ahc->scb_data->hscbs) * sizeof(*scb->hscb),
  222                         /*len*/sizeof(*scb->hscb), op);
  223 }
  225 #ifdef AHC_TARGET_MODE
IO_INLINE uint32_t
ahc_targetcmd_offset(struct ahc_softc *ahc, u_int index)
  228 {
  229         return (((uint8_t *)&ahc->targetcmds[index]) - ahc->qoutfifo);
  230 }
  231 #endif /* AHC_TARGET_MODE */
  232 #endif /* IO_EXPAND */
  234 /******************************** Debugging ***********************************/
  235 static __inline char *ahc_name(struct ahc_softc *ahc);
  237 static __inline char *
ahc_name(struct ahc_softc *ahc)
  239 {
  240         return (ahc->name);
  241 }
  243 /*********************** Miscellaneous Support Functions ***********************/
IO_INLINE void  ahc_update_residual(struct ahc_softc *ahc,
  246                                             struct scb *scb);
IO_INLINE struct ahc_initiator_tinfo *
ahc_fetch_transinfo(struct ahc_softc *ahc,
  249                                             char channel, u_int our_id,
u_int remote_id,
  251                                             struct ahc_tmode_tstate **tstate);
IO_INLINE uint16_t
ahc_inw(struct ahc_softc *ahc, u_int port);
IO_INLINE void  ahc_outw(struct ahc_softc *ahc, u_int port,
u_int value);
IO_INLINE uint32_t
ahc_inl(struct ahc_softc *ahc, u_int port);
IO_INLINE void  ahc_outl(struct ahc_softc *ahc, u_int port,
uint32_t value);
IO_INLINE struct scb*
ahc_get_scb(struct ahc_softc *ahc);
IO_INLINE void          ahc_free_scb(struct ahc_softc *ahc, struct scb *scb);
IO_INLINE struct scb *ahc_lookup_scb(struct ahc_softc *ahc, u_int tag);
IO_INLINE void          ahc_swap_with_next_hscb(struct ahc_softc *ahc,
  266                                                 struct scb *scb);
IO_INLINE void          ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb);
IO_INLINE struct scsi_sense_data *
ahc_get_sense_buf(struct ahc_softc *ahc,
  270                                           struct scb *scb);
IO_INLINE uint32_t
ahc_get_sense_bufaddr(struct ahc_softc *ahc,
  273                                               struct scb *scb);
  275 #ifdef IO_EXPAND
  277 /*
  278  * Determine whether the sequencer reported a residual
  279  * for this SCB/transaction.
  280  */
IO_INLINE void
ahc_update_residual(struct ahc_softc *ahc, struct scb *scb)
  283 {
uint32_t sgptr;
sgptr = aic_le32toh(scb->hscb->sgptr);
  287         if ((sgptr & SG_RESID_VALID) != 0)
ahc_calc_residual(ahc, scb);
  289 }
  291 /*
  292  * Return pointers to the transfer negotiation information
  293  * for the specified our_id/remote_id pair.
  294  */
IO_INLINE struct ahc_initiator_tinfo *
ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id,
u_int remote_id, struct ahc_tmode_tstate **tstate)
  298 {
  299         /*
  300          * Transfer data structures are stored from the perspective
  301          * of the target role.  Since the parameters for a connection
  302          * in the initiator role to a given target are the same as
  303          * when the roles are reversed, we pretend we are the target.
  304          */
  305         /*if (channel == 'B')
  306           our_id += 8;*/
  307         *tstate = ahc->enabled_targets[our_id];
  308         return (&(*tstate)->transinfo[remote_id]);
  309 }
IO_INLINE uint16_t
ahc_inw(struct ahc_softc *ahc, u_int port)
  313 {
  314         return ((ahc_inb(ahc, port+1) << 8) | ahc_inb(ahc, port));
  315 }
IO_INLINE void
ahc_outw(struct ahc_softc *ahc, u_int port, u_int value)
  319 {
ahc_outb(ahc, port, value & 0xFF);
ahc_outb(ahc, port+1, (value >> 8) & 0xFF);
  322 }
IO_INLINE uint32_t
ahc_inl(struct ahc_softc *ahc, u_int port)
  326 {
  327         return ((ahc_inb(ahc, port))
  328               | (ahc_inb(ahc, port+1) << 8)
  329               | (ahc_inb(ahc, port+2) << 16)
  330               | (ahc_inb(ahc, port+3) << 24));
  331 }
IO_INLINE void
ahc_outl(struct ahc_softc *ahc, u_int port, uint32_t value)
  335 {
ahc_outb(ahc, port, (value) & 0xFF);
ahc_outb(ahc, port+1, ((value) >> 8) & 0xFF);
ahc_outb(ahc, port+2, ((value) >> 16) & 0xFF);
ahc_outb(ahc, port+3, ((value) >> 24) & 0xFF);
  340 }
  342 /*
  343  * Get a free scb. If there are none, see if we can allocate a new SCB.
  344  */
IO_INLINE struct scb *
ahc_get_scb(struct ahc_softc *ahc)
  347 {
  348         struct scb *scb;
scb = SLIST_FIRST(&ahc->scb_data->free_scbs);
  352         if (scb != NULL)
SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links.sle);
  355         return (scb);
  356 }
  358 /*
  359  * Return an SCB resource to the free list.
  360  */
IO_INLINE void
ahc_free_scb(struct ahc_softc *ahc, struct scb *scb)
  363 {       
  364         struct hardware_scb *hscb;
hscb = scb->hscb;
  367         /* Clean up for the next user */
ahc->scb_data->scbindex[hscb->tag] = NULL;
scb->flags = SCB_FLAG_NONE;
hscb->control = 0;
SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links.sle);
  374         /* Notify the OSM that a resource is now available. */
ahc_platform_scb_free(ahc, scb);
  376 }
IO_INLINE struct scb *
ahc_lookup_scb(struct ahc_softc *ahc, u_int tag)
  381 {
  382         struct scb* scb;
scb = ahc->scb_data->scbindex[tag];
  385         if (scb != NULL)
ahc_sync_scb(ahc, scb,
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
  388         return (scb);
  389 }
IO_INLINE void
ahc_swap_with_next_hscb(struct ahc_softc *ahc, struct scb *scb)
  394 {
  395         struct hardware_scb *q_hscb;
u_int  saved_tag;
  398         /*
  399          * Our queuing method is a bit tricky.  The card
  400          * knows in advance which HSCB to download, and we
  401          * can't disappoint it.  To achieve this, the next
  402          * SCB to download is saved off in ahc->next_queued_scb.
  403          * When we are called to queue "an arbitrary scb",
  404          * we copy the contents of the incoming HSCB to the one
  405          * the sequencer knows about, swap HSCB pointers and
  406          * finally assign the SCB to the tag indexed location
  407          * in the scb_array.  This makes sure that we can still
  408          * locate the correct SCB by SCB_TAG.
  409          */
q_hscb = ahc->next_queued_scb->hscb;
saved_tag = q_hscb->tag;
memcpy(q_hscb, scb->hscb, sizeof(*scb->hscb));
  413         if ((scb->flags & SCB_CDB32_PTR) != 0) {
q_hscb->shared_data.cdb_ptr =
aic_htole32(ahc_hscb_busaddr(ahc, q_hscb->tag)
  416                               + offsetof(struct hardware_scb, cdb32));
  417         }
q_hscb->tag = saved_tag;
q_hscb->next = scb->hscb->tag;
  421         /* Now swap HSCB pointers. */
ahc->next_queued_scb->hscb = scb->hscb;
scb->hscb = q_hscb;
  425         /* Now define the mapping from tag to SCB in the scbindex */
ahc->scb_data->scbindex[scb->hscb->tag] = scb;
  427 }
  429 /*
  430  * Tell the sequencer about a new transaction to execute.
  431  */
IO_INLINE void
ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb)
  434 {
ahc_swap_with_next_hscb(ahc, scb);
  437         if (scb->hscb->tag == SCB_LIST_NULL
  438          || scb->hscb->next == SCB_LIST_NULL)
panic("Attempt to queue invalid SCB tag %x:%x",
scb->hscb->tag, scb->hscb->next);
  442         /*
  443          * Setup data "oddness".
  444          */
scb->hscb->lun &= LID;
  446         if (ahc_get_transfer_length(scb) & 0x1)
scb->hscb->lun |= SCB_XFERLEN_ODD;
  449         /*
  450          * Keep a history of SCBs we've downloaded in the qinfifo.
  451          */
ahc->qinfifo[ahc->qinfifonext] = scb->hscb->tag;
ahc_dmamap_sync(ahc, ahc->parent_dmat, ahc->shared_data_dmamap,
  454                         /*offset*/ahc->qinfifonext+256, /*len*/1,
BUS_DMASYNC_PREWRITE);
ahc->qinfifonext++;
  458         /*
  459          * Make sure our data is consistent from the
  460          * perspective of the adapter.
  461          */
ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
  464         /* Tell the adapter about the newly queued SCB */
  465         if ((ahc->features & AHC_QUEUE_REGS) != 0) {
ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
  467         } else {
  468                 if ((ahc->features & AHC_AUTOPAUSE) == 0)
ahc_pause(ahc);
ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
  471                 if ((ahc->features & AHC_AUTOPAUSE) == 0)
ahc_unpause(ahc);
  473         }
  474 }
IO_INLINE struct scsi_sense_data *
ahc_get_sense_buf(struct ahc_softc *ahc, struct scb *scb)
  479 {
  480         int offset;
offset = scb - ahc->scb_data->scbarray;
  483         return (&ahc->scb_data->sense[offset]);
  484 }
IO_INLINE uint32_t
ahc_get_sense_bufaddr(struct ahc_softc *ahc, struct scb *scb)
  488 {
  489         int offset;
offset = scb - ahc->scb_data->scbarray;
  492         return (ahc->scb_data->sense_busaddr
  493               + (offset * sizeof(struct scsi_sense_data)));
  494 }
  495 #endif /* IO_EXPAND */
  497 /************************** Interrupt Processing ******************************/
IO_INLINE void  ahc_sync_qoutfifo(struct ahc_softc *ahc, int op);
IO_INLINE void  ahc_sync_tqinfifo(struct ahc_softc *ahc, int op);
IO_INLINE u_int ahc_check_cmdcmpltqueues(struct ahc_softc *ahc);
IO_INLINE int   ahc_intr(struct ahc_softc *ahc);
  503 #ifdef IO_EXPAND
IO_INLINE void
ahc_sync_qoutfifo(struct ahc_softc *ahc, int op)
  506 {
ahc_dmamap_sync(ahc, ahc->parent_dmat, ahc->shared_data_dmamap,
  508                         /*offset*/0, /*len*/256, op);
  509 }
IO_INLINE void
ahc_sync_tqinfifo(struct ahc_softc *ahc, int op)
  513 {
  514 #ifdef AHC_TARGET_MODE
  515         if ((ahc->flags & AHC_TARGETROLE) != 0) {
ahc_dmamap_sync(ahc, ahc->parent_dmat /*shared_data_dmat*/,
ahc->shared_data_dmamap,
ahc_targetcmd_offset(ahc, 0),
  519                                 sizeof(struct target_cmd) * AHC_TMODE_CMDS,
op);
  521         }
  522 #endif
  523 }
  525 /*
  526  * See if the firmware has posted any completed commands
  527  * into our in-core command complete fifos.
  528  */
  529 #define AHC_RUN_QOUTFIFO 0x1
  530 #define AHC_RUN_TQINFIFO 0x2
IO_INLINE u_int
ahc_check_cmdcmpltqueues(struct ahc_softc *ahc)
  533 {
u_int retval;
retval = 0;
ahc_dmamap_sync(ahc, ahc->parent_dmat /*shared_data_dmat*/, ahc->shared_data_dmamap,
  538                         /*offset*/ahc->qoutfifonext, /*len*/1,
BUS_DMASYNC_POSTREAD);
  540         if (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL)
retval |= AHC_RUN_QOUTFIFO;
  542 #ifdef AHC_TARGET_MODE
  543         if ((ahc->flags & AHC_TARGETROLE) != 0
  544             && (ahc->flags & AHC_TQINFIFO_BLOCKED) == 0) {
ahc_dmamap_sync(ahc, ahc->parent_dmat /*shared_data_dmat*/,
ahc->shared_data_dmamap,
ahc_targetcmd_offset(ahc, ahc->tqinfifonext),
  548                           /*len*/sizeof(struct target_cmd),
BUS_DMASYNC_POSTREAD);
  550                 if (ahc->targetcmds[ahc->tqinfifonext].cmd_valid != 0)
retval |= AHC_RUN_TQINFIFO;
  552         }
  553 #endif
  554         return (retval);
  555 }
  558 /*
  559  * Catch an interrupt from the adapter
  560  */
IO_INLINE int
ahc_intr(struct ahc_softc *ahc)
  563 {
u_int   intstat;
  566         if ((ahc->pause & INTEN) == 0) {
  567                 /*
  568                  * Our interrupt is not enabled on the chip
  569                  * and may be disabled for re-entrancy reasons,
  570                  * so just return.  This is likely just a shared
  571                  * interrupt.
  572                  */
  573                 return (0);
  574         }
  575         /*
  576          * Instead of directly reading the interrupt status register,
  577          * infer the cause of the interrupt by checking our in-core
  578          * completion queues.  This avoids a costly PCI bus read in
  579          * most cases.
  580          */
  581         if ((ahc->flags & (AHC_ALL_INTERRUPTS|AHC_EDGE_INTERRUPT)) == 0
  582             && (ahc_check_cmdcmpltqueues(ahc) != 0))
intstat = CMDCMPLT;
  584         else {
intstat = ahc_inb(ahc, INTSTAT);
  586         }
  588         if (intstat & CMDCMPLT) {
ahc_outb(ahc, CLRINT, CLRCMDINT);
  591                 /*
  592                  * Ensure that the chip sees that we've cleared
  593                  * this interrupt before we walk the output fifo.
  594                  * Otherwise, we may, due to posted bus writes,
  595                  * clear the interrupt after we finish the scan,
  596                  * and after the sequencer has added new entries
  597                  * and asserted the interrupt again.
  598                  */
ahc_flush_device_writes(ahc);
ahc_run_qoutfifo(ahc);
  601 #ifdef AHC_TARGET_MODE
  602                 if ((ahc->flags & AHC_TARGETROLE) != 0)
ahc_run_tqinfifo(ahc, /*paused*/FALSE);
  604 #endif
  605         }
  607         if (intstat == 0xFF && (ahc->features & AHC_REMOVABLE) != 0)
  608                 /* Hot eject */
  609                 return 1;
  611         if ((intstat & INT_PEND) == 0) {
  612 #if AHC_PCI_CONFIG > 0
  613                 if (ahc->unsolicited_ints > 500) {
ahc->unsolicited_ints = 0;
  615                         if ((ahc->chip & AHC_PCI) != 0
  616                          && (ahc_inb(ahc, ERROR) & PCIERRSTAT) != 0)
ahc->bus_intr(ahc);
  618                 }
ahc->unsolicited_ints++;
  620 #endif
  621                 return 0;
  622         }
ahc->unsolicited_ints = 0;
  625         if (intstat & BRKADRINT) {
ahc_handle_brkadrint(ahc);
  627                 /* Fatal error, no more interrupts to handle. */
  628                 return 1;
  629         }
  631         if ((intstat & (SEQINT|SCSIINT)) != 0)
ahc_pause_bug_fix(ahc);
  634         if ((intstat & SEQINT) != 0)
ahc_handle_seqint(ahc, intstat);
  637         if ((intstat & SCSIINT) != 0)
ahc_handle_scsiint(ahc, intstat);
  640         return (1);
  641 }
  643 #endif  /* IO_EXPAND */
  645 #endif  /* _AIC7XXX_INLINE_H_ */