phase 3520 dev/ic/aic79xx.c ahd_lookup_phase_entry(int phase)
phase 3531 dev/ic/aic79xx.c if (phase == entry->phase)
phase 858 dev/ic/aic79xx.h uint8_t phase;
phase 1486 dev/ic/aic79xx.h ahd_lookup_phase_entry(int phase);
phase 887 dev/ic/aic7xxx.c if (lastphase == ahc_phase_table[i].phase)
phase 1146 dev/ic/aic7xxx.c if (errorphase == ahc_phase_table[i].phase)
phase 1436 dev/ic/aic7xxx.c if (lastphase == ahc_phase_table[i].phase)
phase 2273 dev/ic/aic7xxx.c ahc_lookup_phase_entry(int phase)
phase 2284 dev/ic/aic7xxx.c if (phase == entry->phase)
phase 798 dev/ic/aic7xxxvar.h uint8_t phase;
phase 1273 dev/ic/aic7xxxvar.h ahc_lookup_phase_entry(int phase);
phase 1727 dev/ic/iha.c int phase;
phase 1729 dev/ic/iha.c if ((phase = iha_wait(sc, iot, ioh, CMD_COMP)) == -1)
phase 1736 dev/ic/iha.c if (phase == PHASE_MSG_OUT) {
phase 1746 dev/ic/iha.c } else if (phase == PHASE_MSG_IN) {
phase 1949 dev/ic/iha.c int phase;
phase 1957 dev/ic/iha.c phase = iha_wait(sc, iot, ioh, XF_FIFO_IN);
phase 1965 dev/ic/iha.c phase = -1;
phase 1970 dev/ic/iha.c phase = iha_wait(sc, iot, ioh, MSG_ACCEPT);
phase 1978 dev/ic/iha.c phase = iha_wait(sc, iot, ioh, MSG_ACCEPT);
phase 1981 dev/ic/iha.c phase = iha_msgin_extended(sc, iot, ioh);
phase 1984 dev/ic/iha.c phase = iha_msgin_ignore_wid_resid(sc, iot, ioh);
phase 1989 dev/ic/iha.c phase = iha_wait(sc, iot, ioh, MSG_ACCEPT);
phase 1990 dev/ic/iha.c if (phase != -1) {
phase 1999 dev/ic/iha.c phase = iha_msgout_reject(sc, iot, ioh);
phase 2003 dev/ic/iha.c if (phase != PHASE_MSG_IN)
phase 2004 dev/ic/iha.c return (phase);
phase 2015 dev/ic/iha.c int phase;
phase 2017 dev/ic/iha.c phase = iha_wait(sc, iot, ioh, MSG_ACCEPT);
phase 2019 dev/ic/iha.c if (phase == PHASE_MSG_IN) {
phase 2020 dev/ic/iha.c phase = iha_wait(sc, iot, ioh, XF_FIFO_IN);
phase 2022 dev/ic/iha.c if (phase != -1) {
phase 2027 dev/ic/iha.c phase = iha_wait(sc, iot, ioh, MSG_ACCEPT);
phase 2031 dev/ic/iha.c return (phase);
phase 2041 dev/ic/iha.c int i, phase, msglen, msgcode;
phase 2047 dev/ic/iha.c phase = iha_wait(sc, iot, ioh, MSG_ACCEPT);
phase 2049 dev/ic/iha.c if (phase != PHASE_MSG_IN)
phase 2050 dev/ic/iha.c return (phase);
phase 2074 dev/ic/iha.c phase = iha_wait(sc, iot, ioh, MSG_ACCEPT);
phase 2075 dev/ic/iha.c if (phase != PHASE_MSG_OUT)
phase 2076 dev/ic/iha.c return (phase);
phase 2107 dev/ic/iha.c phase = iha_wait(sc, iot, ioh, MSG_ACCEPT);
phase 2108 dev/ic/iha.c if (phase != PHASE_MSG_OUT)
phase 2109 dev/ic/iha.c return (phase);
phase 2221 dev/ic/iha.c int phase;
phase 2228 dev/ic/iha.c phase = iha_wait(sc, iot, ioh, XF_FIFO_OUT);
phase 2233 dev/ic/iha.c return (phase);
phase 238 dev/ic/ncr5380sbc.c ncr5380_pio_out(sc, phase, count, data)
phase 240 dev/ic/ncr5380sbc.c int phase, count;
phase 262 dev/ic/ncr5380sbc.c if (SCI_BUS_PHASE(*sc->sci_bus_csr) != phase)
phase 299 dev/ic/ncr5380sbc.c ncr5380_pio_in(sc, phase, count, data)
phase 301 dev/ic/ncr5380sbc.c int phase, count;
phase 321 dev/ic/ncr5380sbc.c if (SCI_BUS_PHASE(*sc->sci_bus_csr) != phase)
phase 1076 dev/ic/ncr5380sbc.c int target, lun, phase, timo;
phase 1205 dev/ic/ncr5380sbc.c phase = SCI_BUS_PHASE(*sc->sci_bus_csr);
phase 1206 dev/ic/ncr5380sbc.c if (phase != PHASE_MSG_IN) {
phase 1208 dev/ic/ncr5380sbc.c sc->sc_dev.dv_xname, phase);
phase 1554 dev/ic/ncr5380sbc.c int n, phase;
phase 1600 dev/ic/ncr5380sbc.c phase = SCI_BUS_PHASE(*sc->sci_bus_csr);
phase 1601 dev/ic/ncr5380sbc.c if (phase != PHASE_MSG_IN) {
phase 1794 dev/ic/ncr5380sbc.c int act_flags, n, phase, progress;
phase 1936 dev/ic/ncr5380sbc.c phase = SCI_BUS_PHASE(*sc->sci_bus_csr);
phase 1937 dev/ic/ncr5380sbc.c if (phase != PHASE_MSG_OUT) {
phase 1942 dev/ic/ncr5380sbc.c NCR_TRACE("msg_out: new phase=%d\n", phase);
phase 2061 dev/ic/ncr5380sbc.c ncr5380_data_xfer(sc, phase)
phase 2063 dev/ic/ncr5380sbc.c int phase;
phase 2072 dev/ic/ncr5380sbc.c if (phase != PHASE_DATA_IN) {
phase 2078 dev/ic/ncr5380sbc.c len = ncr5380_pio_in(sc, phase, sizeof(xs->sense),
phase 2088 dev/ic/ncr5380sbc.c sc->sc_dev.dv_xname, phase_names[phase & 7]);
phase 2095 dev/ic/ncr5380sbc.c if (phase != expected_phase) {
phase 2103 dev/ic/ncr5380sbc.c if (phase == PHASE_DATA_IN)
phase 2104 dev/ic/ncr5380sbc.c ncr5380_pio_in(sc, phase, 4096, NULL);
phase 2106 dev/ic/ncr5380sbc.c ncr5380_pio_out(sc, phase, 4096, NULL);
phase 2108 dev/ic/ncr5380sbc.c if (SCI_BUS_PHASE(*sc->sci_bus_csr) == phase) {
phase 2141 dev/ic/ncr5380sbc.c *sc->sci_tcmd = phase; /* XXX: OK for PDMA? */
phase 2142 dev/ic/ncr5380sbc.c if (phase == PHASE_DATA_OUT) {
phase 2143 dev/ic/ncr5380sbc.c len = (*sc->sc_pio_out)(sc, phase, sc->sc_datalen, sc->sc_dataptr);
phase 2145 dev/ic/ncr5380sbc.c len = (*sc->sc_pio_in) (sc, phase, sc->sc_datalen, sc->sc_dataptr);
phase 2197 dev/ic/ncr5380sbc.c int act_flags, phase, timo;
phase 2255 dev/ic/ncr5380sbc.c phase = SCI_BUS_PHASE(*sc->sci_bus_csr);
phase 2257 dev/ic/ncr5380sbc.c (long) phase_names[phase & 7]);
phase 2270 dev/ic/ncr5380sbc.c *sc->sci_tcmd = phase; /* acknowledge phase change */
phase 2273 dev/ic/ncr5380sbc.c switch (phase) {
phase 2277 dev/ic/ncr5380sbc.c act_flags = ncr5380_data_xfer(sc, phase);
phase 2297 dev/ic/ncr5380sbc.c printf("ncr5380_machine: Unexpected phase 0x%x\n", phase);
phase 2303 dev/ic/ncr5380sbc.c sc->sc_prevphase = phase;
phase 798 dev/ic/trm.c u_int16_t phase;
phase 837 dev/ic/trm.c phase = (u_int16_t) pSRB->ScsiPhase; /* phase: */
phase 843 dev/ic/trm.c stateV = trm_SCSI_phase0[phase];
phase 854 dev/ic/trm.c phase = (u_int16_t) scsi_status & PHASEMASK;
phase 859 dev/ic/trm.c stateV = trm_SCSI_phase1[phase];
phase 280 dev/isa/seagate.c int sea_transfer_pio(struct sea_softc *sea, u_char *phase,
phase 830 dev/isa/seagate.c u_char lun, phase;
phase 870 dev/isa/seagate.c phase = PH_MSGIN;
phase 871 dev/isa/seagate.c sea_transfer_pio(sea, &phase, &len, &data);
phase 908 dev/isa/seagate.c phase = PH_MSGOUT;
phase 910 dev/isa/seagate.c sea_transfer_pio(sea, &phase, &len, &data);
phase 921 dev/isa/seagate.c sea_transfer_pio(struct sea_softc *sea, u_char *phase, int *count, u_char **data)
phase 923 dev/isa/seagate.c u_char p = *phase, tmp;
phase 987 dev/isa/seagate.c *phase = tmp & PH_MASK;
phase 989 dev/isa/seagate.c *phase = PH_INVALID;
phase 991 dev/isa/seagate.c if (c && (*phase != p))
phase 1005 dev/isa/seagate.c u_char msg[3], phase;
phase 1077 dev/isa/seagate.c phase = PH_MSGOUT;
phase 1079 dev/isa/seagate.c sea_transfer_pio(sea, &phase, &len, &data);
phase 1100 dev/isa/seagate.c u_char msg, phase, *msgptr;
phase 1135 dev/isa/seagate.c phase = PH_MSGOUT;
phase 1137 dev/isa/seagate.c sea_transfer_pio(sea, &phase, &len, &msgptr);
phase 1210 dev/isa/seagate.c u_char phase, tmp, old_phase = PH_INVALID;
phase 1243 dev/isa/seagate.c phase = tmp & PH_MASK;
phase 1244 dev/isa/seagate.c if (phase != old_phase)
phase 1245 dev/isa/seagate.c old_phase = phase;
phase 1247 dev/isa/seagate.c switch (phase) {
phase 1274 dev/isa/seagate.c if ((tmp & PH_MASK) != phase)
phase 1276 dev/isa/seagate.c if (!(phase & STAT_IO)) {
phase 1321 dev/isa/seagate.c sea_transfer_pio(sea, &phase, &scb->datalen,
phase 1328 dev/isa/seagate.c sea_transfer_pio(sea, &phase, &len, &data);
phase 1379 dev/isa/seagate.c sea_transfer_pio(sea, &phase, &len, &data);
phase 1398 dev/isa/seagate.c sea_transfer_pio(sea, &phase, &len, &data);
phase 1403 dev/isa/seagate.c sea_transfer_pio(sea, &phase, &len, &data);
phase 367 net/if_spppsubr.c HIDE const char *sppp_phase_name(enum ppp_phase phase);
phase 4329 net/if_spppsubr.c sppp_phase_name(enum ppp_phase phase)
phase 4331 net/if_spppsubr.c switch (phase) {
phase 171 netatalk/ddp_input.c ddp_input( m, ifp, elh, phase )
phase 175 netatalk/ddp_input.c int phase;
phase 245 netatalk/ddp_input.c if ( phase == 1 && ( aa->aa_flags & AFA_PHASE2 )) {
phase 248 netatalk/ddp_input.c if ( phase == 2 && ( aa->aa_flags & AFA_PHASE2 ) == 0 ) {