root/dev/pci/pccbb.c

DEFINITIONS

1. pcicbbmatch
2. cb_chipset
3. pccbb_shutdown
4. pccbbattach
5. pccbb_pci_callback
6. pccbb_chipinit
7. pccbb_pcmcia_attach_setup
8. pccbb_pcmcia_attach_card
9. pccbb_pcmcia_detach_card
10. pccbbintr
11. pccbbintr_function
12. pci113x_insert
13. pccbb_pcmcia_read
14. pccbb_pcmcia_write
15. pccbb_ctrl
16. pccbb_power
17. cb_pcmcia_poll
18. pccbb_detect_card
19. cb_reset
20. cb_detect_voltage
21. cbbprint
22. pccbb_cardenable
23. pccbb_cb_intr_establish
24. pccbb_cb_intr_disestablish
25. pccbb_intr_establish
26. pccbb_intr_disestablish
27. cb_show_regs
28. pccbb_make_tag
29. pccbb_free_tag
30. pccbb_conf_read
31. pccbb_conf_write
32. pccbb_new_pcmcia_io_alloc
33. pccbb_pcmcia_io_free
34. pccbb_pcmcia_io_map
35. pccbb_pcmcia_do_io_map
36. pccbb_pcmcia_io_unmap
37. pccbb_pcmcia_wait_ready
38. pccbb_pcmcia_socket_enable
39. pccbb_pcmcia_socket_disable
40. pccbb_pcmcia_card_detect
41. pccbb_new_pcmcia_mem_alloc
42. pccbb_pcmcia_mem_free
43. pccbb_pcmcia_do_mem_map
44. pccbb_pcmcia_mem_map
45. pccbb_pcmcia_mem_unmap
46. pccbb_pcmcia_poll
47. pccbb_pcmcia_intr_establish
48. pccbb_pcmcia_intr_disestablish
49. pccbb_pcmcia_intr_string
50. pccbb_rbus_cb_space_alloc
51. pccbb_rbus_cb_space_free
52. pccbb_open_win
53. pccbb_close_win
54. pccbb_winlist_insert
55. pccbb_winlist_delete
56. pccbb_winset
57. pccbb_powerhook

    1 /*      $OpenBSD: pccbb.c,v 1.47 2006/10/12 16:35:51 grange Exp $       */
    2 /*      $NetBSD: pccbb.c,v 1.96 2004/03/28 09:49:31 nakayama Exp $      */
    4 /*
    5  * Copyright (c) 1998, 1999 and 2000
    6  *      HAYAKAWA Koichi.  All rights reserved.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  * 3. All advertising materials mentioning features or use of this software
   17  *    must display the following acknowledgement:
   18  *      This product includes software developed by HAYAKAWA Koichi.
   19  * 4. The name of the author may not be used to endorse or promote products
   20  *    derived from this software without specific prior written permission.
   21  *
   22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   24  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   25  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   28  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   29  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   32  */
   34 /*
   35 #define CBB_DEBUG
   36 #define SHOW_REGS
   37 #define PCCBB_PCMCIA_POLL
   38 */
   40 /*
   41 #define CB_PCMCIA_POLL
   42 #define CB_PCMCIA_POLL_ONLY
   43 #define LEVEL2
   44 */
   46 #include <sys/types.h>
   47 #include <sys/param.h>
   48 #include <sys/systm.h>
   49 #include <sys/kernel.h>
   50 #include <sys/errno.h>
   51 #include <sys/evcount.h>
   52 #include <sys/ioctl.h>
   53 #include <sys/syslog.h>
   54 #include <sys/device.h>
   55 #include <sys/malloc.h>
   57 #include <machine/intr.h>
   58 #include <machine/bus.h>
   60 #include <dev/pci/pcivar.h>
   61 #include <dev/pci/pcireg.h>
   62 #include <dev/pci/pcidevs.h>
   64 #include <dev/pci/pccbbreg.h>
   66 #include <dev/cardbus/cardslotvar.h>
   68 #include <dev/cardbus/cardbusvar.h>
   70 #include <dev/pcmcia/pcmciareg.h>
   71 #include <dev/pcmcia/pcmciavar.h>
   73 #include <dev/ic/i82365reg.h>
   74 #include <dev/ic/i82365var.h>
   75 #include <dev/pci/pccbbvar.h>
   77 #ifndef __NetBSD_Version__
   78 struct cfdriver cbb_cd = {
NULL, "cbb", DV_DULL
   80 };
   81 #endif
   83 #if defined CBB_DEBUG
   84 #define DPRINTF(x) printf x
   85 #else
   86 #define DPRINTF(x)
   87 #endif
   89 int     pcicbbmatch(struct device *, void *, void *);
   90 void    pccbbattach(struct device *, struct device *, void *);
   91 int     pccbbintr(void *);
   92 void    pccbb_shutdown(void *);
   93 void    pci113x_insert(void *);
   94 int     pccbbintr_function(struct pccbb_softc *);
   96 int     pccbb_detect_card(struct pccbb_softc *);
   98 void    pccbb_pcmcia_write(struct pcic_handle *, int, int);
u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int);
  100 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg)))
  101 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val)))
  103 int     cb_reset(struct pccbb_softc *);
  104 int     cb_detect_voltage(struct pccbb_softc *);
  105 int     cbbprint(void *, const char *);
  107 int     cb_chipset(u_int32_t, int *);
  108 void    pccbb_pcmcia_attach_setup(struct pccbb_softc *,
  109     struct pcmciabus_attach_args *);
  110 #if 0
  111 void    pccbb_pcmcia_attach_card(struct pcic_handle *);
  112 void    pccbb_pcmcia_detach_card(struct pcic_handle *, int);
  113 void    pccbb_pcmcia_deactivate_card(struct pcic_handle *);
  114 #endif
  116 int     pccbb_ctrl(cardbus_chipset_tag_t, int);
  117 int     pccbb_power(cardbus_chipset_tag_t, int);
  118 int     pccbb_cardenable(struct pccbb_softc * sc, int function);
  119 void   *pccbb_intr_establish(struct pccbb_softc *, int irq, int level,
  120     int (*ih) (void *), void *sc, const char *);
  121 void    pccbb_intr_disestablish(struct pccbb_softc *, void *ih);
  123 void   *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, int level,
  124     int (*ih) (void *), void *sc, const char *);
  125 void    pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih);
cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int, int);
  128 void    pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t);
cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int);
  130 void    pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int,
cardbusreg_t);
  132 void    pccbb_chipinit(struct pccbb_softc *);
  134 int     pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t,
  135     struct pcmcia_mem_handle *);
  136 void    pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t,
  137     struct pcmcia_mem_handle *);
  138 int     pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t,
bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *);
  140 void    pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int);
  141 int     pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t,
bus_size_t, bus_size_t, struct pcmcia_io_handle *);
  143 void    pccbb_pcmcia_io_free(pcmcia_chipset_handle_t,
  144     struct pcmcia_io_handle *);
  145 int     pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t,
bus_size_t, struct pcmcia_io_handle *, int *);
  147 void    pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int);
  148 void   *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t,
  149     struct pcmcia_function *, int, int (*)(void *), void *, char *);
  150 void    pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *);
  151 const char *pccbb_pcmcia_intr_string(pcmcia_chipset_handle_t, void *);
  152 void    pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t);
  153 void    pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t);
  154 int     pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch);
  156 void    pccbb_pcmcia_do_io_map(struct pcic_handle *, int);
  157 void    pccbb_pcmcia_wait_ready(struct pcic_handle *);
  158 void    pccbb_pcmcia_do_mem_map(struct pcic_handle *, int);
  159 void    pccbb_powerhook(int, void *);
  161 /* bus-space allocation and deallocation functions */
  162 int     pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t,
bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align,
  164     int flags, bus_addr_t * addrp, bus_space_handle_t * bshp);
  165 int     pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t,
bus_space_handle_t, bus_size_t);
  168 int     pccbb_open_win(struct pccbb_softc *, bus_space_tag_t,
bus_addr_t, bus_size_t, bus_space_handle_t, int flags);
  170 int     pccbb_close_win(struct pccbb_softc *, bus_space_tag_t,
bus_space_handle_t, bus_size_t);
  172 int     pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t,
bus_size_t, bus_space_handle_t, int);
  174 int     pccbb_winlist_delete(struct pccbb_win_chain_head *,
bus_space_handle_t, bus_size_t);
  176 void    pccbb_winset(bus_addr_t align, struct pccbb_softc *,
bus_space_tag_t);
  178 void    pccbb_winlist_show(struct pccbb_win_chain *);
  180 /* for config_defer */
  181 void    pccbb_pci_callback(struct device *);
  183 #if defined SHOW_REGS
  184 void    cb_show_regs(pci_chipset_tag_t, pcitag_t, bus_space_tag_t,
bus_space_handle_t memh);
  186 #endif
  188 struct cfattach cbb_pci_ca = {
  189         sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach
  190 };
  192 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = {
pccbb_pcmcia_mem_alloc,
pccbb_pcmcia_mem_free,
pccbb_pcmcia_mem_map,
pccbb_pcmcia_mem_unmap,
pccbb_pcmcia_io_alloc,
pccbb_pcmcia_io_free,
pccbb_pcmcia_io_map,
pccbb_pcmcia_io_unmap,
pccbb_pcmcia_intr_establish,
pccbb_pcmcia_intr_disestablish,
pccbb_pcmcia_intr_string,
pccbb_pcmcia_socket_enable,
pccbb_pcmcia_socket_disable,
pccbb_pcmcia_card_detect
  207 };
  209 static struct cardbus_functions pccbb_funcs = {
pccbb_rbus_cb_space_alloc,
pccbb_rbus_cb_space_free,
pccbb_cb_intr_establish,
pccbb_cb_intr_disestablish,
pccbb_ctrl,
pccbb_power,
pccbb_make_tag,
pccbb_free_tag,
pccbb_conf_read,
pccbb_conf_write,
  220 };
  222 int
pcicbbmatch(parent, match, aux)
  224         struct device *parent;
  225         void *match;
  226         void *aux;
  227 {
  228         struct pci_attach_args *pa = (struct pci_attach_args *)aux;
  230         if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS &&
PCI_INTERFACE(pa->pa_class) == 0) {
  233                 return 1;
  234         }
  236         return 0;
  237 }
  239 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \
  240                                 | ((prod) << PCI_PRODUCT_SHIFT))
  242 struct yenta_chipinfo {
pcireg_t yc_id;                /* vendor tag | product tag */
  244         int yc_chiptype;
  245         int yc_flags;
  246 } yc_chipsets[] = {
  247         /* Texas Instruments chips */
  248         { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X,
PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
  250         { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X,
PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
  252         { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X,
PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
  254         { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX,
PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
  256         { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX,
PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
  258         { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX,
PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
  260         { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X,
PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
  262         { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X,
PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
  264         { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX,
PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
  266         { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX,
PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
  268         { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX,
PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
  270         { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X,
PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
  272         { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX,
PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
  274         { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI7XX1), CB_TI12XX,
PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
  277         /* Ricoh chips */
  278         { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C475), CB_RX5C47X,
PCCBB_PCMCIA_MEM_32},
  280         { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C476), CB_RX5C47X,
PCCBB_PCMCIA_MEM_32},
  282         { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C477), CB_RX5C47X,
PCCBB_PCMCIA_MEM_32},
  284         { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C478), CB_RX5C47X,
PCCBB_PCMCIA_MEM_32},
  286         { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C465), CB_RX5C46X,
PCCBB_PCMCIA_MEM_32},
  288         { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C466), CB_RX5C46X,
PCCBB_PCMCIA_MEM_32},
  291         /* Toshiba products */
  292         { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95),
CB_TOPIC95, PCCBB_PCMCIA_MEM_32},
  294         { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B),
CB_TOPIC95B, PCCBB_PCMCIA_MEM_32},
  296         { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97),
CB_TOPIC97, PCCBB_PCMCIA_MEM_32},
  298         { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100),
CB_TOPIC97, PCCBB_PCMCIA_MEM_32},
  301         /* Cirrus Logic products */
  302         { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832),
CB_CIRRUS, PCCBB_PCMCIA_MEM_32},
  304         { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833),
CB_CIRRUS, PCCBB_PCMCIA_MEM_32},
  307         /* older O2Micro bridges */
  308         { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6729),
CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32},
  310         { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6730),
CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32},
  312         { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6872), /* 68[71]2 */
CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32},
  314         { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6832),
CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32},
  316         { MAKEID(PCI_VENDOR_O2MICRO, PCI_PRODUCT_O2MICRO_OZ6836),
CB_OLDO2MICRO, PCCBB_PCMCIA_MEM_32},
  319         /* sentinel, or Generic chip */
  320         { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32},
  321 };
  323 int
cb_chipset(pci_id, flagp)
u_int32_t pci_id;
  326         int *flagp;
  327 {
  328         struct yenta_chipinfo *yc;
  330         /* Loop over except the last default entry. */
  331         for (yc = yc_chipsets; yc < yc_chipsets +
  332             sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++)
  333                 if (pci_id == yc->yc_id)
  334                         break;
  336         if (flagp != NULL)
  337                 *flagp = yc->yc_flags;
  339         return (yc->yc_chiptype);
  340 }
  342 void
pccbb_shutdown(void *arg)
  344 {
  345         struct pccbb_softc *sc = arg;
pcireg_t command;
DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname));
  350         /* turn off power */
pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V);
bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK,
  354             0);
command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);
command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
PCI_COMMAND_MASTER_ENABLE);
pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command);
  361 }
  363 void
pccbbattach(parent, self, aux)
  365         struct device *parent;
  366         struct device *self;
  367         void *aux;
  368 {
  369         struct pccbb_softc *sc = (void *)self;
  370         struct pci_attach_args *pa = aux;
pci_chipset_tag_t pc = pa->pa_pc;
pcireg_t busreg, reg, sock_base;
pci_intr_handle_t ih;
  374         const char *intrstr = NULL;
bus_addr_t sockbase;
  376         int flags;
  378 #ifdef __HAVE_PCCBB_ATTACH_HOOK
pccbb_attach_hook(parent, self, pa);
  380 #endif
sc->sc_chipset = cb_chipset(pa->pa_id, &flags);
  384 #ifdef CBB_DEBUG
printf(" (chipflags %x)", flags);
  386 #endif
TAILQ_INIT(&sc->sc_memwindow);
TAILQ_INIT(&sc->sc_iowindow);
sc->sc_rbus_iot = rbus_pccbb_parent_io(self, pa);
sc->sc_rbus_memt = rbus_pccbb_parent_mem(self, pa);
sc->sc_flags &= ~CBB_MEMHMAPPED;
  396         /*
  397          * MAP socket registers and ExCA registers on memory-space
  398          * When no valid address is set on socket base registers (on pci
  399          * config space), get it not polite way.
  400          */
sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE);
  403         if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 &&
PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) {
  405                 /* The address must be valid. */
  406                 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0,
  407                     &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL, 0))
  408                     {
printf("%s: can't map socket base address 0x%x\n",
sc->sc_dev.dv_xname, sock_base);
  411                         /*
  412                          * I think it's funny: socket base registers must be
  413                          * mapped on memory space, but ...
  414                          */
  415                         if (pci_mapreg_map(pa, PCI_SOCKBASE,
PCI_MAPREG_TYPE_IO, 0, &sc->sc_base_memt,
  417                             &sc->sc_base_memh, &sockbase, NULL, 0)) {
printf("%s: can't map socket base address"
  419                                     " 0x%lx: io mode\n", sc->sc_dev.dv_xname,
sockbase);
  421                                 /* give up... allocate reg space via rbus. */
pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0);
  423                         } else
sc->sc_flags |= CBB_MEMHMAPPED;
  425                 } else {
DPRINTF(("%s: socket base address 0x%lx\n",
sc->sc_dev.dv_xname, sockbase));
sc->sc_flags |= CBB_MEMHMAPPED;
  429                 }
  430         }
sc->sc_mem_start = 0;          /* XXX */
sc->sc_mem_end = 0xffffffff;   /* XXX */
  435         /*
  436          * When bus number isn't set correctly, give up using 32-bit CardBus
  437          * mode.
  438          */
busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM);
  440 #if notyet
  441         if (((busreg >> 8) & 0xff) == 0) {
printf(": CardBus support disabled because of unconfigured bus number\n");
flags |= PCCBB_PCMCIA_16BITONLY;
  444         }
  445 #endif
  447         /* pccbb_machdep.c end */
  449 #if defined CBB_DEBUG
  450         {
  451                 static char *intrname[5] = { "NON", "A", "B", "C", "D" };
printf(": intrpin %s, intrtag %d\n",
intrname[pa->pa_intrpin], pa->pa_intrline);
  454         }
  455 #endif
  457         /* setup softc */
sc->sc_pc = pc;
sc->sc_iot = pa->pa_iot;
sc->sc_memt = pa->pa_memt;
sc->sc_dmat = pa->pa_dmat;
sc->sc_tag = pa->pa_tag;
sc->sc_function = pa->pa_function;
sc->sc_sockbase = sock_base;
sc->sc_busnum = busreg;
sc->sc_intrtag = pa->pa_intrtag;
sc->sc_intrpin = pa->pa_intrpin;
sc->sc_pcmcia_flags = flags;   /* set PCMCIA facility */
  471         /* Map and establish the interrupt. */
  472         if (pci_intr_map(pa, &ih)) {
printf(": couldn't map interrupt\n");
  474                 return;
  475         }
intrstr = pci_intr_string(pc, ih);
  477         /* must do this after intr is mapped and established */
sc->sc_intrline = pci_intr_line(ih);
  480         /*
  481          * XXX pccbbintr should be called under the priority lower
  482          * than any other hard interrupts.
  483          */
sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc,
sc->sc_dev.dv_xname);
  487         if (sc->sc_ih == NULL) {
printf(": couldn't establish interrupt");
  489                 if (intrstr != NULL) {
printf(" at %s", intrstr);
  491                 }
printf("\n");
  493                 return;
  494         }
printf(": %s\n", intrstr);
shutdownhook_establish(pccbb_shutdown, sc);
  499         /* Disable legacy register mapping. */
  500         switch (sc->sc_chipset) {
  501         case CB_RX5C46X:               /* fallthrough */
  502 #if 0
  503         /* The RX5C47X-series requires writes to the PCI_LEGACY register. */
  504         case CB_RX5C47X:
  505 #endif
  506                 /*
  507                  * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges
  508                  * cannot be disabled by substituting 0 into PCI_LEGACY
  509                  * register.  Ricoh CardBus bridges have special bits on Bridge
  510                  * control reg (addr 0x3e on PCI config space).
  511                  */
reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR);
reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA);
pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg);
  515                 break;
  517         default:
  518                 /* XXX I don't know proper way to kill legacy I/O. */
pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0);
  520                 break;
  521         }
timeout_set(&sc->sc_ins_tmo, pci113x_insert, sc);
config_defer(self, pccbb_pci_callback);
  525 }
  527 /*
  528  * void pccbb_pci_callback(struct device *self)
  529  *
  530  *   The actual attach routine: get memory space for YENTA register
  531  *   space, setup YENTA register and route interrupt.
  532  *
  533  *   This function should be deferred because this device may obtain
  534  *   memory space dynamically.  This function must avoid obtaining
  535  *   memory area which has already kept for another device.  Also,
  536  *   this function MUST be done before ISA attach process because this
  537  *   function kills pcic compatible port used by ISA pcic.
  538  */
  539 void
pccbb_pci_callback(self)
  541         struct device *self;
  542 {
  543         struct pccbb_softc *sc = (void *)self;
pci_chipset_tag_t pc = sc->sc_pc;
bus_space_tag_t base_memt;
bus_space_handle_t base_memh;
u_int32_t maskreg;
bus_addr_t sockbase;
  549         struct cbslot_attach_args cba;
  550         struct pcmciabus_attach_args paa;
  551         struct cardslot_attach_args caa;
  552         struct cardslot_softc *csc;
  554         if (!(sc->sc_flags & CBB_MEMHMAPPED)) {
  555                 /* The socket registers aren't mapped correctly. */
  556                 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff,
  557                     (sc->sc_chipset == CB_RX5C47X
  558                     || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000,
  559                     0, &sockbase, &sc->sc_base_memh)) {
  560                         return;
  561                 }
sc->sc_base_memt = sc->sc_memt;
pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase);
DPRINTF(("%s: CardBus register address 0x%lx -> 0x%x\n",
sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag,
PCI_SOCKBASE)));
sc->sc_flags |= CBB_MEMHMAPPED;
  568         }
  570         /* bus bridge initialization */
pccbb_chipinit(sc);
base_memt = sc->sc_base_memt;  /* socket regs memory tag */
base_memh = sc->sc_base_memh;  /* socket regs memory handle */
  576         /* clear data structure for child device interrupt handlers */
sc->sc_pil = NULL;
sc->sc_pil_intr_enable = 1;
powerhook_establish(pccbb_powerhook, sc);
  582         {
u_int32_t sockstat =
bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT);
  585                 if (0 == (sockstat & CB_SOCKET_STAT_CD)) {
sc->sc_flags |= CBB_CARDEXIST;
  587                 }
  588         }
  590         /*
  591          * attach cardbus
  592          */
  593         if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) {
pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM);
pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG);
  597                 /* initialize cbslot_attach */
cba.cba_busname = "cardbus";
cba.cba_iot = sc->sc_iot;
cba.cba_memt = sc->sc_memt;
cba.cba_dmat = sc->sc_dmat;
cba.cba_bus = (busreg >> 8) & 0x0ff;
cba.cba_cc = (void *)sc;
cba.cba_cf = &pccbb_funcs;
cba.cba_intrline = sc->sc_intrline;
cba.cba_rbus_iot = sc->sc_rbus_iot;
cba.cba_rbus_memt = sc->sc_rbus_memt;
cba.cba_cacheline = PCI_CACHELINE(bhlc);
cba.cba_lattimer = PCI_CB_LATENCY(busreg);
  613 #if defined CBB_DEBUG
printf("%s: cacheline 0x%x lattimer 0x%x\n",
sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer);
printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc,
busreg);
  618 #endif
  619 #if defined SHOW_REGS
cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt,
sc->sc_base_memh);
  622 #endif
  623         }
pccbb_pcmcia_attach_setup(sc, &paa);
caa.caa_cb_attach = NULL;
  627         if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) {
caa.caa_cb_attach = &cba;
  629         }
caa.caa_16_attach = &paa;
caa.caa_ph = &sc->sc_pcmcia_h;
  633         if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) {
DPRINTF(("pccbbattach: found cardslot\n"));
sc->sc_csc = csc;
  636         }
sc->sc_ints_on = 1;
  640         /* CSC Interrupt: Card detect interrupt on */
maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK);
maskreg |= CB_SOCKET_MASK_CD;  /* Card detect intr is turned on. */
bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg);
  644         /* reset interrupt */
bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT,
bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT));
  648         return;
  649 }
  651 /*
  652  * void pccbb_chipinit(struct pccbb_softc *sc)
  653  *
  654  *   This function initialize YENTA chip registers listed below:
  655  *     1) PCI command reg,
  656  *     2) PCI and CardBus latency timer,
  657  *     3) route PCI interrupt,
  658  *     4) close all memory and io windows.
  659  */
  660 void
pccbb_chipinit(sc)
  662         struct pccbb_softc *sc;
  663 {
pci_chipset_tag_t pc = sc->sc_pc;
pcitag_t tag = sc->sc_tag;
pcireg_t reg;
  668         /*
  669          * Set PCI command reg.
  670          * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip.
  671          */
reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
  673         /* I believe it is harmless. */
reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
PCI_COMMAND_MASTER_ENABLE);
pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg);
  678         /*
  679          * Set CardBus latency timer.
  680          */
reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG);
  682         if (PCI_CB_LATENCY(reg) < 0x20) {
reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT);
reg |= (0x20 << PCI_CB_LATENCY_SHIFT);
pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg);
  686         }
DPRINTF(("CardBus latency timer 0x%x (%x)\n",
PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG)));
  690         /*
  691          * Set PCI latency timer.
  692          */
reg = pci_conf_read(pc, tag, PCI_BHLC_REG);
  694         if (PCI_LATTIMER(reg) < 0x10) {
reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
reg |= (0x10 << PCI_LATTIMER_SHIFT);
pci_conf_write(pc, tag, PCI_BHLC_REG, reg);
  698         }
DPRINTF(("PCI latency timer 0x%x (%x)\n",
PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG)));
  702         /* Route functional interrupts to PCI. */
reg = pci_conf_read(pc, tag, PCI_BCR_INTR);
reg |= CB_BCR_INTR_IREQ_ENABLE;         /* disable PCI Intr */
reg |= CB_BCR_WRITE_POST_ENABLE;        /* enable write post */
reg |= CB_BCR_RESET_ENABLE;             /* assert reset */
pci_conf_write(pc, tag, PCI_BCR_INTR, reg);
  709         switch (sc->sc_chipset) {
  710         case CB_TI113X:
reg = pci_conf_read(pc, tag, PCI_CBCTRL);
  712                 /* This bit is shared, but may read as 0 on some chips, so set
  713                    it explicitly on both functions. */
reg |= PCI113X_CBCTRL_PCI_IRQ_ENA;
  715                 /* CSC intr enable */
reg |= PCI113X_CBCTRL_PCI_CSC;
  717                 /* functional intr prohibit | prohibit ISA routing */
reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK);
pci_conf_write(pc, tag, PCI_CBCTRL, reg);
  720                 break;
  722         case CB_TI12XX:
  723                 /*
  724                  * Some TI 12xx (and [14][45]xx) based pci cards
  725                  * sometimes have issues with the MFUNC register not
  726                  * being initialized due to a bad EEPROM on board.
  727                  * Laptops that this matters on have this register
  728                  * properly initialized.
  729                  *
  730                  * The TI125X parts have a different register.
  731                  */
reg = pci_conf_read(pc, tag, PCI12XX_MFUNC);
  733                 if (reg == 0) {
reg &= ~PCI12XX_MFUNC_PIN0;
reg |= PCI12XX_MFUNC_PIN0_INTA;
  736                         if ((pci_conf_read(pc, tag, PCI_SYSCTRL) &
PCI12XX_SYSCTRL_INTRTIE) == 0) {
reg &= ~PCI12XX_MFUNC_PIN1;
reg |= PCI12XX_MFUNC_PIN1_INTB;
  740                         }
pci_conf_write(pc, tag, PCI12XX_MFUNC, reg);
  742                 }
  743                 /* FALLTHROUGH */
  745         case CB_TI125X:
  746                 /*
  747                  * Disable zoom video.  Some machines initialize this
  748                  * improperly and experience has shown that this helps
  749                  * prevent strange behavior.
  750                  */
pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0);
reg = pci_conf_read(pc, tag, PCI_SYSCTRL);
reg |= PCI12XX_SYSCTRL_VCCPROT;
pci_conf_write(pc, tag, PCI_SYSCTRL, reg);
reg = pci_conf_read(pc, tag, PCI_CBCTRL);
reg |= PCI12XX_CBCTRL_CSC;
pci_conf_write(pc, tag, PCI_CBCTRL, reg);
  759                 break;
  761         case CB_TOPIC95B:
reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL);
reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL;
pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg);
reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL);
DPRINTF(("%s: topic slot ctrl reg 0x%x -> ",
sc->sc_dev.dv_xname, reg));
reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN |
TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS);
reg &= ~TOPIC_SLOT_CTRL_SWDETECT;
DPRINTF(("0x%x\n", reg));
pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg);
  774                 break;
  776         case CB_TOPIC97:
reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL);
DPRINTF(("%s: topic slot ctrl reg 0x%x -> ",
sc->sc_dev.dv_xname, reg));
reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN |
TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS);
reg &= ~TOPIC_SLOT_CTRL_SWDETECT;
reg |= TOPIC97_SLOT_CTRL_PCIINT;
reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP);
DPRINTF(("0x%x\n", reg));
pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg);
  788                 /* make sure to assert LV card support bits */
bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh,
  790                     0x800 + 0x3e, bus_space_read_1(sc->sc_base_memt,
sc->sc_base_memh, 0x800 + 0x3e) | 0x03);
  793                 /* Power on the controller if the BIOS didn't */
reg = pci_conf_read(pc, tag, TOPIC100_PMCSR);
  795                 if ((reg & TOPIC100_PMCSR_MASK) != TOPIC100_PMCSR_D0)
pci_conf_write(pc, tag, TOPIC100_PMCSR,
  797                             (reg & ~TOPIC100_PMCSR_MASK) | TOPIC100_PMCSR_D0);
  798                 break;
  800         case CB_OLDO2MICRO:
  801                 /*
  802                  * older bridges have problems with both read prefetch and
  803                  * write bursting depending on the combination of the chipset,
  804                  * bridge and the cardbus card. so disable them to be on the
  805                  * safe side. One example is O2Micro 6812 with Atheros AR5012
  806                  * chipsets
  807                  */
DPRINTF(("%s: old O2Micro bridge found\n",
sc->sc_dev.dv_xname, reg));
reg = pci_conf_read(pc, tag, O2MICRO_RESERVED1);
pci_conf_write(pc, tag, O2MICRO_RESERVED1, reg &
  812                     ~(O2MICRO_RES_READ_PREFETCH | O2MICRO_RES_WRITE_BURST));
reg = pci_conf_read(pc, tag, O2MICRO_RESERVED2);
pci_conf_write(pc, tag, O2MICRO_RESERVED2, reg &
  815                     ~(O2MICRO_RES_READ_PREFETCH | O2MICRO_RES_WRITE_BURST));
  816                 break;
  817         }
  819         /* Close all memory and I/O windows. */
pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff);
pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0);
pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff);
pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0);
pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff);
pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0);
pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff);
pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0);
  829         /* reset 16-bit pcmcia bus */
bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh,
  831             0x800 + PCIC_INTR,
bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh,
  833                 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET);
  835         /* turn off power */
pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V);
  837 }
  842 /*
  843  * void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc,
  844  *                                       struct pcmciabus_attach_args *paa)
  845  *
  846  *   This function attaches 16-bit PCcard bus.
  847  */
  848 void
pccbb_pcmcia_attach_setup(sc, paa)
  850         struct pccbb_softc *sc;
  851         struct pcmciabus_attach_args *paa;
  852 {
  853         struct pcic_handle *ph = &sc->sc_pcmcia_h;
rbus_tag_t rb;
  856         /* initialize pcmcia part in pccbb_softc */
ph->ph_parent = (struct device *)sc;
ph->sock = sc->sc_function;
ph->flags = 0;
ph->shutdown = 0;
ph->ih_irq = sc->sc_intrline;
ph->ph_bus_t = sc->sc_base_memt;
ph->ph_bus_h = sc->sc_base_memh;
ph->ph_read = pccbb_pcmcia_read;
ph->ph_write = pccbb_pcmcia_write;
sc->sc_pct = &pccbb_pcmcia_funcs;
  868         /*
  869          * We need to do a few things here:
  870          * 1) Disable routing of CSC and functional interrupts to ISA IRQs by
  871          *    setting the IRQ numbers to 0.
  872          * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable
  873          *    routing of CSC interrupts (e.g. card removal) to PCI while in
  874          *    PCMCIA mode.  We just leave this set all the time.
  875          * 3) Enable card insertion/removal interrupts in case the chip also
  876          *    needs that while in PCMCIA mode.
  877          * 4) Clear any pending CSC interrupt.
  878          */
Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE | PCIC_INTR_RESET);
  880         if (sc->sc_chipset == CB_TI113X) {
Pcic_write(ph, PCIC_CSC_INTR, 0);
  882         } else {
Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE);
Pcic_read(ph, PCIC_CSC);
  885         }
  887         /* initialize pcmcia bus attachment */
paa->paa_busname = "pcmcia";
paa->pct = sc->sc_pct;
paa->pch = ph;
paa->iobase = 0;               /* I don't use them */
paa->iosize = 0;
rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot;
paa->iobase = rb->rb_start + rb->rb_offset;
paa->iosize = rb->rb_end - rb->rb_start;
  897         return;
  898 }
  900 #if 0
  901 void
pccbb_pcmcia_attach_card(ph)
  903         struct pcic_handle *ph;
  904 {
  905         if (ph->flags & PCIC_FLAG_CARDP) {
panic("pccbb_pcmcia_attach_card: already attached");
  907         }
  909         /* call the MI attach function */
pcmcia_card_attach(ph->pcmcia);
ph->flags |= PCIC_FLAG_CARDP;
  913 }
  915 void
pccbb_pcmcia_detach_card(ph, flags)
  917         struct pcic_handle *ph;
  918         int flags;
  919 {
  920         if (!(ph->flags & PCIC_FLAG_CARDP)) {
panic("pccbb_pcmcia_detach_card: already detached");
  922         }
ph->flags &= ~PCIC_FLAG_CARDP;
  926         /* call the MI detach function */
pcmcia_card_detach(ph->pcmcia, flags);
  928 }
  929 #endif
  931 /*
  932  * int pccbbintr(arg)
  933  *    void *arg;
  934  *   This routine handles the interrupt from Yenta PCI-CardBus bridge
  935  *   itself.
  936  */
  937 int
pccbbintr(arg)
  939         void *arg;
  940 {
  941         struct pccbb_softc *sc = (struct pccbb_softc *)arg;
u_int32_t sockevent, sockstate;
bus_space_tag_t memt = sc->sc_base_memt;
bus_space_handle_t memh = sc->sc_base_memh;
  945         struct pcic_handle *ph = &sc->sc_pcmcia_h;
  947         if (!sc->sc_ints_on)
  948                 return 0;
sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT);
bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent);
Pcic_read(ph, PCIC_CSC);
  954         if (sockevent == 0) {
  955                 /* This intr is not for me: it may be for my child devices. */
  956                 if (sc->sc_pil_intr_enable) {
  957                         return pccbbintr_function(sc);
  958                 } else {
  959                         return 0;
  960                 }
  961         }
  963         if (sockevent & CB_SOCKET_EVENT_CD) {
sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT);
  965                 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) {
  966                         /* A card should be removed. */
  967                         if (sc->sc_flags & CBB_CARDEXIST) {
DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname,
sockevent));
DPRINTF((" card removed, 0x%08x\n", sockstate));
sc->sc_flags &= ~CBB_CARDEXIST;
  972                                 if (sc->sc_csc->sc_status &
CARDSLOT_STATUS_CARD_16) {
  974 #if 0
  975                                         struct pcic_handle *ph =
  976                                             &sc->sc_pcmcia_h;
pcmcia_card_deactivate(ph->pcmcia);
pccbb_pcmcia_socket_disable(ph);
pccbb_pcmcia_detach_card(ph,
DETACH_FORCE);
  982 #endif
cardslot_event_throw(sc->sc_csc,
CARDSLOT_EVENT_REMOVAL_16);
  985                                 } else if (sc->sc_csc->sc_status &
CARDSLOT_STATUS_CARD_CB) {
  987                                         /* Cardbus intr removed */
cardslot_event_throw(sc->sc_csc,
CARDSLOT_EVENT_REMOVAL_CB);
  990                                 }
  991                         }
  992                 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) &&
  993                     /*
  994                      * The pccbbintr may called from powerdown hook when
  995                      * the system resumed, to detect the card
  996                      * insertion/removal during suspension.
  997                      */
  998                     (sc->sc_flags & CBB_CARDEXIST) == 0) {
  999                         if (sc->sc_flags & CBB_INSERTING) {
timeout_del(&sc->sc_ins_tmo);
 1001                         }
timeout_add(&sc->sc_ins_tmo, hz / 10);
sc->sc_flags |= CBB_INSERTING;
 1004                 }
 1005         }
 1007         return (1);
 1008 }
 1010 /*
 1011  * int pccbbintr_function(struct pccbb_softc *sc)
 1012  *
 1013  *    This function calls each interrupt handler registered at the
 1014  *    bridge.  The interrupt handlers are called in registered order.
 1015  */
 1016 int
pccbbintr_function(sc)
 1018         struct pccbb_softc *sc;
 1019 {
 1020         int retval = 0, val;
 1021         struct pccbb_intrhand_list *pil;
 1022         int s, splchanged;
 1024         for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) {
 1025                 /*
 1026                  * XXX priority change.  gross.  I use if-else
 1027                  * sentense instead of switch-case sentense because of
 1028                  * avoiding duplicate case value error.  More than one
 1029                  * IPL_XXX use same value.  It depends on
 1030                  * implementation.
 1031                  */
splchanged = 1;
 1033 #if 0
 1034                 if (pil->pil_level == IPL_SERIAL) {
s = splserial();
 1036                 } else if (pil->pil_level == IPL_HIGH) {
 1037 #endif
 1038                 if (pil->pil_level == IPL_HIGH) {
s = splhigh();
 1040                 } else if (pil->pil_level == IPL_CLOCK) {
s = splclock();
 1042                 } else if (pil->pil_level == IPL_AUDIO) {
s = splaudio();
 1044                 } else if (pil->pil_level == IPL_VM) {
s = splvm();
 1046                 } else if (pil->pil_level == IPL_TTY) {
s = spltty();
 1048 #if 0
 1049                 } else if (pil->pil_level == IPL_SOFTSERIAL) {
s = splsoftserial();
 1051 #endif
 1052                 } else if (pil->pil_level == IPL_NET) {
s = splnet();
 1054                 } else {
splchanged = 0;
 1056                         /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */
 1057                 }
val = (*pil->pil_func)(pil->pil_arg);
 1060                 if (val != 0)
pil->pil_count.ec_count++;
 1063                 if (splchanged != 0) {
splx(s);
 1065                 }
retval = retval == 1 ? 1 :
retval == 0 ? val : val != 0 ? val : retval;
 1069         }
 1071         return retval;
 1072 }
 1074 void
pci113x_insert(arg)
 1076         void *arg;
 1077 {
 1078         struct pccbb_softc *sc = (struct pccbb_softc *)arg;
u_int32_t sockevent, sockstate;
sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh,
CB_SOCKET_EVENT);
sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh,
CB_SOCKET_STAT);
 1086         if (0 == (sockstate & CB_SOCKET_STAT_CD)) {     /* card exist */
DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent));
DPRINTF((" card inserted, 0x%08x\n", sockstate));
sc->sc_flags |= CBB_CARDEXIST;
 1090                 /* call pccard interrupt handler here */
 1091                 if (sockstate & CB_SOCKET_STAT_16BIT) {
 1092                         /* 16-bit card found */
 1093 /*      pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */
cardslot_event_throw(sc->sc_csc,
CARDSLOT_EVENT_INSERTION_16);
 1096                 } else if (sockstate & CB_SOCKET_STAT_CB) {
 1097                         /* cardbus card found */
 1098 /*      cardbus_attach_card(sc->sc_csc); */
cardslot_event_throw(sc->sc_csc,
CARDSLOT_EVENT_INSERTION_CB);
 1101                 } else {
 1102                         /* who are you? */
 1103                 }
 1104         } else {
timeout_add(&sc->sc_ins_tmo, hz / 10);
 1106         }
 1107 }
 1109 #define PCCBB_PCMCIA_OFFSET 0x800
u_int8_t
pccbb_pcmcia_read(ph, reg)
 1112         struct pcic_handle *ph;
 1113         int reg;
 1114 {
bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h,
PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ);
 1118         return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h,
PCCBB_PCMCIA_OFFSET + reg);
 1120 }
 1122 void
pccbb_pcmcia_write(ph, reg, val)
 1124         struct pcic_handle *ph;
 1125         int reg;
u_int8_t val;
 1127 {
bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h,
PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE);
bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg,
val);
 1133 }
 1135 /*
 1136  * int pccbb_ctrl(cardbus_chipset_tag_t, int)
 1137  */
 1138 int
pccbb_ctrl(ct, command)
cardbus_chipset_tag_t ct;
 1141         int command;
 1142 {
 1143         struct pccbb_softc *sc = (struct pccbb_softc *)ct;
 1145         switch (command) {
 1146         case CARDBUS_CD:
 1147                 if (2 == pccbb_detect_card(sc)) {
 1148                         int retval = 0;
 1149                         int status = cb_detect_voltage(sc);
 1150                         if (PCCARD_VCC_5V & status) {
retval |= CARDBUS_5V_CARD;
 1152                         }
 1153                         if (PCCARD_VCC_3V & status) {
retval |= CARDBUS_3V_CARD;
 1155                         }
 1156                         if (PCCARD_VCC_XV & status) {
retval |= CARDBUS_XV_CARD;
 1158                         }
 1159                         if (PCCARD_VCC_YV & status) {
retval |= CARDBUS_YV_CARD;
 1161                         }
 1162                         return retval;
 1163                 } else {
 1164                         return 0;
 1165                 }
 1166                 break;
 1167         case CARDBUS_RESET:
 1168                 return cb_reset(sc);
 1169                 break;
 1170         case CARDBUS_IO_ENABLE:       /* fallthrough */
 1171         case CARDBUS_IO_DISABLE:      /* fallthrough */
 1172         case CARDBUS_MEM_ENABLE:      /* fallthrough */
 1173         case CARDBUS_MEM_DISABLE:     /* fallthrough */
 1174         case CARDBUS_BM_ENABLE:       /* fallthrough */
 1175         case CARDBUS_BM_DISABLE:      /* fallthrough */
 1176                 return pccbb_cardenable(sc, command);
 1177                 break;
 1178         }
 1180         return 0;
 1181 }
 1183 /*
 1184  * int pccbb_power(cardbus_chipset_tag_t, int)
 1185  *   This function returns true when it succeeds and returns false when
 1186  *   it fails.
 1187  */
 1188 int
pccbb_power(ct, command)
cardbus_chipset_tag_t ct;
 1191         int command;
 1192 {
 1193         struct pccbb_softc *sc = (struct pccbb_softc *)ct;
u_int32_t status, sock_ctrl;
bus_space_tag_t memt = sc->sc_base_memt;
bus_space_handle_t memh = sc->sc_base_memh;
DPRINTF(("pccbb_power: %s and %s [%x]\n",
 1200             (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" :
 1201             (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" :
 1202             (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" :
 1203             (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" :
 1204             (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" :
 1205             (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" :
 1206             "UNKNOWN",
 1207             (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" :
 1208             (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" :
 1209             (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" :
 1210             (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" :
 1211             "UNKNOWN", command));
status = bus_space_read_4(memt, memh, CB_SOCKET_STAT);
sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL);
 1216         switch (command & CARDBUS_VCCMASK) {
 1217         case CARDBUS_VCC_UC:
 1218                 break;
 1219         case CARDBUS_VCC_5V:
 1220                 if (CB_SOCKET_STAT_5VCARD & status) {   /* check 5 V card */
sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK;
sock_ctrl |= CB_SOCKET_CTRL_VCC_5V;
 1223                 } else {
printf("%s: BAD voltage request: no 5 V card\n",
sc->sc_dev.dv_xname);
 1226                 }
 1227                 break;
 1228         case CARDBUS_VCC_3V:
 1229                 if (CB_SOCKET_STAT_3VCARD & status) {
sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK;
sock_ctrl |= CB_SOCKET_CTRL_VCC_3V;
 1232                 } else {
printf("%s: BAD voltage request: no 3.3 V card\n",
sc->sc_dev.dv_xname);
 1235                 }
 1236                 break;
 1237         case CARDBUS_VCC_0V:
sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK;
 1239                 break;
 1240         default:
 1241                 return 0;              /* power NEVER changed */
 1242                 break;
 1243         }
 1245         switch (command & CARDBUS_VPPMASK) {
 1246         case CARDBUS_VPP_UC:
 1247                 break;
 1248         case CARDBUS_VPP_0V:
sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK;
 1250                 break;
 1251         case CARDBUS_VPP_VCC:
sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK;
sock_ctrl |= ((sock_ctrl >> 4) & 0x07);
 1254                 break;
 1255         case CARDBUS_VPP_12V:
sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK;
sock_ctrl |= CB_SOCKET_CTRL_VPP_12V;
 1258                 break;
 1259         }
 1261 #if 0
DPRINTF(("sock_ctrl: %x\n", sock_ctrl));
 1263 #endif
bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl);
status = bus_space_read_4(memt, memh, CB_SOCKET_STAT);
 1267         if (status & CB_SOCKET_STAT_BADVCC) {   /* bad Vcc request */
printf
 1269                     ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n",
sc->sc_dev.dv_xname, sock_ctrl, status);
DPRINTF(("pccbb_power: %s and %s [%x]\n",
 1272                     (command & CARDBUS_VCCMASK) ==
CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command &
CARDBUS_VCCMASK) ==
CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command &
CARDBUS_VCCMASK) ==
CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command &
CARDBUS_VCCMASK) ==
CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command &
CARDBUS_VCCMASK) ==
CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command &
CARDBUS_VCCMASK) ==
CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN",
 1284                     (command & CARDBUS_VPPMASK) ==
CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command &
CARDBUS_VPPMASK) ==
CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command &
CARDBUS_VPPMASK) ==
CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command &
CARDBUS_VPPMASK) ==
CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command));
 1292 #if 0
 1293                 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) {
u_int32_t force =
bus_space_read_4(memt, memh, CB_SOCKET_FORCE);
 1296                         /* Reset Bad Vcc request */
force &= ~CB_SOCKET_FORCE_BADVCC;
bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force);
printf("new status 0x%x\n", bus_space_read_4(memt, memh,
CB_SOCKET_STAT));
 1301                         return 1;
 1302                 }
 1303 #endif
 1304                 return 0;
 1305         }
 1307         /*
 1308          * XXX delay 300 ms: though the standard defines that the Vcc set-up
 1309          * time is 20 ms, some PC-Card bridge requires longer duration.
 1310          */
delay(300 * 1000);
 1313         return 1;                      /* power changed correctly */
 1314 }
 1316 #if defined CB_PCMCIA_POLL
 1317 struct cb_poll_str {
 1318         void *arg;
 1319         int (*func)(void *);
 1320         int level;
pccard_chipset_tag_t ct;
 1322         int count;
 1323 };
 1325 static struct cb_poll_str cb_poll[10];
 1326 static int cb_poll_n = 0;
 1327 static struct timeout cb_poll_timeout;
 1329 void cb_pcmcia_poll(void *arg);
 1331 void
cb_pcmcia_poll(arg)
 1333         void *arg;
 1334 {
 1335         struct cb_poll_str *poll = arg;
 1336         struct cbb_pcmcia_softc *psc = (void *)poll->ct->v;
 1337         struct pccbb_softc *sc = psc->cpc_parent;
 1338         int s;
u_int32_t spsr;                /* socket present-state reg */
timeout_set(&cb_poll_timeout, cb_pcmcia_poll, arg);
timeout_add(&cb_poll_timeout, hz / 10);
 1343         switch (poll->level) {
 1344         case IPL_NET:
s = splnet();
 1346                 break;
 1347         case IPL_BIO:
s = splbio();
 1349                 break;
 1350         case IPL_TTY:                  /* fallthrough */
 1351         default:
s = spltty();
 1353                 break;
 1354         }
spsr =
bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh,
CB_SOCKET_STAT);
 1360 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2
 1361         if (!(spsr & 0x40)) {          /* CINT low */
 1362 #else
 1363         if (1) {
 1364 #endif
 1365                 if ((*poll->func) (poll->arg) == 1) {
 1366                         ++poll->count;
printf("intr: reported from poller, 0x%x\n", spsr);
 1368 #if defined LEVEL2
 1369                 } else {
printf("intr: miss! 0x%x\n", spsr);
 1371 #endif
 1372                 }
 1373         }
splx(s);
 1375 }
 1376 #endif /* defined CB_PCMCIA_POLL */
 1378 /*
 1379  * int pccbb_detect_card(struct pccbb_softc *sc)
 1380  *   return value:  0 if no card exists.
 1381  *                  1 if 16-bit card exists.
 1382  *                  2 if cardbus card exists.
 1383  */
 1384 int
pccbb_detect_card(sc)
 1386         struct pccbb_softc *sc;
 1387 {
bus_space_handle_t base_memh = sc->sc_base_memh;
bus_space_tag_t base_memt = sc->sc_base_memt;
u_int32_t sockstat =
bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT);
 1392         int retval = 0;
 1394         /*
 1395          * The SCM Microsystems TI1225-based PCI-CardBus dock card that
 1396          * ships with some Lucent WaveLAN cards has only one physical slot
 1397          * but OpenBSD probes two. The phantom card in the second slot can
 1398          * be ignored by punting on unsupported voltages.
 1399          */
 1400         if (sockstat & CB_SOCKET_STAT_XVCARD)
 1401                 return 0;
 1403         /* CD1 and CD2 asserted */
 1404         if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) {
 1405                 /* card must be present */
 1406                 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) {
 1407                         /* NOTACARD DEASSERTED */
 1408                         if (CB_SOCKET_STAT_CB & sockstat) {
 1409                                 /* CardBus mode */
retval = 2;
 1411                         } else if (CB_SOCKET_STAT_16BIT & sockstat) {
 1412                                 /* 16-bit mode */
retval = 1;
 1414                         }
 1415                 }
 1416         }
 1417         return retval;
 1418 }
 1420 /*
 1421  * int cb_reset(struct pccbb_softc *sc)
 1422  *   This function resets CardBus card.
 1423  */
 1424 int
cb_reset(sc)
 1426         struct pccbb_softc *sc;
 1427 {
 1428         /*
 1429          * Reset Assert at least 20 ms
 1430          * Some machines request longer duration.
 1431          */
 1432         int reset_duration =
 1433             (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000);
u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR);
 1436         /* Reset bit Assert (bit 6 at 0x3E) */
bcr |= CB_BCR_RESET_ENABLE;
pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr);
delay(reset_duration);
 1441         if (CBB_CARDEXIST & sc->sc_flags) {     /* A card exists.  Reset it! */
 1442                 /* Reset bit Deassert (bit 6 at 0x3E) */
bcr &= ~CB_BCR_RESET_ENABLE;
pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr);
delay(reset_duration);
 1446         }
 1447         /* No card found on the slot. Keep Reset. */
 1448         return 1;
 1449 }
 1451 /*
 1452  * int cb_detect_voltage(struct pccbb_softc *sc)
 1453  *  This function detect card Voltage.
 1454  */
 1455 int
cb_detect_voltage(sc)
 1457         struct pccbb_softc *sc;
 1458 {
u_int32_t psr;                 /* socket present-state reg */
bus_space_tag_t iot = sc->sc_base_memt;
bus_space_handle_t ioh = sc->sc_base_memh;
 1462         int vol = PCCARD_VCC_UKN;      /* set 0 */
psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT);
 1466         if (0x400u & psr) {
vol |= PCCARD_VCC_5V;
 1468         }
 1469         if (0x800u & psr) {
vol |= PCCARD_VCC_3V;
 1471         }
 1473         return vol;
 1474 }
 1476 int
cbbprint(aux, pcic)
 1478         void *aux;
 1479         const char *pcic;
 1480 {
 1481 /*
 1482   struct cbslot_attach_args *cba = aux;
 1483 
 1484   if (cba->cba_slot >= 0) {
 1485     printf(" slot %d", cba->cba_slot);
 1486   }
 1487 */
 1488         return UNCONF;
 1489 }
 1491 /*
 1492  * int pccbb_cardenable(struct pccbb_softc *sc, int function)
 1493  *   This function enables and disables the card
 1494  */
 1495 int
pccbb_cardenable(sc, function)
 1497         struct pccbb_softc *sc;
 1498         int function;
 1499 {
u_int32_t command =
pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);
DPRINTF(("pccbb_cardenable:"));
 1504         switch (function) {
 1505         case CARDBUS_IO_ENABLE:
command |= PCI_COMMAND_IO_ENABLE;
 1507                 break;
 1508         case CARDBUS_IO_DISABLE:
command &= ~PCI_COMMAND_IO_ENABLE;
 1510                 break;
 1511         case CARDBUS_MEM_ENABLE:
command |= PCI_COMMAND_MEM_ENABLE;
 1513                 break;
 1514         case CARDBUS_MEM_DISABLE:
command &= ~PCI_COMMAND_MEM_ENABLE;
 1516                 break;
 1517         case CARDBUS_BM_ENABLE:
command |= PCI_COMMAND_MASTER_ENABLE;
 1519                 break;
 1520         case CARDBUS_BM_DISABLE:
command &= ~PCI_COMMAND_MASTER_ENABLE;
 1522                 break;
 1523         default:
 1524                 return 0;
 1525         }
pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command);
DPRINTF((" command reg 0x%x\n", command));
 1529         return 1;
 1530 }
 1532 /*
 1533  * void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct,
 1534  *                                      int irq,
 1535  *                                      int level,
 1536  *                                      int (* func)(void *),
 1537  *                                      void *arg,
 1538  *                                      const char *name)
 1539  *
 1540  *   This function registers an interrupt handler at the bridge, in
 1541  *   order not to call the interrupt handlers of child devices when
 1542  *   a card-deletion interrupt occurs.
 1543  *
 1544  *   The arguments irq is not used because pccbb selects intr vector.
 1545  */
 1546 void *
pccbb_cb_intr_establish(ct, irq, level, func, arg, name)
cardbus_chipset_tag_t ct;
 1549         int irq, level;
 1550         int (*func)(void *);
 1551         void *arg;
 1552         const char *name;
 1553 {
 1554         struct pccbb_softc *sc = (struct pccbb_softc *)ct;
 1556         return pccbb_intr_establish(sc, irq, level, func, arg, name);
 1557 }
 1560 /*
 1561  * void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct,
 1562  *                                         void *ih)
 1563  *
 1564  *   This function removes an interrupt handler pointed by ih.
 1565  */
 1566 void
pccbb_cb_intr_disestablish(ct, ih)
cardbus_chipset_tag_t ct;
 1569         void *ih;
 1570 {
 1571         struct pccbb_softc *sc = (struct pccbb_softc *)ct;
pccbb_intr_disestablish(sc, ih);
 1574 }
 1577 /*
 1578  * void *pccbb_intr_establish(struct pccbb_softc *sc,
 1579  *                                   int irq,
 1580  *                                   int level,
 1581  *                                   int (* func)(void *),
 1582  *                                   void *arg,
 1583  *                                   const char *name)
 1584  *
 1585  *   This function registers an interrupt handler at the bridge, in
 1586  *   order not to call the interrupt handlers of child devices when
 1587  *   a card-deletion interrupt occurs.
 1588  *
 1589  *   The arguments irq and level are not used.
 1590  */
 1591 void *
pccbb_intr_establish(sc, irq, level, func, arg, name)
 1593         struct pccbb_softc *sc;
 1594         int irq, level;
 1595         int (*func)(void *);
 1596         void *arg;
 1597         const char *name;
 1598 {
 1599         struct pccbb_intrhand_list *pil, *newpil;
pcireg_t reg;
DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil));
 1604         if (sc->sc_pil == NULL) {
 1605                 /* initialize bridge intr routing */
reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR);
reg &= ~CB_BCR_INTR_IREQ_ENABLE;
pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg);
 1610                 switch (sc->sc_chipset) {
 1611                 case CB_TI113X:
reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL);
 1613                         /* functional intr enabled */
reg |= PCI113X_CBCTRL_PCI_INTR;
pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg);
 1616                         break;
 1617                 default:
 1618                         break;
 1619                 }
 1620         }
 1622         /*
 1623          * Allocate a room for interrupt handler structure.
 1624          */
newpil = (struct pccbb_intrhand_list *)
malloc(sizeof(struct pccbb_intrhand_list), M_DEVBUF, M_WAITOK);
newpil->pil_func = func;
newpil->pil_arg = arg;
newpil->pil_level = level;
evcount_attach(&newpil->pil_count, name, &sc->sc_intrline,
 1632             &evcount_intr);
newpil->pil_next = NULL;
 1635         if (sc->sc_pil == NULL) {
sc->sc_pil = newpil;
 1637         } else {
 1638                 for (pil = sc->sc_pil; pil->pil_next != NULL;
pil = pil->pil_next);
pil->pil_next = newpil;
 1641         }
DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil));
 1645         return newpil;
 1646 }
 1648 /*
 1649  * void *pccbb_intr_disestablish(struct pccbb_softc *sc,
 1650  *                                      void *ih)
 1651  *
 1652  *   This function removes an interrupt handler pointed by ih.
 1653  */
 1654 void
pccbb_intr_disestablish(sc, ih)
 1656         struct pccbb_softc *sc;
 1657         void *ih;
 1658 {
 1659         struct pccbb_intrhand_list *pil, **pil_prev;
pcireg_t reg;
DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil));
pil_prev = &sc->sc_pil;
 1666         for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) {
 1667                 if (pil == ih) {
evcount_detach(&pil->pil_count);
 1669                         *pil_prev = pil->pil_next;
free(pil, M_DEVBUF);
DPRINTF(("pccbb_intr_disestablish frees one pil\n"));
 1672                         break;
 1673                 }
pil_prev = &pil->pil_next;
 1675         }
 1677         if (sc->sc_pil == NULL) {
 1678                 /* No interrupt handlers */
DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n"));
 1682                 /* stop routing PCI intr */
reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR);
reg |= CB_BCR_INTR_IREQ_ENABLE;
pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg);
 1687                 switch (sc->sc_chipset) {
 1688                 case CB_TI113X:
reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL);
 1690                         /* functional intr disabled */
reg &= ~PCI113X_CBCTRL_PCI_INTR;
pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg);
 1693                         break;
 1694                 default:
 1695                         break;
 1696                 }
 1697         }
 1698 }
 1700 #if defined SHOW_REGS
 1701 void
cb_show_regs(pc, tag, memt, memh)
pci_chipset_tag_t pc;
pcitag_t tag;
bus_space_tag_t memt;
bus_space_handle_t memh;
 1707 {
 1708         int i;
printf("PCI config regs:");
 1710         for (i = 0; i < 0x50; i += 4) {
 1711                 if (i % 16 == 0) {
printf("\n 0x%02x:", i);
 1713                 }
printf(" %08x", pci_conf_read(pc, tag, i));
 1715         }
 1716         for (i = 0x80; i < 0xb0; i += 4) {
 1717                 if (i % 16 == 0) {
printf("\n 0x%02x:", i);
 1719                 }
printf(" %08x", pci_conf_read(pc, tag, i));
 1721         }
 1723         if (memh == 0) {
printf("\n");
 1725                 return;
 1726         }
printf("\nsocket regs:");
 1729         for (i = 0; i <= 0x10; i += 0x04) {
printf(" %08x", bus_space_read_4(memt, memh, i));
 1731         }
printf("\nExCA regs:");
 1733         for (i = 0; i < 0x08; ++i) {
printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i));
 1735         }
printf("\n");
 1737         return;
 1738 }
 1739 #endif
 1741 /*
 1742  * cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc,
 1743  *                                    int busno, int devno, int function)
 1744  *   This is the function to make a tag to access config space of
 1745  *  a CardBus Card.  It works same as pci_conf_read.
 1746  */
cardbustag_t
pccbb_make_tag(cc, busno, devno, function)
cardbus_chipset_tag_t cc;
 1750         int busno, devno, function;
 1751 {
 1752         struct pccbb_softc *sc = (struct pccbb_softc *)cc;
 1754         return pci_make_tag(sc->sc_pc, busno, devno, function);
 1755 }
 1757 void
pccbb_free_tag(cc, tag)
cardbus_chipset_tag_t cc;
cardbustag_t tag;
 1761 {
 1762 }
 1764 /*
 1765  * cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc,
 1766  *                                     cardbustag_t tag, int offset)
 1767  *   This is the function to read the config space of a CardBus Card.
 1768  *  It works same as pci_conf_read.
 1769  */
cardbusreg_t
pccbb_conf_read(cc, tag, offset)
cardbus_chipset_tag_t cc;
cardbustag_t tag;
 1774         int offset;                    /* register offset */
 1775 {
 1776         struct pccbb_softc *sc = (struct pccbb_softc *)cc;
 1778         return pci_conf_read(sc->sc_pc, tag, offset);
 1779 }
 1781 /*
 1782  * void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag,
 1783  *                              int offs, cardbusreg_t val)
 1784  *   This is the function to write the config space of a CardBus Card.
 1785  *  It works same as pci_conf_write.
 1786  */
 1787 void
pccbb_conf_write(cc, tag, reg, val)
cardbus_chipset_tag_t cc;
cardbustag_t tag;
 1791         int reg;                       /* register offset */
cardbusreg_t val;
 1793 {
 1794         struct pccbb_softc *sc = (struct pccbb_softc *)cc;
pci_conf_write(sc->sc_pc, tag, reg, val);
 1797 }
 1799 #if 0
 1800 int
 1801 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch,
bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask,
 1803     int speed, int flags,
bus_space_handle_t * iohp)
 1805 #endif
 1806 /*
 1807  * int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch,
 1808  *                                  bus_addr_t start, bus_size_t size,
 1809  *                                  bus_size_t align,
 1810  *                                  struct pcmcia_io_handle *pcihp
 1811  *
 1812  * This function only allocates I/O region for pccard. This function
 1813  * never maps the allocated region to pccard I/O area.
 1814  *
 1815  * XXX: The interface of this function is not very good, I believe.
 1816  */
 1817 int
pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp)
pcmcia_chipset_handle_t pch;
bus_addr_t start;              /* start address */
bus_size_t size;
bus_size_t align;
 1823         struct pcmcia_io_handle *pcihp;
 1824 {
 1825         struct pcic_handle *ph = (struct pcic_handle *)pch;
bus_addr_t ioaddr;
 1827         int flags = 0;
bus_space_tag_t iot;
bus_space_handle_t ioh;
bus_addr_t mask;
rbus_tag_t rb;
 1833         if (align == 0) {
align = size;          /* XXX: funny??? */
 1835         }
 1837         if (start != 0) {
 1838                 /* XXX: assume all card decode lower 10 bits by its hardware */
mask = 0x3ff;
 1840                 /* enforce to use only masked address */
start &= mask;
 1842         } else {
 1843                 /*
 1844                  * calculate mask:
 1845                  *  1. get the most significant bit of size (call it msb).
 1846                  *  2. compare msb with the value of size.
 1847                  *  3. if size is larger, shift msb left once.
 1848                  *  4. obtain mask value to decrement msb.
 1849                  */
bus_size_t size_tmp = size;
 1851                 int shifts = 0;
mask = 1;
 1854                 while (size_tmp) {
 1855                         ++shifts;
size_tmp >>= 1;
 1857                 }
mask = (1 << shifts);
 1859                 if (mask < size) {
mask <<= 1;
 1861                 }
mask--;
 1863         }
 1865         /*
 1866          * Allocate some arbitrary I/O space.
 1867          */
iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot;
rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot;
 1872         if (rbus_space_alloc(rb, start, size, mask, align, 0, &ioaddr, &ioh)) {
 1873                 return 1;
 1874         }
pcihp->iot = iot;
pcihp->ioh = ioh;
pcihp->addr = ioaddr;
pcihp->size = size;
pcihp->flags = flags;
 1882         return 0;
 1883 }
 1885 /*
 1886  * int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch,
 1887  *                                 struct pcmcia_io_handle *pcihp)
 1888  *
 1889  * This function only frees I/O region for pccard.
 1890  *
 1891  * XXX: The interface of this function is not very good, I believe.
 1892  */
 1893 void
pccbb_pcmcia_io_free(pch, pcihp)
pcmcia_chipset_handle_t pch;
 1896         struct pcmcia_io_handle *pcihp;
 1897 {
bus_space_handle_t ioh = pcihp->ioh;
bus_size_t size = pcihp->size;
 1901         struct pccbb_softc *sc =
 1902             (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent;
rbus_tag_t rb = sc->sc_rbus_iot;
rbus_space_free(rb, ioh, size, NULL);
 1906 }
 1908 /*
 1909  * int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width,
 1910  *                                bus_addr_t offset, bus_size_t size,
 1911  *                                struct pcmcia_io_handle *pcihp,
 1912  *                                int *windowp)
 1913  *
 1914  * This function maps the allocated I/O region to pccard. This function
 1915  * never allocates any I/O region for pccard I/O area.  I don't
 1916  * understand why the original authors of pcmciabus separated alloc and
 1917  * map.  I believe the two must be unite.
 1918  *
 1919  * XXX: no wait timing control?
 1920  */
 1921 int
pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp)
pcmcia_chipset_handle_t pch;
 1924         int width;
bus_addr_t offset;
bus_size_t size;
 1927         struct pcmcia_io_handle *pcihp;
 1928         int *windowp;
 1929 {
 1930         struct pcic_handle *ph = (struct pcic_handle *)pch;
bus_addr_t ioaddr = pcihp->addr + offset;
 1932         int i, win;
 1933 #if defined CBB_DEBUG
 1934         static char *width_names[] = { "dynamic", "io8", "io16" };
 1935 #endif
 1937         /* Sanity check I/O handle. */
 1939         if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) {
panic("pccbb_pcmcia_io_map iot is bogus");
 1941         }
 1943         /* XXX Sanity check offset/size. */
win = -1;
 1946         for (i = 0; i < PCIC_IO_WINS; i++) {
 1947                 if ((ph->ioalloc & (1 << i)) == 0) {
win = i;
ph->ioalloc |= (1 << i);
 1950                         break;
 1951                 }
 1952         }
 1954         if (win == -1) {
 1955                 return 1;
 1956         }
 1958         *windowp = win;
 1960         /* XXX this is pretty gross */
DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n",
win, width_names[width], (u_long) ioaddr, (u_long) size));
 1965         /* XXX wtf is this doing here? */
 1967 #if 0
printf(" port 0x%lx", (u_long) ioaddr);
 1969         if (size > 1) {
printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1);
 1971         }
 1972 #endif
ph->io[win].addr = ioaddr;
ph->io[win].size = size;
ph->io[win].width = width;
 1978         /* actual dirty register-value changing in the function below. */
pccbb_pcmcia_do_io_map(ph, win);
 1981         return 0;
 1982 }
 1984 /*
 1985  * void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win)
 1986  *
 1987  * This function changes register-value to map I/O region for pccard.
 1988  */
 1989 void
pccbb_pcmcia_do_io_map(ph, win)
 1991         struct pcic_handle *ph;
 1992         int win;
 1993 {
 1994         static u_int8_t pcic_iowidth[3] = {
PCIC_IOCTL_IO0_IOCS16SRC_CARD,
PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE |
PCIC_IOCTL_IO0_DATASIZE_8BIT,
PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE |
PCIC_IOCTL_IO0_DATASIZE_16BIT,
 2000         };
 2002 #define PCIC_SIA_START_LOW 0
 2003 #define PCIC_SIA_START_HIGH 1
 2004 #define PCIC_SIA_STOP_LOW 2
 2005 #define PCIC_SIA_STOP_HIGH 3
 2007         int regbase_win = 0x8 + win * 0x04;
u_int8_t ioctl, enable;
DPRINTF(
 2011             ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n",
win, (long)ph->io[win].addr, (long)ph->io[win].size,
ph->io[win].width * 8));
Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW,
ph->io[win].addr & 0xff);
Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH,
 2018             (ph->io[win].addr >> 8) & 0xff);
Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW,
 2021             (ph->io[win].addr + ph->io[win].size - 1) & 0xff);
Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH,
 2023             ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff);
ioctl = Pcic_read(ph, PCIC_IOCTL);
enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE);
 2027         switch (win) {
 2028         case 0:
ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT |
PCIC_IOCTL_IO0_IOCS16SRC_MASK |
PCIC_IOCTL_IO0_DATASIZE_MASK);
ioctl |= pcic_iowidth[ph->io[win].width];
enable |= PCIC_ADDRWIN_ENABLE_IO0;
 2034                 break;
 2035         case 1:
ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT |
PCIC_IOCTL_IO1_IOCS16SRC_MASK |
PCIC_IOCTL_IO1_DATASIZE_MASK);
ioctl |= (pcic_iowidth[ph->io[win].width] << 4);
enable |= PCIC_ADDRWIN_ENABLE_IO1;
 2041                 break;
 2042         }
Pcic_write(ph, PCIC_IOCTL, ioctl);
Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable);
 2045 #if defined CBB_DEBUG
 2046         {
u_int8_t start_low =
Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW);
u_int8_t start_high =
Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH);
u_int8_t stop_low =
Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW);
u_int8_t stop_high =
Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH);
printf
 2056                     (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n",
start_low, start_high, stop_low, stop_high, ioctl, enable);
 2058         }
 2059 #endif
 2060 }
 2062 /*
 2063  * void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win)
 2064  *
 2065  * This function unmaps I/O region.  No return value.
 2066  */
 2067 void
pccbb_pcmcia_io_unmap(pch, win)
pcmcia_chipset_handle_t pch;
 2070         int win;
 2071 {
 2072         struct pcic_handle *ph = (struct pcic_handle *)pch;
 2073         int reg;
 2075         if (win >= PCIC_IO_WINS || win < 0) {
panic("pccbb_pcmcia_io_unmap: window out of range");
 2077         }
reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE);
 2080         switch (win) {
 2081         case 0:
reg &= ~PCIC_ADDRWIN_ENABLE_IO0;
 2083                 break;
 2084         case 1:
reg &= ~PCIC_ADDRWIN_ENABLE_IO1;
 2086                 break;
 2087         }
Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg);
ph->ioalloc &= ~(1 << win);
 2091 }
 2093 /*
 2094  * void pccbb_pcmcia_wait_ready(struct pcic_handle *ph)
 2095  *
 2096  * This function enables the card.  All information is stored in
 2097  * the first argument, pcmcia_chipset_handle_t.
 2098  */
 2099 void
pccbb_pcmcia_wait_ready(ph)
 2101         struct pcic_handle *ph;
 2102 {
 2103         int i;
DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n",
Pcic_read(ph, PCIC_IF_STATUS)));
 2108         for (i = 0; i < 10000; i++) {
 2109                 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) {
 2110                         return;
 2111                 }
delay(500);
 2113 #ifdef CBB_DEBUG
 2114                 if ((i > 5000) && (i % 100 == 99))
printf(".");
 2116 #endif
 2117         }
 2119 #ifdef DIAGNOSTIC
printf("pcic_wait_ready: ready never happened, status = %02x\n",
Pcic_read(ph, PCIC_IF_STATUS));
 2122 #endif
 2123 }
 2125 /*
 2126  * void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch)
 2127  *
 2128  * This function enables the card.  All information is stored in
 2129  * the first argument, pcmcia_chipset_handle_t.
 2130  */
 2131 void
pccbb_pcmcia_socket_enable(pch)
pcmcia_chipset_handle_t pch;
 2134 {
 2135         struct pcic_handle *ph = (struct pcic_handle *)pch;
 2136         struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent;
 2137         int cardtype, win;
u_int8_t power, intr;
pcireg_t spsr;
 2140         int voltage;
 2142         /* this bit is mostly stolen from pcic_attach_card */
DPRINTF(("pccbb_pcmcia_socket_enable: "));
 2146         /* get card Vcc info */
spsr =
bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh,
CB_SOCKET_STAT);
 2151         if (spsr & CB_SOCKET_STAT_5VCARD) {
DPRINTF(("5V card\n"));
voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC;
 2154         } else if (spsr & CB_SOCKET_STAT_3VCARD) {
DPRINTF(("3V card\n"));
voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC;
 2157         } else {
printf("?V card, 0x%x\n", spsr);        /* XXX */
 2159                 return;
 2160         }
 2162         /* disable socket i/o: negate output enable bit */
power = 0;
Pcic_write(ph, PCIC_PWRCTL, power);
 2167         /* power down the socket to reset it, clear the card reset pin */
pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V);
 2171         /*
 2172          * wait 200ms until power fails (Tpf).  Then, wait 100ms since
 2173          * we are changing Vcc (Toff).
 2174          */
 2175         /* delay(300*1000); too much */
 2177         /* assert reset bit */
intr = Pcic_read(ph, PCIC_INTR);
intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK);
Pcic_write(ph, PCIC_INTR, intr);
 2182         /* power up the socket and output enable */
power = Pcic_read(ph, PCIC_PWRCTL);
power |= PCIC_PWRCTL_OE;
Pcic_write(ph, PCIC_PWRCTL, power);
pccbb_power(sc, voltage);
 2188         /*
 2189          * hold RESET at least 10us.
 2190          */
delay(10);
delay(2 * 1000);               /* XXX: TI1130 requires it. */
delay(20 * 1000);              /* XXX: TI1130 requires it. */
 2195         /* clear the reset flag */
intr |= PCIC_INTR_RESET;
Pcic_write(ph, PCIC_INTR, intr);
 2200         /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */
delay(20000);
 2204         /* wait for the chip to finish initializing */
pccbb_pcmcia_wait_ready(ph);
 2208         /* zero out the address windows */
Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0);
 2212         /* set the card type */
cardtype = pcmcia_card_gettype(ph->pcmcia);
intr |= ((cardtype == PCMCIA_IFTYPE_IO) ?
PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM);
Pcic_write(ph, PCIC_INTR, intr);
DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n",
ph->ph_parent->dv_xname, ph->sock,
 2222             ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr));
 2224         /* reinstall all the memory and io mappings */
 2226         for (win = 0; win < PCIC_MEM_WINS; ++win) {
 2227                 if (ph->memalloc & (1 << win)) {
pccbb_pcmcia_do_mem_map(ph, win);
 2229                 }
 2230         }
 2232         for (win = 0; win < PCIC_IO_WINS; ++win) {
 2233                 if (ph->ioalloc & (1 << win)) {
pccbb_pcmcia_do_io_map(ph, win);
 2235                 }
 2236         }
 2237 }
 2239 /*
 2240  * void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph)
 2241  *
 2242  * This function disables the card.  All information is stored in
 2243  * the first argument, pcmcia_chipset_handle_t.
 2244  */
 2245 void
pccbb_pcmcia_socket_disable(pch)
pcmcia_chipset_handle_t pch;
 2248 {
 2249         struct pcic_handle *ph = (struct pcic_handle *)pch;
 2250         struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent;
u_int8_t power, intr;
DPRINTF(("pccbb_pcmcia_socket_disable\n"));
 2255         /* reset signal asserting... */
intr = Pcic_read(ph, PCIC_INTR);
intr &= ~(PCIC_INTR_CARDTYPE_MASK);
Pcic_write(ph, PCIC_INTR, intr);
delay(2 * 1000);
 2262         /* power down the socket */
power = Pcic_read(ph, PCIC_PWRCTL);
power &= ~PCIC_PWRCTL_OE;
Pcic_write(ph, PCIC_PWRCTL, power);
pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V);
 2267         /*
 2268          * wait 300ms until power fails (Tpf).
 2269          */
delay(300 * 1000);
 2271 }
 2273 /*
 2274  * int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph)
 2275  *
 2276  * This function detects whether a card is in the slot or not.
 2277  * If a card is inserted, return 1.  Otherwise, return 0.
 2278  */
 2279 int
pccbb_pcmcia_card_detect(pch)
pcmcia_chipset_handle_t pch;
 2282 {
 2283         struct pcic_handle *ph = (struct pcic_handle *)pch;
 2284         struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent;
DPRINTF(("pccbb_pcmcia_card_detect\n"));
 2287         return pccbb_detect_card(sc) == 1 ? 1 : 0;
 2288 }
 2290 #if 0
 2291 int
 2292 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch,
bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags,
bus_space_tag_t * memtp bus_space_handle_t * memhp)
 2295 #endif
 2296 /*
 2297  * int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch,
 2298  *                                   bus_size_t size,
 2299  *                                   struct pcmcia_mem_handle *pcmhp)
 2300  *
 2301  * This function only allocates memory region for pccard. This
 2302  * function never maps the allocated region to pccard memory area.
 2303  *
 2304  * XXX: Why the argument of start address is not in?
 2305  */
 2306 int
pccbb_pcmcia_mem_alloc(pch, size, pcmhp)
pcmcia_chipset_handle_t pch;
bus_size_t size;
 2310         struct pcmcia_mem_handle *pcmhp;
 2311 {
 2312         struct pcic_handle *ph = (struct pcic_handle *)pch;
bus_space_handle_t memh;
bus_addr_t addr;
bus_size_t sizepg;
 2316         struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent;
rbus_tag_t rb;
 2319         /* out of sc->memh, allocate as many pages as necessary */
 2321         /* convert size to PCIC pages */
 2322         /*
 2323          * This is not enough; when the requested region is on the page
 2324          * boundaries, this may calculate wrong result.
 2325          */
sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE;
 2327 #if 0
 2328         if (sizepg > PCIC_MAX_MEM_PAGES) {
 2329                 return 1;
 2330         }
 2331 #endif
 2333         if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) {
 2334                 return 1;
 2335         }
addr = 0;                      /* XXX gcc -Wuninitialized */
rb = sc->sc_rbus_memt;
 2340         if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE,
sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0,
 2342             &addr, &memh)) {
 2343                 return 1;
 2344         }
DPRINTF(
 2347             ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n",
addr, size, sizepg * PCIC_MEM_PAGESIZE));
pcmhp->memt = sc->sc_memt;
pcmhp->memh = memh;
pcmhp->addr = addr;
pcmhp->size = size;
pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE;
 2355         /* What is mhandle?  I feel it is very dirty and it must go trush. */
pcmhp->mhandle = 0;
 2357         /* No offset???  Funny. */
 2359         return 0;
 2360 }
 2362 /*
 2363  * void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch,
 2364  *                                   struct pcmcia_mem_handle *pcmhp)
 2365  *
 2366  * This function release the memory space allocated by the function
 2367  * pccbb_pcmcia_mem_alloc().
 2368  */
 2369 void
pccbb_pcmcia_mem_free(pch, pcmhp)
pcmcia_chipset_handle_t pch;
 2372         struct pcmcia_mem_handle *pcmhp;
 2373 {
 2374         struct pcic_handle *ph = (struct pcic_handle *)pch;
 2375         struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent;
rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL);
 2378 }
 2380 /*
 2381  * void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win)
 2382  *
 2383  * This function release the memory space allocated by the function
 2384  * pccbb_pcmcia_mem_alloc().
 2385  */
 2386 void
pccbb_pcmcia_do_mem_map(ph, win)
 2388         struct pcic_handle *ph;
 2389         int win;
 2390 {
 2391         int regbase_win;
bus_addr_t phys_addr;
bus_addr_t phys_end;
 2395 #define PCIC_SMM_START_LOW 0
 2396 #define PCIC_SMM_START_HIGH 1
 2397 #define PCIC_SMM_STOP_LOW 2
 2398 #define PCIC_SMM_STOP_HIGH 3
 2399 #define PCIC_CMA_LOW 4
 2400 #define PCIC_CMA_HIGH 5
u_int8_t start_low, start_high = 0;
u_int8_t stop_low, stop_high;
u_int8_t off_low, off_high;
u_int8_t mem_window;
 2406         int reg;
regbase_win = 0x10 + win * 0x08;
phys_addr = ph->mem[win].addr;
phys_end = phys_addr + ph->mem[win].size;
DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n",
phys_addr, phys_end, ph->mem[win].offset));
 2416 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT
 2417 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8)
 2418 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12)
 2420         /* bit 19:12 */
start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff;
 2422         /* bit 23:20 and bit 7 on */
start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f)
 2424             | PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; /* bit 7 on */
 2425         /* bit 31:24, for 32-bit address */
mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff;
Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low);
Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high);
 2431         if (((struct pccbb_softc *)ph->
ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) {
Pcic_write(ph, 0x40 + win, mem_window);
 2434         }
stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff;
stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f)
 2438             | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */
 2439         /* XXX Geee, WAIT2!! Crazy!!  I must rewrite this routine. */
Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low);
Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high);
off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff;
off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8))
 2446             & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK)
 2447             | ((ph->mem[win].kind == PCMCIA_MEM_ATTR) ?
PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0);
Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low);
Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high);
reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE);
reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16);
Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg);
 2457 #if defined CBB_DEBUG
 2458         {
 2459                 int r1, r2, r3, r4, r5, r6, r7 = 0;
r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW);
r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH);
r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW);
r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH);
r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW);
r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH);
 2467                 if (((struct pccbb_softc *)(ph->
ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) {
r7 = Pcic_read(ph, 0x40 + win);
 2470                 }
DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x "
 2473                     "%02x%02x", win, r1, r2, r3, r4, r5, r6));
 2474                 if (((struct pccbb_softc *)(ph->
ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) {
DPRINTF((" %02x", r7));
 2477                 }
DPRINTF(("\n"));
 2479         }
 2480 #endif
 2481 }
 2483 /*
 2484  * int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind,
 2485  *                                 bus_addr_t card_addr, bus_size_t size,
 2486  *                                 struct pcmcia_mem_handle *pcmhp,
 2487  *                                 bus_size_t *offsetp, int *windowp)
 2488  *
 2489  * This function maps memory space allocated by the function
 2490  * pccbb_pcmcia_mem_alloc().
 2491  */
 2492 int
pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp)
pcmcia_chipset_handle_t pch;
 2495         int kind;
bus_addr_t card_addr;
bus_size_t size;
 2498         struct pcmcia_mem_handle *pcmhp;
bus_size_t *offsetp;
 2500         int *windowp;
 2501 {
 2502         struct pcic_handle *ph = (struct pcic_handle *)pch;
bus_addr_t busaddr;
 2504         long card_offset;
 2505         int win;
 2507         for (win = 0; win < PCIC_MEM_WINS; ++win) {
 2508                 if ((ph->memalloc & (1 << win)) == 0) {
ph->memalloc |= (1 << win);
 2510                         break;
 2511                 }
 2512         }
 2514         if (win == PCIC_MEM_WINS) {
 2515                 return 1;
 2516         }
 2518         *windowp = win;
 2520         /* XXX this is pretty gross */
 2522         if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) {
panic("pccbb_pcmcia_mem_map memt is bogus");
 2524         }
busaddr = pcmhp->addr;
 2528         /*
 2529          * compute the address offset to the pcmcia address space for the
 2530          * pcic.  this is intentionally signed.  The masks and shifts below
 2531          * will cause TRT to happen in the pcic registers.  Deal with making
 2532          * sure the address is aligned, and return the alignment offset.
 2533          */
 2535         *offsetp = card_addr % PCIC_MEM_PAGESIZE;
card_addr -= *offsetp;
DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr "
 2539             "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size,
 2540             (u_long) card_addr));
 2542         /*
 2543          * include the offset in the size, and decrement size by one, since
 2544          * the hw wants start/stop
 2545          */
size += *offsetp - 1;
card_offset = (((long)card_addr) - ((long)busaddr));
ph->mem[win].addr = busaddr;
ph->mem[win].size = size;
ph->mem[win].offset = card_offset;
ph->mem[win].kind = kind;
pccbb_pcmcia_do_mem_map(ph, win);
 2557         return 0;
 2558 }
 2560 /*
 2561  * int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch,
 2562  *                                   int window)
 2563  *
 2564  * This function unmaps memory space which mapped by the function
 2565  * pccbb_pcmcia_mem_map().
 2566  */
 2567 void
pccbb_pcmcia_mem_unmap(pch, window)
pcmcia_chipset_handle_t pch;
 2570         int window;
 2571 {
 2572         struct pcic_handle *ph = (struct pcic_handle *)pch;
 2573         int reg;
 2575         if (window >= PCIC_MEM_WINS) {
panic("pccbb_pcmcia_mem_unmap: window out of range");
 2577         }
reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE);
reg &= ~(1 << window);
Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg);
ph->memalloc &= ~(1 << window);
 2584 }
 2586 #if defined PCCBB_PCMCIA_POLL
 2587 struct pccbb_poll_str {
 2588         void *arg;
 2589         int (*func)(void *);
 2590         int level;
 2591         struct pcic_handle *ph;
 2592         int count;
 2593         int num;
 2594 };
 2596 static struct pccbb_poll_str pccbb_poll[10];
 2597 static int pccbb_poll_n = 0;
 2598 static struct timeout pccbb_poll_timeout;
 2600 void pccbb_pcmcia_poll(void *arg);
 2602 void
pccbb_pcmcia_poll(arg)
 2604         void *arg;
 2605 {
 2606         struct pccbb_poll_str *poll = arg;
 2607         struct pcic_handle *ph = poll->ph;
 2608         struct pccbb_softc *sc = ph->sc;
 2609         int s;
u_int32_t spsr;                /* socket present-state reg */
timeout_set(&pccbb_poll_timeout, pccbb_pcmcia_poll, arg);
timeout_add(&pccbb_poll_timeout, hz * 2);
 2614         switch (poll->level) {
 2615         case IPL_NET:
s = splnet();
 2617                 break;
 2618         case IPL_BIO:
s = splbio();
 2620                 break;
 2621         case IPL_TTY:                  /* fallthrough */
 2622         default:
s = spltty();
 2624                 break;
 2625         }
spsr =
bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh,
CB_SOCKET_STAT);
 2631 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2
 2632         if (!(spsr & 0x40))            /* CINT low */
 2633 #else
 2634         if (1)
 2635 #endif
 2636         {
 2637                 if ((*poll->func) (poll->arg) > 0) {
 2638                         ++poll->count;
 2639         /* printf("intr: reported from poller, 0x%x\n", spsr); */
 2640 #if defined LEVEL2
 2641                 } else {
printf("intr: miss! 0x%x\n", spsr);
 2643 #endif
 2644                 }
 2645         }
splx(s);
 2647 }
 2648 #endif /* defined CB_PCMCIA_POLL */
 2650 /*
 2651  * void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch,
 2652  *                                          struct pcmcia_function *pf,
 2653  *                                          int ipl,
 2654  *                                          int (*func)(void *),
 2655  *                                          void *arg);
 2656  *
 2657  * This function enables PC-Card interrupt.  PCCBB uses PCI interrupt line.
 2658  */
 2659 void *
pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg, xname)
pcmcia_chipset_handle_t pch;
 2662         struct pcmcia_function *pf;
 2663         int ipl;
 2664         int (*func)(void *);
 2665         void *arg;
 2666         char *xname;
 2667 {
 2668         struct pcic_handle *ph = (struct pcic_handle *)pch;
 2669         struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent;
 2671         if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) {
 2672                 /* what should I do? */
 2673                 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) {
DPRINTF(
 2675                             ("%s does not provide edge nor pulse interrupt\n",
sc->sc_dev.dv_xname));
 2677                         return NULL;
 2678                 }
 2679                 /*
 2680                  * XXX Noooooo!  The interrupt flag must set properly!!
 2681                  * dumb pcmcia driver!!
 2682                  */
 2683         }
 2685         return pccbb_intr_establish(sc, -1, ipl, func, arg, xname);
 2686 }
 2688 /*
 2689  * void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch,
 2690  *                                            void *ih)
 2691  *
 2692  * This function disables PC-Card interrupt.
 2693  */
 2694 void
pccbb_pcmcia_intr_disestablish(pch, ih)
pcmcia_chipset_handle_t pch;
 2697         void *ih;
 2698 {
 2699         struct pcic_handle *ph = (struct pcic_handle *)pch;
 2700         struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent;
pccbb_intr_disestablish(sc, ih);
 2703 }
 2705 const char *
pccbb_pcmcia_intr_string(pch, ih)
pcmcia_chipset_handle_t pch;
 2708         void *ih;
 2709 {
 2710         if (ih == NULL)
 2711                 return "couldn't establish interrupt";
 2712         else
 2713                 return "";      /* card shares interrupt of the bridge */
 2714 }
 2716 /*
 2717  * int
 2718  * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb,
 2719  *                          bus_addr_t addr, bus_size_t size,
 2720  *                          bus_addr_t mask, bus_size_t align,
 2721  *                          int flags, bus_addr_t *addrp;
 2722  *                          bus_space_handle_t *bshp)
 2723  *
 2724  *   This function allocates a portion of memory or io space for
 2725  *   clients.  This function is called from CardBus card drivers.
 2726  */
 2727 int
pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp)
cardbus_chipset_tag_t ct;
rbus_tag_t rb;
bus_addr_t addr;
bus_size_t size;
bus_addr_t mask;
bus_size_t align;
 2735         int flags;
bus_addr_t *addrp;
bus_space_handle_t *bshp;
 2738 {
 2739         struct pccbb_softc *sc = (struct pccbb_softc *)ct;
DPRINTF(
 2742             ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n",
addr, size, mask, align));
 2745         if (align == 0) {
align = size;
 2747         }
 2749         if (rb->rb_bt == sc->sc_memt) {
 2750                 if (align < 16) {
 2751                         return 1;
 2752                 }
 2753         } else if (rb->rb_bt == sc->sc_iot) {
 2754                 if (align < 4) {
 2755                         return 1;
 2756                 }
 2757                 /* XXX: hack for avoiding ISA image */
 2758                 if (mask < 0x0100) {
mask = 0x3ff;
addr = 0x300;
 2761                 }
 2763         } else {
DPRINTF(
 2765                     ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n",
rb->rb_bt));
 2767                 return 1;
 2768                 /* XXX: panic here? */
 2769         }
 2771         if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) {
printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname);
 2773                 return 1;
 2774         }
pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0);
 2778         return 0;
 2779 }
 2781 /*
 2782  * int
 2783  * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb,
 2784  *                         bus_space_handle_t *bshp, bus_size_t size);
 2785  *
 2786  *   This function is called from CardBus card drivers.
 2787  */
 2788 int
pccbb_rbus_cb_space_free(ct, rb, bsh, size)
cardbus_chipset_tag_t ct;
rbus_tag_t rb;
bus_space_handle_t bsh;
bus_size_t size;
 2794 {
 2795         struct pccbb_softc *sc = (struct pccbb_softc *)ct;
bus_space_tag_t bt = rb->rb_bt;
pccbb_close_win(sc, bt, bsh, size);
 2800         if (bt == sc->sc_memt) {
 2801         } else if (bt == sc->sc_iot) {
 2802         } else {
 2803                 return 1;
 2804                 /* XXX: panic here? */
 2805         }
 2807         return rbus_space_free(rb, bsh, size, NULL);
 2808 }
 2810 int
pccbb_open_win(sc, bst, addr, size, bsh, flags)
 2812         struct pccbb_softc *sc;
bus_space_tag_t bst;
bus_addr_t addr;
bus_size_t size;
bus_space_handle_t bsh;
 2817         int flags;
 2818 {
 2819         struct pccbb_win_chain_head *head;
bus_addr_t align;
head = &sc->sc_iowindow;
align = 0x04;
 2824         if (sc->sc_memt == bst) {
head = &sc->sc_memwindow;
align = 0x1000;
DPRINTF(("using memory window, %x %x %x\n\n",
sc->sc_iot, sc->sc_memt, bst));
 2829         }
 2831         if (pccbb_winlist_insert(head, addr, size, bsh, flags)) {
printf("%s: pccbb_open_win: %s winlist insert failed\n",
sc->sc_dev.dv_xname,
 2834                     (head == &sc->sc_memwindow) ? "mem" : "io");
 2835         }
pccbb_winset(align, sc, bst);
 2838         return 0;
 2839 }
 2841 int
pccbb_close_win(sc, bst, bsh, size)
 2843         struct pccbb_softc *sc;
bus_space_tag_t bst;
bus_space_handle_t bsh;
bus_size_t size;
 2847 {
 2848         struct pccbb_win_chain_head *head;
bus_addr_t align;
head = &sc->sc_iowindow;
align = 0x04;
 2853         if (sc->sc_memt == bst) {
head = &sc->sc_memwindow;
align = 0x1000;
 2856         }
 2858         if (pccbb_winlist_delete(head, bsh, size)) {
printf("%s: pccbb_close_win: %s winlist delete failed\n",
sc->sc_dev.dv_xname,
 2861                     (head == &sc->sc_memwindow) ? "mem" : "io");
 2862         }
pccbb_winset(align, sc, bst);
 2865         return 0;
 2866 }
 2868 int
pccbb_winlist_insert(head, start, size, bsh, flags)
 2870         struct pccbb_win_chain_head *head;
bus_addr_t start;
bus_size_t size;
bus_space_handle_t bsh;
 2874         int flags;
 2875 {
 2876         struct pccbb_win_chain *chainp, *elem;
 2878         if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF,
M_NOWAIT)) == NULL)
 2880                 return (1);             /* fail */
elem->wc_start = start;
elem->wc_end = start + (size - 1);
elem->wc_handle = bsh;
elem->wc_flags = flags;
 2887         for (chainp = TAILQ_FIRST(head); chainp != NULL;
chainp = TAILQ_NEXT(chainp, wc_list)) {
 2889                 if (chainp->wc_end < start)
 2890                         continue;
TAILQ_INSERT_AFTER(head, chainp, elem, wc_list);
 2892                 return (0);
 2893         }
TAILQ_INSERT_TAIL(head, elem, wc_list);
 2896         return (0);
 2897 }
 2899 int
pccbb_winlist_delete(head, bsh, size)
 2901         struct pccbb_win_chain_head *head;
bus_space_handle_t bsh;
bus_size_t size;
 2904 {
 2905         struct pccbb_win_chain *chainp;
 2907         for (chainp = TAILQ_FIRST(head); chainp != NULL;
chainp = TAILQ_NEXT(chainp, wc_list)) {
 2909                 if (memcmp(&chainp->wc_handle, &bsh, sizeof(bsh)))
 2910                         continue;
 2911                 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) {
printf("pccbb_winlist_delete: window 0x%lx size "
 2913                             "inconsistent: 0x%lx, 0x%lx\n",
chainp->wc_start,
chainp->wc_end - chainp->wc_start,
size - 1);
 2917                         return 1;
 2918                 }
TAILQ_REMOVE(head, chainp, wc_list);
free(chainp, M_DEVBUF);
 2923                 return 0;
 2924         }
 2926         return 1;              /* fail: no candidate to remove */
 2927 }
 2929 void
pccbb_winset(align, sc, bst)
bus_addr_t align;
 2932         struct pccbb_softc *sc;
bus_space_tag_t bst;
 2934 {
pci_chipset_tag_t pc;
pcitag_t tag;
bus_addr_t mask = ~(align - 1);
 2938         struct {
cardbusreg_t win_start;
cardbusreg_t win_limit;
 2941                 int win_flags;
 2942         } win[2];
 2943         struct pccbb_win_chain *chainp;
 2944         int offs;
win[0].win_start = win[1].win_start = 0xffffffff;
win[0].win_limit = win[1].win_limit = 0;
win[0].win_flags = win[1].win_flags = 0;
chainp = TAILQ_FIRST(&sc->sc_iowindow);
offs = 0x2c;
 2952         if (sc->sc_memt == bst) {
chainp = TAILQ_FIRST(&sc->sc_memwindow);
offs = 0x1c;
 2955         }
 2957         if (chainp != NULL) {
win[0].win_start = chainp->wc_start & mask;
win[0].win_limit = chainp->wc_end & mask;
win[0].win_flags = chainp->wc_flags;
chainp = TAILQ_NEXT(chainp, wc_list);
 2962         }
 2964         for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) {
 2965                 if (win[1].win_start == 0xffffffff) {
 2966                         /* window 1 is not used */
 2967                         if ((win[0].win_flags == chainp->wc_flags) &&
 2968                             (win[0].win_limit + align >=
 2969                             (chainp->wc_start & mask))) {
 2970                                 /* concatenate */
win[0].win_limit = chainp->wc_end & mask;
 2972                         } else {
 2973                                 /* make new window */
win[1].win_start = chainp->wc_start & mask;
win[1].win_limit = chainp->wc_end & mask;
win[1].win_flags = chainp->wc_flags;
 2977                         }
 2978                         continue;
 2979                 }
 2981                 /* Both windows are engaged. */
 2982                 if (win[0].win_flags == win[1].win_flags) {
 2983                         /* same flags */
 2984                         if (win[0].win_flags == chainp->wc_flags) {
 2985                                 if (win[1].win_start - (win[0].win_limit +
align) <
 2987                                     (chainp->wc_start & mask) -
 2988                                     ((chainp->wc_end & mask) + align)) {
 2989                                         /*
 2990                                          * merge window 0 and 1, and set win1
 2991                                          * to chainp
 2992                                          */
win[0].win_limit = win[1].win_limit;
win[1].win_start =
chainp->wc_start & mask;
win[1].win_limit =
chainp->wc_end & mask;
 2998                                 } else {
win[1].win_limit =
chainp->wc_end & mask;
 3001                                 }
 3002                         } else {
 3003                                 /* different flags */
 3005                                 /* concatenate win0 and win1 */
win[0].win_limit = win[1].win_limit;
 3007                                 /* allocate win[1] to new space */
win[1].win_start = chainp->wc_start & mask;
win[1].win_limit = chainp->wc_end & mask;
win[1].win_flags = chainp->wc_flags;
 3011                         }
 3012                 } else {
 3013                         /* the flags of win[0] and win[1] is different */
 3014                         if (win[0].win_flags == chainp->wc_flags) {
win[0].win_limit = chainp->wc_end & mask;
 3016                                 /*
 3017                                  * XXX this creates overlapping windows, so
 3018                                  * what should the poor bridge do if one is
 3019                                  * cachable, and the other is not?
 3020                                  */
printf("%s: overlapping windows\n",
sc->sc_dev.dv_xname);
 3023                         } else {
win[1].win_limit = chainp->wc_end & mask;
 3025                         }
 3026                 }
 3027         }
pc = sc->sc_pc;
tag = sc->sc_tag;
pci_conf_write(pc, tag, offs, win[0].win_start);
pci_conf_write(pc, tag, offs + 4, win[0].win_limit);
pci_conf_write(pc, tag, offs + 8, win[1].win_start);
pci_conf_write(pc, tag, offs + 12, win[1].win_limit);
DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n",
pci_conf_read(pc, tag, offs),
pci_conf_read(pc, tag, offs + 4) + align,
pci_conf_read(pc, tag, offs + 8),
pci_conf_read(pc, tag, offs + 12) + align));
 3041         if (bst == sc->sc_memt) {
pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR);
bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1);
 3045                 if (win[0].win_flags & PCCBB_MEM_CACHABLE)
bcr |= CB_BCR_PREFETCH_MEMWIN0;
 3047                 if (win[1].win_flags & PCCBB_MEM_CACHABLE)
bcr |= CB_BCR_PREFETCH_MEMWIN1;
pci_conf_write(pc, tag, PCI_BCR_INTR, bcr);
 3050         }
 3051 }
 3053 void
pccbb_powerhook(why, arg)
 3055         int why;
 3056         void *arg;
 3057 {
 3058         struct pccbb_softc *sc = arg;
u_int32_t reg;
bus_space_tag_t base_memt = sc->sc_base_memt;   /* socket regs memory */
bus_space_handle_t base_memh = sc->sc_base_memh;
DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why));
 3065         if (why == PWR_SUSPEND || why == PWR_STANDBY) {
DPRINTF(("%s: power: why %d stopping intr\n",
sc->sc_dev.dv_xname, why));
 3068                 if (sc->sc_pil_intr_enable) {
 3069                         (void)pccbbintr_function(sc);
 3070                 }
sc->sc_pil_intr_enable = 0;
 3073                 /* ToDo: deactivate or suspend child devices */
 3075         }
 3077         if (why == PWR_RESUME) {
 3078                 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0)
 3079                         /* BIOS did not recover this register */
pci_conf_write (sc->sc_pc, sc->sc_tag,
PCI_SOCKBASE, sc->sc_sockbase);
 3082                 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0)
 3083                         /* BIOS did not recover this register */
pci_conf_write (sc->sc_pc, sc->sc_tag,
PCI_BUSNUM, sc->sc_busnum);
 3086                 /* CSC Interrupt: Card detect interrupt on */
reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK);
 3088                 /* Card detect intr is turned on. */
reg |= CB_SOCKET_MASK_CD;
bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg);
 3091                 /* reset interrupt */
reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT);
bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg);
 3095                 /*
 3096                  * check for card insertion or removal during suspend period.
 3097                  * XXX: the code can't cope with card swap (remove then
 3098                  * insert).  how can we detect such situation?
 3099                  */
 3100                 (void)pccbbintr(sc);
sc->sc_pil_intr_enable = 1;
DPRINTF(("%s: power: RESUME enabling intr\n",
sc->sc_dev.dv_xname));
 3106                 /* ToDo: activate or wakeup child devices */
 3107         }
 3108 }