root/dev/sdmmc/sdhc.c

DEFINITIONS

1. sdhc_host_found
2. sdhc_power
3. sdhc_shutdown
4. sdhc_host_reset
5. sdhc_host_ocr
6. sdhc_host_maxblklen
7. sdhc_card_detect
8. sdhc_bus_power
9. sdhc_clock_divisor
10. sdhc_bus_clock
11. sdhc_card_intr_mask
12. sdhc_card_intr_ack
13. sdhc_wait_state
14. sdhc_exec_command
15. sdhc_start_command
16. sdhc_transfer_data
17. sdhc_read_data
18. sdhc_write_data
19. sdhc_soft_reset
20. sdhc_wait_intr
21. sdhc_intr
22. sdhc_dump_regs

    1 /*      $OpenBSD: sdhc.c,v 1.21 2007/05/31 23:37:21 uwe Exp $   */
    3 /*
    4  * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
    5  *
    6  * Permission to use, copy, modify, and distribute this software for any
    7  * purpose with or without fee is hereby granted, provided that the above
    8  * copyright notice and this permission notice appear in all copies.
    9  *
   10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
   13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
   14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
   15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
   16  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
   17  */
   19 /*
   20  * SD Host Controller driver based on the SD Host Controller Standard
   21  * Simplified Specification Version 1.00 (www.sdcard.com).
   22  */
   24 #include <sys/param.h>
   25 #include <sys/device.h>
   26 #include <sys/kernel.h>
   27 #include <sys/kthread.h>
   28 #include <sys/malloc.h>
   29 #include <sys/systm.h>
   31 #include <dev/sdmmc/sdhcreg.h>
   32 #include <dev/sdmmc/sdhcvar.h>
   33 #include <dev/sdmmc/sdmmcchip.h>
   34 #include <dev/sdmmc/sdmmcreg.h>
   35 #include <dev/sdmmc/sdmmcvar.h>
   37 #define SDHC_COMMAND_TIMEOUT    hz
   38 #define SDHC_BUFFER_TIMEOUT     hz
   39 #define SDHC_TRANSFER_TIMEOUT   hz
   41 struct sdhc_host {
   42         struct sdhc_softc *sc;          /* host controller device */
   43         struct device *sdmmc;           /* generic SD/MMC device */
bus_space_tag_t iot;            /* host register set tag */
bus_space_handle_t ioh;         /* host register set handle */
u_int clkbase;                  /* base clock frequency in KHz */
   47         int maxblklen;                  /* maximum block length */
   48         int flags;                      /* flags for this host */
u_int32_t ocr;                  /* OCR value from capabilities */
u_int8_t regs[14];              /* host controller state */
u_int16_t intr_status;          /* soft interrupt status */
u_int16_t intr_error_status;    /* soft error status */
   53 };
   55 #define HDEVNAME(hp)    ((hp)->sc->sc_dev.dv_xname)
   57 /* flag values */
   58 #define SHF_USE_DMA             0x0001
   60 #define HREAD1(hp, reg)                                                 \
   61         (bus_space_read_1((hp)->iot, (hp)->ioh, (reg)))
   62 #define HREAD2(hp, reg)                                                 \
   63         (bus_space_read_2((hp)->iot, (hp)->ioh, (reg)))
   64 #define HREAD4(hp, reg)                                                 \
   65         (bus_space_read_4((hp)->iot, (hp)->ioh, (reg)))
   66 #define HWRITE1(hp, reg, val)                                           \
bus_space_write_1((hp)->iot, (hp)->ioh, (reg), (val))
   68 #define HWRITE2(hp, reg, val)                                           \
bus_space_write_2((hp)->iot, (hp)->ioh, (reg), (val))
   70 #define HWRITE4(hp, reg, val)                                           \
bus_space_write_4((hp)->iot, (hp)->ioh, (reg), (val))
   72 #define HCLR1(hp, reg, bits)                                            \
HWRITE1((hp), (reg), HREAD1((hp), (reg)) & ~(bits))
   74 #define HCLR2(hp, reg, bits)                                            \
HWRITE2((hp), (reg), HREAD2((hp), (reg)) & ~(bits))
   76 #define HSET1(hp, reg, bits)                                            \
HWRITE1((hp), (reg), HREAD1((hp), (reg)) | (bits))
   78 #define HSET2(hp, reg, bits)                                            \
HWRITE2((hp), (reg), HREAD2((hp), (reg)) | (bits))
   81 int     sdhc_host_reset(sdmmc_chipset_handle_t);
u_int32_t sdhc_host_ocr(sdmmc_chipset_handle_t);
   83 int     sdhc_host_maxblklen(sdmmc_chipset_handle_t);
   84 int     sdhc_card_detect(sdmmc_chipset_handle_t);
   85 int     sdhc_bus_power(sdmmc_chipset_handle_t, u_int32_t);
   86 int     sdhc_bus_clock(sdmmc_chipset_handle_t, int);
   87 void    sdhc_card_intr_mask(sdmmc_chipset_handle_t, int);
   88 void    sdhc_card_intr_ack(sdmmc_chipset_handle_t);
   89 void    sdhc_exec_command(sdmmc_chipset_handle_t, struct sdmmc_command *);
   90 int     sdhc_start_command(struct sdhc_host *, struct sdmmc_command *);
   91 int     sdhc_wait_state(struct sdhc_host *, u_int32_t, u_int32_t);
   92 int     sdhc_soft_reset(struct sdhc_host *, int);
   93 int     sdhc_wait_intr(struct sdhc_host *, int, int);
   94 void    sdhc_transfer_data(struct sdhc_host *, struct sdmmc_command *);
   95 void    sdhc_read_data(struct sdhc_host *, u_char *, int);
   96 void    sdhc_write_data(struct sdhc_host *, u_char *, int);
   98 #ifdef SDHC_DEBUG
   99 int sdhcdebug = 0;
  100 #define DPRINTF(n,s)    do { if ((n) <= sdhcdebug) printf s; } while (0)
  101 void    sdhc_dump_regs(struct sdhc_host *);
  102 #else
  103 #define DPRINTF(n,s)    do {} while(0)
  104 #endif
  106 struct sdmmc_chip_functions sdhc_functions = {
  107         /* host controller reset */
sdhc_host_reset,
  109         /* host controller capabilities */
sdhc_host_ocr,
sdhc_host_maxblklen,
  112         /* card detection */
sdhc_card_detect,
  114         /* bus power and clock frequency */
sdhc_bus_power,
sdhc_bus_clock,
  117         /* command execution */
sdhc_exec_command,
  119         /* card interrupt */
sdhc_card_intr_mask,
sdhc_card_intr_ack
  122 };
  124 struct cfdriver sdhc_cd = {
NULL, "sdhc", DV_DULL
  126 };
  128 /*
  129  * Called by attachment driver.  For each SD card slot there is one SD
  130  * host controller standard register set. (1.3)
  131  */
  132 int
sdhc_host_found(struct sdhc_softc *sc, bus_space_tag_t iot,
bus_space_handle_t ioh, bus_size_t iosize, int usedma)
  135 {
  136         struct sdmmcbus_attach_args saa;
  137         struct sdhc_host *hp;
u_int32_t caps;
  139         int error = 1;
  140 #ifdef SDHC_DEBUG
u_int16_t version;
version = bus_space_read_2(iot, ioh, SDHC_HOST_CTL_VERSION);
printf("%s: SD Host Specification/Vendor Version ",
sc->sc_dev.dv_xname);
  146         switch(SDHC_SPEC_VERSION(version)) {
  147         case 0x00:
printf("1.0/%u\n", SDHC_VENDOR_VERSION(version));
  149                 break;
  150         default:
printf(">1.0/%u\n", SDHC_VENDOR_VERSION(version));
  152                 break;
  153         }
  154 #endif
  156         /* Allocate one more host structure. */
sc->sc_nhosts++;
MALLOC(hp, struct sdhc_host *, sizeof(struct sdhc_host),
M_DEVBUF, M_WAITOK);
sc->sc_host[sc->sc_nhosts - 1] = hp;
  162         /* Fill in the new host structure. */
bzero(hp, sizeof(struct sdhc_host));
hp->sc = sc;
hp->iot = iot;
hp->ioh = ioh;
  168         /*
  169          * Reset the host controller and enable interrupts.
  170          */
  171         (void)sdhc_host_reset(hp);
  173         /* Determine host capabilities. */
caps = HREAD4(hp, SDHC_CAPABILITIES);
  176         /* Use DMA if the host system and the controller support it. */
  177         if (usedma && ISSET(caps, SDHC_DMA_SUPPORT))
SET(hp->flags, SHF_USE_DMA);
  180         /*
  181          * Determine the base clock frequency. (2.2.24)
  182          */
  183         if (SDHC_BASE_FREQ_KHZ(caps) != 0)
hp->clkbase = SDHC_BASE_FREQ_KHZ(caps);
  185         if (hp->clkbase == 0) {
  186                 /* The attachment driver must tell us. */
printf("%s: base clock frequency unknown\n",
sc->sc_dev.dv_xname);
  189                 goto err;
  190         } else if (hp->clkbase < 10000 || hp->clkbase > 63000) {
  191                 /* SDHC 1.0 supports only 10-63 MHz. */
printf("%s: base clock frequency out of range: %u MHz\n",
sc->sc_dev.dv_xname, hp->clkbase / 1000);
  194                 goto err;
  195         }
  197         /*
  198          * XXX Set the data timeout counter value according to
  199          * capabilities. (2.2.15)
  200          */
  202         /*
  203          * Determine SD bus voltage levels supported by the controller.
  204          */
  205         if (ISSET(caps, SDHC_VOLTAGE_SUPP_1_8V))
SET(hp->ocr, MMC_OCR_1_7V_1_8V | MMC_OCR_1_8V_1_9V);
  207         if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_0V))
SET(hp->ocr, MMC_OCR_2_9V_3_0V | MMC_OCR_3_0V_3_1V);
  209         if (ISSET(caps, SDHC_VOLTAGE_SUPP_3_3V))
SET(hp->ocr, MMC_OCR_3_2V_3_3V | MMC_OCR_3_3V_3_4V);
  212         /*
  213          * Determine the maximum block length supported by the host
  214          * controller. (2.2.24)
  215          */
  216         switch((caps >> SDHC_MAX_BLK_LEN_SHIFT) & SDHC_MAX_BLK_LEN_MASK) {
  217         case SDHC_MAX_BLK_LEN_512:
hp->maxblklen = 512;
  219                 break;
  220         case SDHC_MAX_BLK_LEN_1024:
hp->maxblklen = 1024;
  222                 break;
  223         case SDHC_MAX_BLK_LEN_2048:
hp->maxblklen = 2048;
  225                 break;
  226         default:
hp->maxblklen = 1;
  228                 break;
  229         }
  231         /*
  232          * Attach the generic SD/MMC bus driver.  (The bus driver must
  233          * not invoke any chipset functions before it is attached.)
  234          */
bzero(&saa, sizeof(saa));
saa.saa_busname = "sdmmc";
saa.sct = &sdhc_functions;
saa.sch = hp;
hp->sdmmc = config_found(&sc->sc_dev, &saa, NULL);
  241         if (hp->sdmmc == NULL) {
error = 0;
  243                 goto err;
  244         }
  246         return 0;
err:
FREE(hp, M_DEVBUF);
sc->sc_host[sc->sc_nhosts - 1] = NULL;
sc->sc_nhosts--;
  252         return (error);
  253 }
  255 /*
  256  * Power hook established by or called from attachment driver.
  257  */
  258 void
sdhc_power(int why, void *arg)
  260 {
  261         struct sdhc_softc *sc = arg;
  262         struct sdhc_host *hp;
  263         int n, i;
  265         switch(why) {
  266         case PWR_STANDBY:
  267         case PWR_SUSPEND:
  268                 /* XXX poll for command completion or suspend command
  269                  * in progress */
  271                 /* Save the host controller state. */
  272                 for (n = 0; n < sc->sc_nhosts; n++) {
hp = sc->sc_host[n];
  274                         for (i = 0; i < sizeof hp->regs; i++)
hp->regs[i] = HREAD1(hp, i);
  276                 }
  277                 break;
  279         case PWR_RESUME:
  280                 /* Restore the host controller state. */
  281                 for (n = 0; n < sc->sc_nhosts; n++) {
hp = sc->sc_host[n];
  283                         (void)sdhc_host_reset(hp);
  284                         for (i = 0; i < sizeof hp->regs; i++)
HWRITE1(hp, i, hp->regs[i]);
  286                 }
  287                 break;
  288         }
  289 }
  291 /*
  292  * Shutdown hook established by or called from attachment driver.
  293  */
  294 void
sdhc_shutdown(void *arg)
  296 {
  297         struct sdhc_softc *sc = arg;
  298         struct sdhc_host *hp;
  299         int i;
  301         /* XXX chip locks up if we don't disable it before reboot. */
  302         for (i = 0; i < sc->sc_nhosts; i++) {
hp = sc->sc_host[i];
  304                 (void)sdhc_host_reset(hp);
  305         }
  306 }
  308 /*
  309  * Reset the host controller.  Called during initialization, when
  310  * cards are removed, upon resume, and during error recovery.
  311  */
  312 int
sdhc_host_reset(sdmmc_chipset_handle_t sch)
  314 {
  315         struct sdhc_host *hp = sch;
u_int16_t imask;
  317         int error;
  318         int s;
s = splsdmmc();
  322         /* Disable all interrupts. */
HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, 0);
  325         /*
  326          * Reset the entire host controller and wait up to 100ms for
  327          * the controller to clear the reset bit.
  328          */
  329         if ((error = sdhc_soft_reset(hp, SDHC_RESET_ALL)) != 0) {
splx(s);
  331                 return (error);
  332         }       
  334         /* Set data timeout counter value to max for now. */
HWRITE1(hp, SDHC_TIMEOUT_CTL, SDHC_TIMEOUT_MAX);
  337         /* Enable interrupts. */
imask = SDHC_CARD_REMOVAL | SDHC_CARD_INSERTION |
SDHC_BUFFER_READ_READY | SDHC_BUFFER_WRITE_READY |
SDHC_DMA_INTERRUPT | SDHC_BLOCK_GAP_EVENT |
SDHC_TRANSFER_COMPLETE | SDHC_COMMAND_COMPLETE;
HWRITE2(hp, SDHC_NINTR_STATUS_EN, imask);
HWRITE2(hp, SDHC_EINTR_STATUS_EN, SDHC_EINTR_STATUS_MASK);
HWRITE2(hp, SDHC_NINTR_SIGNAL_EN, imask);
HWRITE2(hp, SDHC_EINTR_SIGNAL_EN, SDHC_EINTR_SIGNAL_MASK);
splx(s);
  349         return 0;
  350 }
u_int32_t
sdhc_host_ocr(sdmmc_chipset_handle_t sch)
  354 {
  355         struct sdhc_host *hp = sch;
  356         return hp->ocr;
  357 }
  359 int
sdhc_host_maxblklen(sdmmc_chipset_handle_t sch)
  361 {
  362         struct sdhc_host *hp = sch;
  363         return hp->maxblklen;
  364 }
  366 /*
  367  * Return non-zero if the card is currently inserted.
  368  */
  369 int
sdhc_card_detect(sdmmc_chipset_handle_t sch)
  371 {
  372         struct sdhc_host *hp = sch;
  373         return ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CARD_INSERTED) ?
  374             1 : 0;
  375 }
  377 /*
  378  * Set or change SD bus voltage and enable or disable SD bus power.
  379  * Return zero on success.
  380  */
  381 int
sdhc_bus_power(sdmmc_chipset_handle_t sch, u_int32_t ocr)
  383 {
  384         struct sdhc_host *hp = sch;
u_int8_t vdd;
  386         int s;
s = splsdmmc();
  390         /*
  391          * Disable bus power before voltage change.
  392          */
HWRITE1(hp, SDHC_POWER_CTL, 0);
  395         /* If power is disabled, reset the host and return now. */
  396         if (ocr == 0) {
splx(s);
  398                 (void)sdhc_host_reset(hp);
  399                 return 0;
  400         }
  402         /*
  403          * Select the maximum voltage according to capabilities.
  404          */
ocr &= hp->ocr;
  406         if (ISSET(ocr, MMC_OCR_3_2V_3_3V|MMC_OCR_3_3V_3_4V))
vdd = SDHC_VOLTAGE_3_3V;
  408         else if (ISSET(ocr, MMC_OCR_2_9V_3_0V|MMC_OCR_3_0V_3_1V))
vdd = SDHC_VOLTAGE_3_0V;
  410         else if (ISSET(ocr, MMC_OCR_1_7V_1_8V|MMC_OCR_1_8V_1_9V))
vdd = SDHC_VOLTAGE_1_8V;
  412         else {
  413                 /* Unsupported voltage level requested. */
splx(s);
  415                 return EINVAL;
  416         }
  418         /*
  419          * Enable bus power.  Wait at least 1 ms (or 74 clocks) plus
  420          * voltage ramp until power rises.
  421          */
HWRITE1(hp, SDHC_POWER_CTL, (vdd << SDHC_VOLTAGE_SHIFT) |
SDHC_BUS_POWER);
sdmmc_delay(10000);
  426         /*
  427          * The host system may not power the bus due to battery low,
  428          * etc.  In that case, the host controller should clear the
  429          * bus power bit.
  430          */
  431         if (!ISSET(HREAD1(hp, SDHC_POWER_CTL), SDHC_BUS_POWER)) {
splx(s);
  433                 return ENXIO;
  434         }
splx(s);
  437         return 0;
  438 }
  440 /*
  441  * Return the smallest possible base clock frequency divisor value
  442  * for the CLOCK_CTL register to produce `freq' (KHz).
  443  */
  444 static int
sdhc_clock_divisor(struct sdhc_host *hp, u_int freq)
  446 {
  447         int div;
  449         for (div = 1; div <= 256; div *= 2)
  450                 if ((hp->clkbase / div) <= freq)
  451                         return (div / 2);
  452         /* No divisor found. */
  453         return -1;
  454 }
  456 /*
  457  * Set or change SDCLK frequency or disable the SD clock.
  458  * Return zero on success.
  459  */
  460 int
sdhc_bus_clock(sdmmc_chipset_handle_t sch, int freq)
  462 {
  463         struct sdhc_host *hp = sch;
  464         int s;
  465         int div;
  466         int timo;
  467         int error = 0;
s = splsdmmc();
  471 #ifdef DIAGNOSTIC
  472         /* Must not stop the clock if commands are in progress. */
  473         if (ISSET(HREAD4(hp, SDHC_PRESENT_STATE), SDHC_CMD_INHIBIT_MASK) &&
sdhc_card_detect(hp))
printf("sdhc_sdclk_frequency_select: command in progress\n");
  476 #endif
  478         /*
  479          * Stop SD clock before changing the frequency.
  480          */
HWRITE2(hp, SDHC_CLOCK_CTL, 0);
  482         if (freq == SDMMC_SDCLK_OFF)
  483                 goto ret;
  485         /*
  486          * Set the minimum base clock frequency divisor.
  487          */
  488         if ((div = sdhc_clock_divisor(hp, freq)) < 0) {
  489                 /* Invalid base clock frequency or `freq' value. */
error = EINVAL;
  491                 goto ret;
  492         }
HWRITE2(hp, SDHC_CLOCK_CTL, div << SDHC_SDCLK_DIV_SHIFT);
  495         /*
  496          * Start internal clock.  Wait 10ms for stabilization.
  497          */
HSET2(hp, SDHC_CLOCK_CTL, SDHC_INTCLK_ENABLE);
  499         for (timo = 1000; timo > 0; timo--) {
  500                 if (ISSET(HREAD2(hp, SDHC_CLOCK_CTL), SDHC_INTCLK_STABLE))
  501                         break;
sdmmc_delay(10);
  503         }
  504         if (timo == 0) {
error = ETIMEDOUT;
  506                 goto ret;
  507         }
  509         /*
  510          * Enable SD clock.
  511          */
HSET2(hp, SDHC_CLOCK_CTL, SDHC_SDCLK_ENABLE);
ret:
splx(s);
  516         return error;
  517 }
  519 void
sdhc_card_intr_mask(sdmmc_chipset_handle_t sch, int enable)
  521 {
  522         struct sdhc_host *hp = sch;
  524         if (enable) {
HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT);
HSET2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT);
  527         } else {
HCLR2(hp, SDHC_NINTR_SIGNAL_EN, SDHC_CARD_INTERRUPT);
HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT);
  530         }
  531 }
  533 void
sdhc_card_intr_ack(sdmmc_chipset_handle_t sch)
  535 {
  536         struct sdhc_host *hp = sch;
HSET2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT);
  539 }
  541 int
sdhc_wait_state(struct sdhc_host *hp, u_int32_t mask, u_int32_t value)
  543 {
u_int32_t state;
  545         int timeout;
  547         for (timeout = 10; timeout > 0; timeout--) {
  548                 if (((state = HREAD4(hp, SDHC_PRESENT_STATE)) & mask)
  549                     == value)
  550                         return 0;
sdmmc_delay(10000);
  552         }
DPRINTF(0,("%s: timeout waiting for %x (state=%b)\n", HDEVNAME(hp),
value, state, SDHC_PRESENT_STATE_BITS));
  555         return ETIMEDOUT;
  556 }
  558 void
sdhc_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd)
  560 {
  561         struct sdhc_host *hp = sch;
  562         int error;
  564         /*
  565          * Start the MMC command, or mark `cmd' as failed and return.
  566          */
error = sdhc_start_command(hp, cmd);
  568         if (error != 0) {
cmd->c_error = error;
SET(cmd->c_flags, SCF_ITSDONE);
  571                 return;
  572         }
  574         /*
  575          * Wait until the command phase is done, or until the command
  576          * is marked done for any other reason.
  577          */
  578         if (!sdhc_wait_intr(hp, SDHC_COMMAND_COMPLETE,
SDHC_COMMAND_TIMEOUT)) {
cmd->c_error = ETIMEDOUT;
SET(cmd->c_flags, SCF_ITSDONE);
  582                 return;
  583         }
  585         /*
  586          * The host controller removes bits [0:7] from the response
  587          * data (CRC) and we pass the data up unchanged to the bus
  588          * driver (without padding).
  589          */
  590         if (cmd->c_error == 0 && ISSET(cmd->c_flags, SCF_RSP_PRESENT)) {
  591                 if (ISSET(cmd->c_flags, SCF_RSP_136)) {
u_char *p = (u_char *)cmd->c_resp;
  593                         int i;
  595                         for (i = 0; i < 15; i++)
  596                                 *p++ = HREAD1(hp, SDHC_RESPONSE + i);
  597                 } else
cmd->c_resp[0] = HREAD4(hp, SDHC_RESPONSE);
  599         }
  601         /*
  602          * If the command has data to transfer in any direction,
  603          * execute the transfer now.
  604          */
  605         if (cmd->c_error == 0 && cmd->c_data != NULL)
sdhc_transfer_data(hp, cmd);
  608         /* Turn off the LED. */
HCLR1(hp, SDHC_HOST_CTL, SDHC_LED_ON);
DPRINTF(1,("%s: cmd %u done (flags=%#x error=%d)\n",
HDEVNAME(hp), cmd->c_opcode, cmd->c_flags, cmd->c_error));
SET(cmd->c_flags, SCF_ITSDONE);
  614 }
  616 int
sdhc_start_command(struct sdhc_host *hp, struct sdmmc_command *cmd)
  618 {
u_int16_t blksize = 0;
u_int16_t blkcount = 0;
u_int16_t mode;
u_int16_t command;
  623         int error;
  624         int s;
DPRINTF(1,("%s: start cmd %u arg=%#x data=%#x dlen=%d flags=%#x "
  627             "proc=\"%s\"\n", HDEVNAME(hp), cmd->c_opcode, cmd->c_arg,
cmd->c_data, cmd->c_datalen, cmd->c_flags, curproc ?
curproc->p_comm : ""));
  631         /*
  632          * The maximum block length for commands should be the minimum
  633          * of the host buffer size and the card buffer size. (1.7.2)
  634          */
  636         /* Fragment the data into proper blocks. */
  637         if (cmd->c_datalen > 0) {
blksize = MIN(cmd->c_datalen, cmd->c_blklen);
blkcount = cmd->c_datalen / blksize;
  640                 if (cmd->c_datalen % blksize > 0) {
  641                         /* XXX: Split this command. (1.7.4) */
printf("%s: data not a multiple of %d bytes\n",
HDEVNAME(hp), blksize);
  644                         return EINVAL;
  645                 }
  646         }
  648         /* Check limit imposed by 9-bit block count. (1.7.2) */
  649         if (blkcount > SDHC_BLOCK_COUNT_MAX) {
printf("%s: too much data\n", HDEVNAME(hp));
  651                 return EINVAL;
  652         }
  654         /* Prepare transfer mode register value. (2.2.5) */
mode = 0;
  656         if (ISSET(cmd->c_flags, SCF_CMD_READ))
mode |= SDHC_READ_MODE;
  658         if (blkcount > 0) {
mode |= SDHC_BLOCK_COUNT_ENABLE;
  660                 if (blkcount > 1) {
mode |= SDHC_MULTI_BLOCK_MODE;
  662                         /* XXX only for memory commands? */
mode |= SDHC_AUTO_CMD12_ENABLE;
  664                 }
  665         }
  666 #ifdef notyet
  667         if (ISSET(hp->flags, SHF_USE_DMA))
mode |= SDHC_DMA_ENABLE;
  669 #endif
  671         /*
  672          * Prepare command register value. (2.2.6)
  673          */
command = (cmd->c_opcode & SDHC_COMMAND_INDEX_MASK) <<
SDHC_COMMAND_INDEX_SHIFT;
  677         if (ISSET(cmd->c_flags, SCF_RSP_CRC))
command |= SDHC_CRC_CHECK_ENABLE;
  679         if (ISSET(cmd->c_flags, SCF_RSP_IDX))
command |= SDHC_INDEX_CHECK_ENABLE;
  681         if (cmd->c_data != NULL)
command |= SDHC_DATA_PRESENT_SELECT;
  684         if (!ISSET(cmd->c_flags, SCF_RSP_PRESENT))
command |= SDHC_NO_RESPONSE;
  686         else if (ISSET(cmd->c_flags, SCF_RSP_136))
command |= SDHC_RESP_LEN_136;
  688         else if (ISSET(cmd->c_flags, SCF_RSP_BSY))
command |= SDHC_RESP_LEN_48_CHK_BUSY;
  690         else
command |= SDHC_RESP_LEN_48;
  693         /* Wait until command and data inhibit bits are clear. (1.5) */
  694         if ((error = sdhc_wait_state(hp, SDHC_CMD_INHIBIT_MASK, 0)) != 0)
  695                 return error;
s = splsdmmc();
  699         /* Alert the user not to remove the card. */
HSET1(hp, SDHC_HOST_CTL, SDHC_LED_ON);
  702         /* XXX: Set DMA start address if SHF_USE_DMA is set. */
DPRINTF(1,("%s: cmd=%#x mode=%#x blksize=%d blkcount=%d\n",
HDEVNAME(hp), command, mode, blksize, blkcount));
  707         /*
  708          * Start a CPU data transfer.  Writing to the high order byte
  709          * of the SDHC_COMMAND register triggers the SD command. (1.5)
  710          */
HWRITE2(hp, SDHC_TRANSFER_MODE, mode);
HWRITE2(hp, SDHC_BLOCK_SIZE, blksize);
  713         if (blkcount > 1)
HWRITE2(hp, SDHC_BLOCK_COUNT, blkcount);
HWRITE4(hp, SDHC_ARGUMENT, cmd->c_arg);
HWRITE2(hp, SDHC_COMMAND, command);
splx(s);
  719         return 0;
  720 }
  722 void
sdhc_transfer_data(struct sdhc_host *hp, struct sdmmc_command *cmd)
  724 {
u_char *datap = cmd->c_data;
  726         int i, datalen;
  727         int mask;
  728         int error;
mask = ISSET(cmd->c_flags, SCF_CMD_READ) ?
SDHC_BUFFER_READ_ENABLE : SDHC_BUFFER_WRITE_ENABLE;
error = 0;
datalen = cmd->c_datalen;
DPRINTF(1,("%s: resp=%#x datalen=%d\n", HDEVNAME(hp),
MMC_R1(cmd->c_resp), datalen));
  738 #ifdef SDHC_DEBUG
  739         /* XXX I forgot why I wanted to know when this happens :-( */
  740         if ((cmd->c_opcode == 52 || cmd->c_opcode == 53) &&
ISSET(MMC_R1(cmd->c_resp), 0xcb00))
printf("%s: CMD52/53 error response flags %#x\n",
HDEVNAME(hp), MMC_R1(cmd->c_resp) & 0xff00);
  744 #endif
  746         while (datalen > 0) {
  747                 if (!sdhc_wait_intr(hp, SDHC_BUFFER_READ_READY|
SDHC_BUFFER_WRITE_READY, SDHC_BUFFER_TIMEOUT)) {
error = ETIMEDOUT;
  750                         break;
  751                 }
  753                 if ((error = sdhc_wait_state(hp, mask, mask)) != 0)
  754                         break;
i = MIN(datalen, cmd->c_blklen);
  757                 if (ISSET(cmd->c_flags, SCF_CMD_READ))
sdhc_read_data(hp, datap, i);
  759                 else
sdhc_write_data(hp, datap, i);
datap += i;
datalen -= i;
  764         }
  766         if (error == 0 && !sdhc_wait_intr(hp, SDHC_TRANSFER_COMPLETE,
SDHC_TRANSFER_TIMEOUT))
error = ETIMEDOUT;
  770         if (error != 0)
cmd->c_error = error;
SET(cmd->c_flags, SCF_ITSDONE);
DPRINTF(1,("%s: data transfer done (error=%d)\n",
HDEVNAME(hp), cmd->c_error));
  776 }
  778 void
sdhc_read_data(struct sdhc_host *hp, u_char *datap, int datalen)
  780 {
  781         while (datalen > 3) {
  782                 *(u_int32_t *)datap = HREAD4(hp, SDHC_DATA);
datap += 4;
datalen -= 4;
  785         }
  786         if (datalen > 0) {
u_int32_t rv = HREAD4(hp, SDHC_DATA);
  788                 do {
  789                         *datap++ = rv & 0xff;
rv = rv >> 8;
  791                 } while (--datalen > 0);
  792         }
  793 }
  795 void
sdhc_write_data(struct sdhc_host *hp, u_char *datap, int datalen)
  797 {
  798         while (datalen > 3) {
DPRINTF(3,("%08x\n", *(u_int32_t *)datap));
HWRITE4(hp, SDHC_DATA, *((u_int32_t *)datap)++);
datalen -= 4;
  802         }
  803         if (datalen > 0) {
u_int32_t rv = *datap++;
  805                 if (datalen > 1)
rv |= *datap++ << 8;
  807                 if (datalen > 2)
rv |= *datap++ << 16;
DPRINTF(3,("rv %08x\n", rv));
HWRITE4(hp, SDHC_DATA, rv);
  811         }
  812 }
  814 /* Prepare for another command. */
  815 int
sdhc_soft_reset(struct sdhc_host *hp, int mask)
  817 {
  818         int timo;
DPRINTF(1,("%s: software reset reg=%#x\n", HDEVNAME(hp), mask));
HWRITE1(hp, SDHC_SOFTWARE_RESET, mask);
  823         for (timo = 10; timo > 0; timo--) {
  824                 if (!ISSET(HREAD1(hp, SDHC_SOFTWARE_RESET), mask))
  825                         break;
sdmmc_delay(10000);
HWRITE1(hp, SDHC_SOFTWARE_RESET, 0);
  828         }
  829         if (timo == 0) {
DPRINTF(1,("%s: timeout reg=%#x\n", HDEVNAME(hp),
HREAD1(hp, SDHC_SOFTWARE_RESET)));
HWRITE1(hp, SDHC_SOFTWARE_RESET, 0);
  833                 return (ETIMEDOUT);
  834         }
  836         return (0);
  837 }
  839 int
sdhc_wait_intr(struct sdhc_host *hp, int mask, int timo)
  841 {
  842         int status;
  843         int s;
mask |= SDHC_ERROR_INTERRUPT;
s = splsdmmc();
status = hp->intr_status & mask;
  849         while (status == 0) {
  850                 if (tsleep(&hp->intr_status, PWAIT, "hcintr", timo)
  851                     == EWOULDBLOCK) {
status |= SDHC_ERROR_INTERRUPT;
  853                         break;
  854                 }
status = hp->intr_status & mask;
  856         }
hp->intr_status &= ~status;
DPRINTF(2,("%s: intr status %#x error %#x\n", HDEVNAME(hp), status,
hp->intr_error_status));
  862         /* Command timeout has higher priority than command complete. */
  863         if (ISSET(status, SDHC_ERROR_INTERRUPT)) {
hp->intr_error_status = 0;
  865                 (void)sdhc_soft_reset(hp, SDHC_RESET_DAT|SDHC_RESET_CMD);
status = 0;
  867         }
splx(s);
  870         return status;
  871 }
  873 /*
  874  * Established by attachment driver at interrupt priority IPL_SDMMC.
  875  */
  876 int
sdhc_intr(void *arg)
  878 {
  879         struct sdhc_softc *sc = arg;
  880         int host;
  881         int done = 0;
  883         /* We got an interrupt, but we don't know from which slot. */
  884         for (host = 0; host < sc->sc_nhosts; host++) {
  885                 struct sdhc_host *hp = sc->sc_host[host];
u_int16_t status;
  888                 if (hp == NULL)
  889                         continue;
  891                 /* Find out which interrupts are pending. */
status = HREAD2(hp, SDHC_NINTR_STATUS);
  893                 if (!ISSET(status, SDHC_NINTR_STATUS_MASK))
  894                         continue; /* no interrupt for us */
  896                 /* Acknowledge the interrupts we are about to handle. */
HWRITE2(hp, SDHC_NINTR_STATUS, status);
DPRINTF(2,("%s: interrupt status=%b\n", HDEVNAME(hp),
status, SDHC_NINTR_STATUS_BITS));
  901                 /* Claim this interrupt. */
done = 1;
  904                 /*
  905                  * Service error interrupts.
  906                  */
  907                 if (ISSET(status, SDHC_ERROR_INTERRUPT)) {
u_int16_t error;
  910                         /* Acknowledge error interrupts. */
error = HREAD2(hp, SDHC_EINTR_STATUS);
HWRITE2(hp, SDHC_EINTR_STATUS, error);
DPRINTF(2,("%s: error interrupt, status=%b\n",
HDEVNAME(hp), error, SDHC_EINTR_STATUS_BITS));
  916                         if (ISSET(error, SDHC_CMD_TIMEOUT_ERROR|
SDHC_DATA_TIMEOUT_ERROR)) {
hp->intr_error_status |= error;
hp->intr_status |= status;
wakeup(&hp->intr_status);
  921                         }
  922                 }
  924                 /*
  925                  * Wake up the sdmmc event thread to scan for cards.
  926                  */
  927                 if (ISSET(status, SDHC_CARD_REMOVAL|SDHC_CARD_INSERTION))
sdmmc_needs_discover(hp->sdmmc);
  930                 /*
  931                  * Wake up the blocking process to service command
  932                  * related interrupt(s).
  933                  */
  934                 if (ISSET(status, SDHC_BUFFER_READ_READY|
SDHC_BUFFER_WRITE_READY|SDHC_COMMAND_COMPLETE|
SDHC_TRANSFER_COMPLETE)) {
hp->intr_status |= status;
wakeup(&hp->intr_status);
  939                 }
  941                 /*
  942                  * Service SD card interrupts.
  943                  */
  944                 if (ISSET(status, SDHC_CARD_INTERRUPT)) {
DPRINTF(0,("%s: card interrupt\n", HDEVNAME(hp)));
HCLR2(hp, SDHC_NINTR_STATUS_EN, SDHC_CARD_INTERRUPT);
sdmmc_card_intr(hp->sdmmc);
  948                 }
  949         }
  950         return done;
  951 }
  953 #ifdef SDHC_DEBUG
  954 void
sdhc_dump_regs(struct sdhc_host *hp)
  956 {
printf("0x%02x PRESENT_STATE:    %b\n", SDHC_PRESENT_STATE,
HREAD4(hp, SDHC_PRESENT_STATE), SDHC_PRESENT_STATE_BITS);
printf("0x%02x POWER_CTL:        %x\n", SDHC_POWER_CTL,
HREAD1(hp, SDHC_POWER_CTL));
printf("0x%02x NINTR_STATUS:     %x\n", SDHC_NINTR_STATUS,
HREAD2(hp, SDHC_NINTR_STATUS));
printf("0x%02x EINTR_STATUS:     %x\n", SDHC_EINTR_STATUS,
HREAD2(hp, SDHC_EINTR_STATUS));
printf("0x%02x NINTR_STATUS_EN:  %x\n", SDHC_NINTR_STATUS_EN,
HREAD2(hp, SDHC_NINTR_STATUS_EN));
printf("0x%02x EINTR_STATUS_EN:  %x\n", SDHC_EINTR_STATUS_EN,
HREAD2(hp, SDHC_EINTR_STATUS_EN));
printf("0x%02x NINTR_SIGNAL_EN:  %x\n", SDHC_NINTR_SIGNAL_EN,
HREAD2(hp, SDHC_NINTR_SIGNAL_EN));
printf("0x%02x EINTR_SIGNAL_EN:  %x\n", SDHC_EINTR_SIGNAL_EN,
HREAD2(hp, SDHC_EINTR_SIGNAL_EN));
printf("0x%02x CAPABILITIES:     %x\n", SDHC_CAPABILITIES,
HREAD4(hp, SDHC_CAPABILITIES));
printf("0x%02x MAX_CAPABILITIES: %x\n", SDHC_MAX_CAPABILITIES,
HREAD4(hp, SDHC_MAX_CAPABILITIES));
  977 }
  978 #endif