root/dev/sdmmc/sdmmcreg.h

INCLUDED FROM

DEFINITIONS

1. __bitfield

    1 /*      $OpenBSD: sdmmcreg.h,v 1.3 2007/03/18 22:21:21 uwe Exp $        */
    3 /*
    4  * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
    5  *
    6  * Permission to use, copy, modify, and distribute this software for any
    7  * purpose with or without fee is hereby granted, provided that the above
    8  * copyright notice and this permission notice appear in all copies.
    9  *
   10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
   13  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
   14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
   15  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
   16  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
   17  */
   19 #ifndef _SDMMCREG_H_
   20 #define _SDMMCREG_H_
   22 /* MMC commands */                              /* response type */
   23 #define MMC_GO_IDLE_STATE               0       /* R0 */
   24 #define MMC_SEND_OP_COND                1       /* R3 */
   25 #define MMC_ALL_SEND_CID                2       /* R2 */
   26 #define MMC_SET_RELATIVE_ADDR           3       /* R1 */
   27 #define MMC_SELECT_CARD                 7       /* R1 */
   28 #define MMC_SEND_CSD                    9       /* R2 */
   29 #define MMC_STOP_TRANSMISSION           12      /* R1B */
   30 #define MMC_SEND_STATUS                 13      /* R1 */
   31 #define MMC_SET_BLOCKLEN                16      /* R1 */
   32 #define MMC_READ_BLOCK_SINGLE           17      /* R1 */
   33 #define MMC_READ_BLOCK_MULTIPLE         18      /* R1 */
   34 #define MMC_SET_BLOCK_COUNT             23      /* R1 */
   35 #define MMC_WRITE_BLOCK_SINGLE          24      /* R1 */
   36 #define MMC_WRITE_BLOCK_MULTIPLE        25      /* R1 */
   37 #define MMC_APP_CMD                     55      /* R1 */
   39 /* SD commands */                               /* response type */
   40 #define SD_SEND_RELATIVE_ADDR           3       /* R6 */
   42 /* SD application commands */                   /* response type */
   43 #define SD_APP_SET_BUS_WIDTH            6       /* R1 */
   44 #define SD_APP_OP_COND                  41      /* R3 */
   46 /* OCR bits */
   47 #define MMC_OCR_MEM_READY               (1<<31) /* memory power-up status bit */
   48 #define MMC_OCR_3_5V_3_6V               (1<<23)
   49 #define MMC_OCR_3_4V_3_5V               (1<<22)
   50 #define MMC_OCR_3_3V_3_4V               (1<<21)
   51 #define MMC_OCR_3_2V_3_3V               (1<<20)
   52 #define MMC_OCR_3_1V_3_2V               (1<<19)
   53 #define MMC_OCR_3_0V_3_1V               (1<<18)
   54 #define MMC_OCR_2_9V_3_0V               (1<<17)
   55 #define MMC_OCR_2_8V_2_9V               (1<<16)
   56 #define MMC_OCR_2_7V_2_8V               (1<<15)
   57 #define MMC_OCR_2_6V_2_7V               (1<<14)
   58 #define MMC_OCR_2_5V_2_6V               (1<<13)
   59 #define MMC_OCR_2_4V_2_5V               (1<<12)
   60 #define MMC_OCR_2_3V_2_4V               (1<<11)
   61 #define MMC_OCR_2_2V_2_3V               (1<<10)
   62 #define MMC_OCR_2_1V_2_2V               (1<<9)
   63 #define MMC_OCR_2_0V_2_1V               (1<<8)
   64 #define MMC_OCR_1_9V_2_0V               (1<<7)
   65 #define MMC_OCR_1_8V_1_9V               (1<<6)
   66 #define MMC_OCR_1_7V_1_8V               (1<<5)
   67 #define MMC_OCR_1_6V_1_7V               (1<<4)
   69 /* R1 response type bits */
   70 #define MMC_R1_READY_FOR_DATA           (1<<8)  /* ready for next transfer */
   71 #define MMC_R1_APP_CMD                  (1<<5)  /* app. commands supported */
   73 /* 48-bit response decoding (32 bits w/o CRC) */
   74 #define MMC_R1(resp)                    ((resp)[0])
   75 #define MMC_R3(resp)                    ((resp)[0])
   76 #define SD_R6(resp)                     ((resp)[0])
   78 /* RCA argument and response */
   79 #define MMC_ARG_RCA(rca)                ((rca) << 16)
   80 #define SD_R6_RCA(resp)                 (SD_R6((resp)) >> 16)
   82 /* bus width argument */
   83 #define SD_ARG_BUS_WIDTH_1              0
   84 #define SD_ARG_BUS_WIDTH_4              2
   86 /* MMC R2 response (CSD) */
   87 #define MMC_CSD_CSDVER(resp)            MMC_RSP_BITS((resp), 126, 2)
   88 #define  MMC_CSD_CSDVER_1_0             1
   89 #define  MMC_CSD_CSDVER_2_0             2
   90 #define MMC_CSD_MMCVER(resp)            MMC_RSP_BITS((resp), 122, 4)
   91 #define  MMC_CSD_MMCVER_1_0             0 /* MMC 1.0 - 1.2 */
   92 #define  MMC_CSD_MMCVER_1_4             1 /* MMC 1.4 */
   93 #define  MMC_CSD_MMCVER_2_0             2 /* MMC 2.0 - 2.2 */
   94 #define  MMC_CSD_MMCVER_3_1             3 /* MMC 3.1 - 3.3 */
   95 #define  MMC_CSD_MMCVER_4_0             4 /* MMC 4 */
   96 #define MMC_CSD_READ_BL_LEN(resp)       MMC_RSP_BITS((resp), 80, 4)
   97 #define MMC_CSD_C_SIZE(resp)            MMC_RSP_BITS((resp), 62, 12)
   98 #define MMC_CSD_CAPACITY(resp)          ((MMC_CSD_C_SIZE((resp))+1) << \
   99                                          (MMC_CSD_C_SIZE_MULT((resp))+2))
  100 #define MMC_CSD_C_SIZE_MULT(resp)       MMC_RSP_BITS((resp), 47, 3)
  102 /* MMC v1 R2 response (CID) */
  103 #define MMC_CID_MID_V1(resp)            MMC_RSP_BITS((resp), 104, 24)
  104 #define MMC_CID_PNM_V1_CPY(resp, pnm)                                   \
  105         do {                                                            \
  106                 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8);                 \
  107                 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8);                 \
  108                 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8);                 \
  109                 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8);                 \
  110                 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8);                 \
  111                 (pnm)[5] = MMC_RSP_BITS((resp), 56, 8);                 \
  112                 (pnm)[6] = MMC_RSP_BITS((resp), 48, 8);                 \
  113                 (pnm)[7] = '\0';                                        \
  114         } while (0)
  115 #define MMC_CID_REV_V1(resp)            MMC_RSP_BITS((resp), 40, 8)
  116 #define MMC_CID_PSN_V1(resp)            MMC_RSP_BITS((resp), 16, 24)
  117 #define MMC_CID_MDT_V1(resp)            MMC_RSP_BITS((resp), 8, 8)
  119 /* MMC v2 R2 response (CID) */
  120 #define MMC_CID_MID_V2(resp)            MMC_RSP_BITS((resp), 120, 8)
  121 #define MMC_CID_OID_V2(resp)            MMC_RSP_BITS((resp), 104, 16)
  122 #define MMC_CID_PNM_V2_CPY(resp, pnm)                                   \
  123         do {                                                            \
  124                 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8);                 \
  125                 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8);                 \
  126                 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8);                 \
  127                 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8);                 \
  128                 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8);                 \
  129                 (pnm)[5] = MMC_RSP_BITS((resp), 56, 8);                 \
  130                 (pnm)[6] = '\0';                                        \
  131         } while (0)
  132 #define MMC_CID_PSN_V2(resp)            MMC_RSP_BITS((resp), 16, 32)
  134 /* SD R2 response (CSD) */
  135 #define SD_CSD_CSDVER(resp)             MMC_RSP_BITS((resp), 126, 2)
  136 #define  SD_CSD_CSDVER_1_0              0
  137 #define SD_CSD_TAAC(resp)               MMC_RSP_BITS((resp), 112, 8)
  138 #define  SD_CSD_TAAC_1_5_MSEC           0x26
  139 #define SD_CSD_NSAC(resp)               MMC_RSP_BITS((resp), 104, 8)
  140 #define SD_CSD_SPEED(resp)              MMC_RSP_BITS((resp), 96, 8)
  141 #define  SD_CSD_SPEED_25_MHZ            0x32
  142 #define  SD_CSD_SPEED_50_MHZ            0x5a
  143 #define SD_CSD_CCC(resp)                MMC_RSP_BITS((resp), 84, 12)
  144 #define  SD_CSD_CCC_ALL                 0x5f5
  145 #define SD_CSD_READ_BL_LEN(resp)        MMC_RSP_BITS((resp), 80, 4)
  146 #define SD_CSD_READ_BL_PARTIAL(resp)    MMC_RSP_BITS((resp), 79, 1)
  147 #define SD_CSD_WRITE_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 78, 1)
  148 #define SD_CSD_READ_BLK_MISALIGN(resp)  MMC_RSP_BITS((resp), 77, 1)
  149 #define SD_CSD_DSR_IMP(resp)            MMC_RSP_BITS((resp), 76, 1)
  150 #define SD_CSD_C_SIZE(resp)             MMC_RSP_BITS((resp), 62, 12)
  151 #define SD_CSD_CAPACITY(resp)           ((SD_CSD_C_SIZE((resp))+1) << \
  152                                          (SD_CSD_C_SIZE_MULT((resp))+2))
  153 #define SD_CSD_VDD_R_CURR_MIN(resp)     MMC_RSP_BITS((resp), 59, 3)
  154 #define SD_CSD_VDD_R_CURR_MAX(resp)     MMC_RSP_BITS((resp), 56, 3)
  155 #define SD_CSD_VDD_W_CURR_MIN(resp)     MMC_RSP_BITS((resp), 53, 3)
  156 #define SD_CSD_VDD_W_CURR_MAX(resp)     MMC_RSP_BITS((resp), 50, 3)
  157 #define  SD_CSD_VDD_RW_CURR_100mA       0x7
  158 #define  SD_CSD_VDD_RW_CURR_80mA        0x6
  159 #define SD_CSD_C_SIZE_MULT(resp)        MMC_RSP_BITS((resp), 47, 3)
  160 #define SD_CSD_ERASE_BLK_EN(resp)       MMC_RSP_BITS((resp), 46, 1)
  161 #define SD_CSD_SECTOR_SIZE(resp)        MMC_RSP_BITS((resp), 39, 7) /* +1 */
  162 #define SD_CSD_WP_GRP_SIZE(resp)        MMC_RSP_BITS((resp), 32, 7) /* +1 */
  163 #define SD_CSD_WP_GRP_ENABLE(resp)      MMC_RSP_BITS((resp), 31, 1)
  164 #define SD_CSD_R2W_FACTOR(resp)         MMC_RSP_BITS((resp), 26, 3)
  165 #define SD_CSD_WRITE_BL_LEN(resp)       MMC_RSP_BITS((resp), 22, 4)
  166 #define  SD_CSD_RW_BL_LEN_2G            0xa
  167 #define  SD_CSD_RW_BL_LEN_1G            0x9
  168 #define SD_CSD_WRITE_BL_PARTIAL(resp)   MMC_RSP_BITS((resp), 21, 1)
  169 #define SD_CSD_FILE_FORMAT_GRP(resp)    MMC_RSP_BITS((resp), 15, 1)
  170 #define SD_CSD_COPY(resp)               MMC_RSP_BITS((resp), 14, 1)
  171 #define SD_CSD_PERM_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 13, 1)
  172 #define SD_CSD_TMP_WRITE_PROTECT(resp)  MMC_RSP_BITS((resp), 12, 1)
  173 #define SD_CSD_FILE_FORMAT(resp)        MMC_RSP_BITS((resp), 10, 2)
  175 /* SD R2 response (CID) */
  176 #define SD_CID_MID(resp)                MMC_RSP_BITS((resp), 120, 8)
  177 #define SD_CID_OID(resp)                MMC_RSP_BITS((resp), 104, 16)
  178 #define SD_CID_PNM_CPY(resp, pnm)                                       \
  179         do {                                                            \
  180                 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8);                 \
  181                 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8);                 \
  182                 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8);                 \
  183                 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8);                 \
  184                 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8);                 \
  185                 (pnm)[5] = '\0';                                        \
  186         } while (0)
  187 #define SD_CID_REV(resp)                MMC_RSP_BITS((resp), 56, 8)
  188 #define SD_CID_PSN(resp)                MMC_RSP_BITS((resp), 24, 32)
  189 #define SD_CID_MDT(resp)                MMC_RSP_BITS((resp), 8, 12)
  191 /* Might be slow, but it should work on big and little endian systems. */
  192 #define MMC_RSP_BITS(resp, start, len)  __bitfield((resp), (start)-8, (len))
  193 static __inline int
__bitfield(u_int32_t *src, int start, int len)
  195 {
u_int8_t *sp;
u_int32_t dst, mask;
  198         int shift, bs, bc;
  200         if (start < 0 || len < 0 || len > 32)
  201                 return 0;
dst = 0;
mask = len % 32 ? UINT_MAX >> (32 - (len % 32)) : UINT_MAX;
shift = 0;
  207         while (len > 0) {
sp = (u_int8_t *)src + start / 8;
bs = start % 8;
bc = 8 - bs;
  211                 if (bc > len)
bc = len;
dst |= (*sp++ >> bs) << shift;
shift += bc;
start += bc;
len -= bc;
  217         }
dst &= mask;
  220         return (int)dst;
  221 }
  223 #endif