regs 282 arch/i386/i386/amd64errata.c u_int32_t regs[4];
regs 284 arch/i386/i386/amd64errata.c cpuid(0x80000001, regs);
regs 293 arch/i386/i386/amd64errata.c if (cpurevs[i + 1] == regs[0]) {
regs 233 arch/i386/i386/apm.c apm_perror(const char *str, struct apmregs *regs)
regs 236 arch/i386/i386/apm.c apm_err_translate(APM_ERR_CODE(regs)),
regs 237 arch/i386/i386/apm.c APM_ERR_CODE(regs));
regs 244 arch/i386/i386/apm.c apm_power_print (struct apm_softc *sc, struct apmregs *regs)
regs 247 arch/i386/i386/apm.c sc->batt_life = BATT_LIFE(regs);
regs 248 arch/i386/i386/apm.c if (BATT_LIFE(regs) != APM_BATT_LIFE_UNKNOWN) {
regs 251 arch/i386/i386/apm.c BATT_LIFE(regs));
regs 254 arch/i386/i386/apm.c switch (AC_STATE(regs)) {
regs 271 arch/i386/i386/apm.c switch (BATT_STATE(regs)) {
regs 288 arch/i386/i386/apm.c printf("undecoded (%x)", BATT_STATE(regs));
regs 292 arch/i386/i386/apm.c if (BATT_FLAGS(regs) & APM_BATT_FLAG_NOBATTERY)
regs 296 arch/i386/i386/apm.c if (BATT_FLAGS(regs) & APM_BATT_FLAG_HIGH)
regs 298 arch/i386/i386/apm.c else if (BATT_FLAGS(regs) & APM_BATT_FLAG_LOW)
regs 300 arch/i386/i386/apm.c else if (BATT_FLAGS(regs) & APM_BATT_FLAG_CRITICAL)
regs 304 arch/i386/i386/apm.c if (BATT_FLAGS(regs) & APM_BATT_FLAG_CHARGING)
regs 306 arch/i386/i386/apm.c if (BATT_REM_VALID(regs)) {
regs 307 arch/i386/i386/apm.c int life = BATT_REMAINING(regs);
regs 343 arch/i386/i386/apm.c apm_resume(struct apm_softc *sc, struct apmregs *regs)
regs 355 arch/i386/i386/apm.c apm_record_event(sc, regs->bx);
regs 380 arch/i386/i386/apm.c apm_handle_event(struct apm_softc *sc, struct apmregs *regs)
regs 385 arch/i386/i386/apm.c switch (regs->bx) {
regs 395 arch/i386/i386/apm.c if (apm_record_event(sc, regs->bx)) {
regs 410 arch/i386/i386/apm.c if (apm_record_event(sc, regs->bx)) {
regs 420 arch/i386/i386/apm.c if (apm_record_event(sc, regs->bx)) {
regs 435 arch/i386/i386/apm.c if (apm_record_event(sc, regs->bx)) {
regs 449 arch/i386/i386/apm.c apm_record_event(sc, regs->bx);
regs 453 arch/i386/i386/apm.c apm_resume(sc, regs);
regs 457 arch/i386/i386/apm.c apm_resume(sc, regs);
regs 461 arch/i386/i386/apm.c apm_resume(sc, regs);
regs 466 arch/i386/i386/apm.c apm_record_event(sc, regs->bx);
regs 470 arch/i386/i386/apm.c apm_record_event(sc, regs->bx);
regs 476 arch/i386/i386/apm.c apm_record_event(sc, regs->bx);
regs 494 arch/i386/i386/apm.c switch (regs->bx >> 8) {
regs 501 arch/i386/i386/apm.c DPRINTF(("apm_handle_event: %s event, code %d\n", p, regs->bx));
regs 510 arch/i386/i386/apm.c struct apmregs regs;
regs 517 arch/i386/i386/apm.c if (apm_get_event(®s) != 0) {
regs 519 arch/i386/i386/apm.c if (!(APM_ERR_CODE(®s) & APM_ERR_NOEVENTS))
regs 520 arch/i386/i386/apm.c apm_perror("get event", ®s);
regs 524 arch/i386/i386/apm.c if (apm_handle_event(sc, ®s))
regs 528 arch/i386/i386/apm.c if (apm_error || APM_ERR_CODE(®s) == APM_ERR_NOTCONN)
regs 549 arch/i386/i386/apm.c struct apmregs regs;
regs 551 arch/i386/i386/apm.c bzero(®s, sizeof(regs));
regs 552 arch/i386/i386/apm.c regs.cx = onoff ? APM_MGT_ENABLE : APM_MGT_DISABLE;
regs 554 arch/i386/i386/apm.c (apm_minver? APM_DEV_APM_BIOS : APM_MGT_ALL), ®s) != 0)
regs 555 arch/i386/i386/apm.c apm_perror("power management enable", ®s);
regs 561 arch/i386/i386/apm.c struct apmregs regs;
regs 565 arch/i386/i386/apm.c bzero(®s, sizeof(regs));
regs 566 arch/i386/i386/apm.c regs.cx = onoff ? APM_MGT_ENGAGE : APM_MGT_DISENGAGE;
regs 567 arch/i386/i386/apm.c if (apmcall(APM_PWR_MGT_ENGAGE, dev, ®s) != 0)
regs 569 arch/i386/i386/apm.c dev, apm_err_translate(APM_ERR_CODE(®s)),
regs 570 arch/i386/i386/apm.c APM_ERR_CODE(®s));
regs 577 arch/i386/i386/apm.c struct apmregs regs;
regs 584 arch/i386/i386/apm.c bzero(®s, sizeof(regs));
regs 585 arch/i386/i386/apm.c regs.cx = onoff ? APM_MGT_ENABLE : APM_MGT_DISABLE;
regs 586 arch/i386/i386/apm.c if (apmcall(APM_DEVICE_MGMT_ENABLE, dev, ®s) != 0)
regs 588 arch/i386/i386/apm.c dev, apm_err_translate(APM_ERR_CODE(®s)),
regs 589 arch/i386/i386/apm.c APM_ERR_CODE(®s));
regs 596 arch/i386/i386/apm.c struct apmregs regs;
regs 600 arch/i386/i386/apm.c bzero(®s, sizeof(regs));
regs 601 arch/i386/i386/apm.c regs.cx = state;
regs 602 arch/i386/i386/apm.c if (apmcall(APM_SET_PWR_STATE, dev, ®s) != 0) {
regs 603 arch/i386/i386/apm.c apm_perror("set power state", ®s);
regs 604 arch/i386/i386/apm.c if (APM_ERR_CODE(®s) == APM_ERR_UNRECOG_DEV)
regs 615 arch/i386/i386/apm.c struct apmregs regs;
regs 625 arch/i386/i386/apm.c bzero(®s, sizeof(regs));
regs 626 arch/i386/i386/apm.c if (apmcall(APM_CPU_BUSY, 0, ®s) != 0) {
regs 628 arch/i386/i386/apm.c apm_perror("set CPU busy", ®s);
regs 638 arch/i386/i386/apm.c struct apmregs regs;
regs 658 arch/i386/i386/apm.c bzero(®s, sizeof(regs));
regs 659 arch/i386/i386/apm.c if (apmcall(APM_CPU_IDLE, 0, ®s) != 0) {
regs 661 arch/i386/i386/apm.c apm_perror("set CPU idle", ®s);
regs 678 arch/i386/i386/apm.c struct apmregs regs;
regs 681 arch/i386/i386/apm.c bzero(®s, sizeof(regs));
regs 682 arch/i386/i386/apm.c regs.cx = APM_VERSION;
regs 685 arch/i386/i386/apm.c (rv = apmcall(APM_DRIVER_VERSION, APM_DEV_APM_BIOS, ®s)) == 0) {
regs 686 arch/i386/i386/apm.c apm_majver = APM_CONN_MAJOR(®s);
regs 687 arch/i386/i386/apm.c apm_minver = APM_CONN_MINOR(®s);
regs 691 arch/i386/i386/apm.c apm_perror("set version 1.2", ®s);
regs 694 arch/i386/i386/apm.c bzero(®s, sizeof(regs));
regs 695 arch/i386/i386/apm.c regs.cx = 0x0101;
regs 697 arch/i386/i386/apm.c if (apmcall(APM_DRIVER_VERSION, APM_DEV_APM_BIOS, ®s) == 0) {
regs 702 arch/i386/i386/apm.c apm_perror("set version 1.1", ®s);
regs 736 arch/i386/i386/apm.c struct apmregs regs;
regs 738 arch/i386/i386/apm.c bzero(®s, sizeof(regs));
regs 740 arch/i386/i386/apm.c (apm_minver == 1 ? APM_DEV_ALLDEVS : APM_DEFAULTS_ALL), ®s))
regs 741 arch/i386/i386/apm.c apm_perror("system defaults failed", ®s);
regs 743 arch/i386/i386/apm.c if (apmcall(APM_DISCONNECT, APM_DEV_APM_BIOS, ®s))
regs 744 arch/i386/i386/apm.c apm_perror("disconnect failed", ®s);
regs 798 arch/i386/i386/apm.c struct apmregs regs;
regs 884 arch/i386/i386/apm.c bzero(®s, sizeof(regs));
regs 885 arch/i386/i386/apm.c if (apm_get_powstat(®s) == 0)
regs 886 arch/i386/i386/apm.c apm_power_print(sc, ®s);
regs 888 arch/i386/i386/apm.c apm_perror("get power status", ®s);
regs 1027 arch/i386/i386/apm.c struct apmregs regs;
regs 1080 arch/i386/i386/apm.c bzero(®s, sizeof(regs));
regs 1081 arch/i386/i386/apm.c if (!apmcall(APM_GET_POWER_STATE, actl->dev, ®s))
regs 1083 arch/i386/i386/apm.c sc->sc_dev.dv_xname, dev, regs.cx);
regs 1089 arch/i386/i386/apm.c if (apm_get_powstat(®s) == 0) {
regs 1094 arch/i386/i386/apm.c if (BATT_LIFE(®s) != APM_BATT_LIFE_UNKNOWN)
regs 1095 arch/i386/i386/apm.c powerp->battery_life = BATT_LIFE(®s);
regs 1096 arch/i386/i386/apm.c powerp->ac_state = AC_STATE(®s);
regs 1099 arch/i386/i386/apm.c if (!(BATT_FLAGS(®s) & APM_BATT_FLAG_NOBATTERY))
regs 1100 arch/i386/i386/apm.c powerp->battery_state = BATT_STATE(®s);
regs 1104 arch/i386/i386/apm.c if (BATT_FLAGS(®s) & APM_BATT_FLAG_HIGH)
regs 1106 arch/i386/i386/apm.c else if (BATT_FLAGS(®s) & APM_BATT_FLAG_LOW)
regs 1108 arch/i386/i386/apm.c else if (BATT_FLAGS(®s) & APM_BATT_FLAG_CRITICAL)
regs 1110 arch/i386/i386/apm.c else if (BATT_FLAGS(®s) & APM_BATT_FLAG_CHARGING)
regs 1112 arch/i386/i386/apm.c else if (BATT_FLAGS(®s) & APM_BATT_FLAG_NOBATTERY)
regs 1116 arch/i386/i386/apm.c if (BATT_REM_VALID(®s)) {
regs 1117 arch/i386/i386/apm.c powerp->minutes_left = BATT_REMAINING(®s);
regs 1124 arch/i386/i386/apm.c apm_perror("ioctl get power status", ®s);
regs 101 arch/i386/i386/db_interface.c kdb_trap(int type, int code, db_regs_t *regs)
regs 132 arch/i386/i386/db_interface.c ddb_regs = *regs;
regs 133 arch/i386/i386/db_interface.c if (KERNELMODE(regs->tf_cs, regs->tf_eflags)) {
regs 137 arch/i386/i386/db_interface.c ddb_regs.tf_esp = (int)®s->tf_esp; /* kernel stack pointer */
regs 149 arch/i386/i386/db_interface.c regs->tf_fs = ddb_regs.tf_fs & 0xffff;
regs 150 arch/i386/i386/db_interface.c regs->tf_gs = ddb_regs.tf_gs & 0xffff;
regs 151 arch/i386/i386/db_interface.c regs->tf_es = ddb_regs.tf_es & 0xffff;
regs 152 arch/i386/i386/db_interface.c regs->tf_ds = ddb_regs.tf_ds & 0xffff;
regs 153 arch/i386/i386/db_interface.c regs->tf_edi = ddb_regs.tf_edi;
regs 154 arch/i386/i386/db_interface.c regs->tf_esi = ddb_regs.tf_esi;
regs 155 arch/i386/i386/db_interface.c regs->tf_ebp = ddb_regs.tf_ebp;
regs 156 arch/i386/i386/db_interface.c regs->tf_ebx = ddb_regs.tf_ebx;
regs 157 arch/i386/i386/db_interface.c regs->tf_edx = ddb_regs.tf_edx;
regs 158 arch/i386/i386/db_interface.c regs->tf_ecx = ddb_regs.tf_ecx;
regs 159 arch/i386/i386/db_interface.c regs->tf_eax = ddb_regs.tf_eax;
regs 160 arch/i386/i386/db_interface.c regs->tf_eip = ddb_regs.tf_eip;
regs 161 arch/i386/i386/db_interface.c regs->tf_cs = ddb_regs.tf_cs & 0xffff;
regs 162 arch/i386/i386/db_interface.c regs->tf_eflags = ddb_regs.tf_eflags;
regs 163 arch/i386/i386/db_interface.c if (!KERNELMODE(regs->tf_cs, regs->tf_eflags)) {
regs 165 arch/i386/i386/db_interface.c regs->tf_esp = ddb_regs.tf_esp;
regs 166 arch/i386/i386/db_interface.c regs->tf_ss = ddb_regs.tf_ss & 0xffff;
regs 164 arch/i386/i386/kgdb_machdep.c kgdb_getregs(db_regs_t *regs, kgdb_reg_t *gdb_regs)
regs 167 arch/i386/i386/kgdb_machdep.c gdb_regs[ 0] = regs->tf_eax;
regs 168 arch/i386/i386/kgdb_machdep.c gdb_regs[ 1] = regs->tf_ecx;
regs 169 arch/i386/i386/kgdb_machdep.c gdb_regs[ 2] = regs->tf_edx;
regs 170 arch/i386/i386/kgdb_machdep.c gdb_regs[ 3] = regs->tf_ebx;
regs 171 arch/i386/i386/kgdb_machdep.c gdb_regs[ 5] = regs->tf_ebp;
regs 172 arch/i386/i386/kgdb_machdep.c gdb_regs[ 6] = regs->tf_esi;
regs 173 arch/i386/i386/kgdb_machdep.c gdb_regs[ 7] = regs->tf_edi;
regs 174 arch/i386/i386/kgdb_machdep.c gdb_regs[ 8] = regs->tf_eip;
regs 175 arch/i386/i386/kgdb_machdep.c gdb_regs[ 9] = regs->tf_eflags;
regs 176 arch/i386/i386/kgdb_machdep.c gdb_regs[10] = regs->tf_cs;
regs 177 arch/i386/i386/kgdb_machdep.c gdb_regs[12] = regs->tf_ds;
regs 178 arch/i386/i386/kgdb_machdep.c gdb_regs[13] = regs->tf_es;
regs 179 arch/i386/i386/kgdb_machdep.c gdb_regs[14] = regs->tf_fs;
regs 180 arch/i386/i386/kgdb_machdep.c gdb_regs[15] = regs->tf_gs;
regs 182 arch/i386/i386/kgdb_machdep.c if (KERNELMODE(regs->tf_cs, regs->tf_eflags)) {
regs 186 arch/i386/i386/kgdb_machdep.c gdb_regs[ 4] = (kgdb_reg_t)®s->tf_esp; /* kernel stack
regs 196 arch/i386/i386/kgdb_machdep.c kgdb_setregs(db_regs_t *regs, kgdb_reg_t *gdb_regs)
regs 199 arch/i386/i386/kgdb_machdep.c regs->tf_eax = gdb_regs[ 0];
regs 200 arch/i386/i386/kgdb_machdep.c regs->tf_ecx = gdb_regs[ 1];
regs 201 arch/i386/i386/kgdb_machdep.c regs->tf_edx = gdb_regs[ 2];
regs 202 arch/i386/i386/kgdb_machdep.c regs->tf_ebx = gdb_regs[ 3];
regs 203 arch/i386/i386/kgdb_machdep.c regs->tf_ebp = gdb_regs[ 5];
regs 204 arch/i386/i386/kgdb_machdep.c regs->tf_esi = gdb_regs[ 6];
regs 205 arch/i386/i386/kgdb_machdep.c regs->tf_edi = gdb_regs[ 7];
regs 206 arch/i386/i386/kgdb_machdep.c regs->tf_eip = gdb_regs[ 8];
regs 207 arch/i386/i386/kgdb_machdep.c regs->tf_eflags = gdb_regs[ 9];
regs 208 arch/i386/i386/kgdb_machdep.c regs->tf_cs = gdb_regs[10];
regs 209 arch/i386/i386/kgdb_machdep.c regs->tf_ds = gdb_regs[12];
regs 210 arch/i386/i386/kgdb_machdep.c regs->tf_es = gdb_regs[13];
regs 212 arch/i386/i386/kgdb_machdep.c if (KERNELMODE(regs->tf_cs, regs->tf_eflags) == 0) {
regs 216 arch/i386/i386/kgdb_machdep.c regs->tf_esp = gdb_regs[ 4];
regs 217 arch/i386/i386/kgdb_machdep.c regs->tf_ss = gdb_regs[11];
regs 251 arch/i386/i386/kvm86.c kvm86_simplecall(int no, struct kvm86regs *regs)
regs 257 arch/i386/i386/kvm86.c tf.tf_eax = regs->eax;
regs 258 arch/i386/i386/kvm86.c tf.tf_ebx = regs->ebx;
regs 259 arch/i386/i386/kvm86.c tf.tf_ecx = regs->ecx;
regs 260 arch/i386/i386/kvm86.c tf.tf_edx = regs->edx;
regs 261 arch/i386/i386/kvm86.c tf.tf_esi = regs->esi;
regs 262 arch/i386/i386/kvm86.c tf.tf_edi = regs->edi;
regs 263 arch/i386/i386/kvm86.c tf.tf_vm86_es = regs->es;
regs 269 arch/i386/i386/kvm86.c regs->eax = tf.tf_eax;
regs 270 arch/i386/i386/kvm86.c regs->ebx = tf.tf_ebx;
regs 271 arch/i386/i386/kvm86.c regs->ecx = tf.tf_ecx;
regs 272 arch/i386/i386/kvm86.c regs->edx = tf.tf_edx;
regs 273 arch/i386/i386/kvm86.c regs->esi = tf.tf_esi;
regs 274 arch/i386/i386/kvm86.c regs->edi = tf.tf_edi;
regs 275 arch/i386/i386/kvm86.c regs->es = tf.tf_vm86_es;
regs 276 arch/i386/i386/kvm86.c regs->eflags = tf.tf_eflags;
regs 41 arch/i386/i386/longrun.c uint32_t regs[2];
regs 77 arch/i386/i386/longrun.c uint32_t eflags, regs[4];
regs 81 arch/i386/i386/longrun.c cpuid(0x80860007, regs);
regs 85 arch/i386/i386/longrun.c cpuspeed = regs[0];
regs 113 arch/i386/i386/longrun.c msrinfo.regs[0] = LONGRUN_MODE_WRITE(msrinfo.regs[0], 0); /* low */
regs 114 arch/i386/i386/longrun.c msrinfo.regs[1] = LONGRUN_MODE_WRITE(msrinfo.regs[1], high);
regs 118 arch/i386/i386/longrun.c msrinfo.regs[0] = (msrinfo.regs[0] & ~0x01) | mode;
regs 364 arch/i386/i386/machdep.c cpuid(u_int32_t ax, u_int32_t *regs)
regs 373 arch/i386/i386/machdep.c :"0" (ax), "S" (regs)
regs 1065 arch/i386/i386/machdep.c u_int32_t regs[4];
regs 1082 arch/i386/i386/machdep.c cpuid(0x80000001, regs);
regs 1083 arch/i386/i386/machdep.c val = regs[3];
regs 1109 arch/i386/i386/machdep.c cpuid(0xC0000000, regs); /* Check for RNG */
regs 1110 arch/i386/i386/machdep.c val = regs[0];
regs 1112 arch/i386/i386/machdep.c cpuid(0xC0000001, regs);
regs 1113 arch/i386/i386/machdep.c val = regs[3];
regs 1362 arch/i386/i386/machdep.c u_int regs[4];
regs 1368 arch/i386/i386/machdep.c cpuid(0x06, regs);
regs 1369 arch/i386/i386/machdep.c if ((regs[0] & 0x01) != 1)
regs 1679 arch/i386/i386/machdep.c u_int regs[4];
regs 1680 arch/i386/i386/machdep.c cpuid(0x80000000, regs);
regs 1681 arch/i386/i386/machdep.c if (regs[0] >= 0x80000006) {
regs 1682 arch/i386/i386/machdep.c cpuid(0x80000006, regs);
regs 1683 arch/i386/i386/machdep.c cachesize = (regs[2] >> 16);
regs 1879 arch/i386/i386/machdep.c u_int32_t regs[4];
regs 1882 arch/i386/i386/machdep.c cpuid(0x80860001, regs);
regs 1886 arch/i386/i386/machdep.c if (((regs[1] >> 16) & 0xff) >= 0x3)
regs 380 arch/i386/i386/powernow-k7.c u_int regs[4];
regs 394 arch/i386/i386/powernow-k7.c cpuid(0x80000000, regs);
regs 395 arch/i386/i386/powernow-k7.c if (regs[0] < 0x80000007)
regs 398 arch/i386/i386/powernow-k7.c cpuid(0x80000007, regs);
regs 399 arch/i386/i386/powernow-k7.c if (!(regs[3] & AMD_PN_FID_VID))
regs 403 arch/i386/i386/powernow-k7.c cpuid(0x80000001, regs);
regs 427 arch/i386/i386/powernow-k7.c k7pnow_states(cstate, regs[0], maxfid, startvid);
regs 437 arch/i386/i386/powernow-k8.c u_int32_t regs[4];
regs 447 arch/i386/i386/powernow-k8.c cpuid(0x80000000, regs);
regs 448 arch/i386/i386/powernow-k8.c if (regs[0] < 0x80000007)
regs 451 arch/i386/i386/powernow-k8.c cpuid(0x80000007, regs);
regs 452 arch/i386/i386/powernow-k8.c if (!(regs[3] & AMD_PN_FID_VID))
regs 456 arch/i386/i386/powernow-k8.c cpuid(0x80000001, regs);
regs 483 arch/i386/i386/powernow-k8.c k8pnow_states(cstate, regs[0], maxfid, maxvid);
regs 153 arch/i386/i386/process_machdep.c process_read_regs(struct proc *p, struct reg *regs)
regs 159 arch/i386/i386/process_machdep.c regs->r_gs = tf->tf_vm86_gs & 0xffff;
regs 160 arch/i386/i386/process_machdep.c regs->r_fs = tf->tf_vm86_fs & 0xffff;
regs 161 arch/i386/i386/process_machdep.c regs->r_es = tf->tf_vm86_es & 0xffff;
regs 162 arch/i386/i386/process_machdep.c regs->r_ds = tf->tf_vm86_ds & 0xffff;
regs 163 arch/i386/i386/process_machdep.c regs->r_eflags = get_vflags(p);
regs 167 arch/i386/i386/process_machdep.c regs->r_gs = tf->tf_gs & 0xffff;
regs 168 arch/i386/i386/process_machdep.c regs->r_fs = tf->tf_fs & 0xffff;
regs 169 arch/i386/i386/process_machdep.c regs->r_es = tf->tf_es & 0xffff;
regs 170 arch/i386/i386/process_machdep.c regs->r_ds = tf->tf_ds & 0xffff;
regs 171 arch/i386/i386/process_machdep.c regs->r_eflags = tf->tf_eflags;
regs 173 arch/i386/i386/process_machdep.c regs->r_edi = tf->tf_edi;
regs 174 arch/i386/i386/process_machdep.c regs->r_esi = tf->tf_esi;
regs 175 arch/i386/i386/process_machdep.c regs->r_ebp = tf->tf_ebp;
regs 176 arch/i386/i386/process_machdep.c regs->r_ebx = tf->tf_ebx;
regs 177 arch/i386/i386/process_machdep.c regs->r_edx = tf->tf_edx;
regs 178 arch/i386/i386/process_machdep.c regs->r_ecx = tf->tf_ecx;
regs 179 arch/i386/i386/process_machdep.c regs->r_eax = tf->tf_eax;
regs 180 arch/i386/i386/process_machdep.c regs->r_eip = tf->tf_eip;
regs 181 arch/i386/i386/process_machdep.c regs->r_cs = tf->tf_cs & 0xffff;
regs 182 arch/i386/i386/process_machdep.c regs->r_esp = tf->tf_esp;
regs 183 arch/i386/i386/process_machdep.c regs->r_ss = tf->tf_ss & 0xffff;
regs 189 arch/i386/i386/process_machdep.c process_read_fpregs(struct proc *p, struct fpreg *regs)
regs 221 arch/i386/i386/process_machdep.c memcpy(regs, &s87, sizeof(*regs));
regs 223 arch/i386/i386/process_machdep.c memcpy(regs, &frame->sv_87, sizeof(*regs));
regs 265 arch/i386/i386/process_machdep.c process_write_regs(struct proc *p, struct reg *regs)
regs 271 arch/i386/i386/process_machdep.c tf->tf_vm86_gs = regs->r_gs & 0xffff;
regs 272 arch/i386/i386/process_machdep.c tf->tf_vm86_fs = regs->r_fs & 0xffff;
regs 273 arch/i386/i386/process_machdep.c tf->tf_vm86_es = regs->r_es & 0xffff;
regs 274 arch/i386/i386/process_machdep.c tf->tf_vm86_ds = regs->r_ds & 0xffff;
regs 275 arch/i386/i386/process_machdep.c set_vflags(p, regs->r_eflags);
regs 282 arch/i386/i386/process_machdep.c if (((regs->r_eflags ^ tf->tf_eflags) & PSL_USERSTATIC) != 0 ||
regs 283 arch/i386/i386/process_machdep.c !USERMODE(regs->r_cs, regs->r_eflags))
regs 286 arch/i386/i386/process_machdep.c tf->tf_gs = regs->r_gs & 0xffff;
regs 287 arch/i386/i386/process_machdep.c tf->tf_fs = regs->r_fs & 0xffff;
regs 288 arch/i386/i386/process_machdep.c tf->tf_es = regs->r_es & 0xffff;
regs 289 arch/i386/i386/process_machdep.c tf->tf_ds = regs->r_ds & 0xffff;
regs 290 arch/i386/i386/process_machdep.c tf->tf_eflags = regs->r_eflags;
regs 292 arch/i386/i386/process_machdep.c tf->tf_edi = regs->r_edi;
regs 293 arch/i386/i386/process_machdep.c tf->tf_esi = regs->r_esi;
regs 294 arch/i386/i386/process_machdep.c tf->tf_ebp = regs->r_ebp;
regs 295 arch/i386/i386/process_machdep.c tf->tf_ebx = regs->r_ebx;
regs 296 arch/i386/i386/process_machdep.c tf->tf_edx = regs->r_edx;
regs 297 arch/i386/i386/process_machdep.c tf->tf_ecx = regs->r_ecx;
regs 298 arch/i386/i386/process_machdep.c tf->tf_eax = regs->r_eax;
regs 299 arch/i386/i386/process_machdep.c tf->tf_eip = regs->r_eip;
regs 300 arch/i386/i386/process_machdep.c tf->tf_cs = regs->r_cs & 0xffff;
regs 301 arch/i386/i386/process_machdep.c tf->tf_esp = regs->r_esp;
regs 302 arch/i386/i386/process_machdep.c tf->tf_ss = regs->r_ss & 0xffff;
regs 308 arch/i386/i386/process_machdep.c process_write_fpregs(struct proc *p, struct fpreg *regs)
regs 323 arch/i386/i386/process_machdep.c memcpy(&s87, regs, sizeof(*regs));
regs 326 arch/i386/i386/process_machdep.c memcpy(&frame->sv_87, regs, sizeof(*regs));
regs 332 arch/i386/i386/process_machdep.c process_read_xmmregs(struct proc *p, struct xmmregs *regs)
regs 349 arch/i386/i386/process_machdep.c memcpy(regs, &frame->sv_xmm, sizeof(*regs));
regs 354 arch/i386/i386/process_machdep.c process_write_xmmregs(struct proc *p, const struct xmmregs *regs)
regs 368 arch/i386/i386/process_machdep.c memcpy(&frame->sv_xmm, regs, sizeof(*regs));
regs 160 arch/i386/i386/vm86.c #define V86_AH(regs) (((u_char *)&((regs)->tf_eax))[1])
regs 161 arch/i386/i386/vm86.c #define V86_AL(regs) (((u_char *)&((regs)->tf_eax))[0])
regs 414 arch/i386/i386/vm86.c #define DOVREG(reg) tf->tf_vm86_##reg = (u_short) vm86s.regs.vmsc.sc_##reg
regs 415 arch/i386/i386/vm86.c #define DOREG(reg) tf->tf_##reg = (u_short) vm86s.regs.vmsc.sc_##reg
regs 439 arch/i386/i386/vm86.c set_vflags(p, vm86s.regs.vmsc.sc_eflags | PSL_VM);
regs 57 arch/i386/include/apmvar.h #define APM_ERR_CODE(regs) (((regs)->ax & 0xff00) >> 8)
regs 48 arch/i386/include/db_machdep.h #define PC_REGS(regs) ((db_addr_t)(regs)->tf_eip)
regs 49 arch/i386/include/db_machdep.h #define SET_PC_REGS(regs, value) (regs)->tf_eip = (int)(value)
regs 55 arch/i386/include/db_machdep.h #define FIXUP_PC_AFTER_BREAK(regs) ((regs)->tf_eip -= BKPT_SIZE)
regs 57 arch/i386/include/db_machdep.h #define db_clear_single_step(regs) ((regs)->tf_eflags &= ~PSL_T)
regs 58 arch/i386/include/db_machdep.h #define db_set_single_step(regs) ((regs)->tf_eflags |= PSL_T)
regs 60 arch/i386/include/vm86.h struct vm86_regs regs;
regs 434 arch/i386/isa/clock.c rtcget(mc_todregs *regs)
regs 438 arch/i386/isa/clock.c MC146818_GETTOD(NULL, regs); /* XXX softc */
regs 443 arch/i386/isa/clock.c rtcput(mc_todregs *regs)
regs 445 arch/i386/isa/clock.c MC146818_PUTTOD(NULL, regs); /* XXX softc */
regs 144 arch/i386/pci/piixpcib.c struct kvm86regs regs;
regs 147 arch/i386/pci/piixpcib.c memset(®s, 0, sizeof(struct kvm86regs));
regs 148 arch/i386/pci/piixpcib.c regs.eax = PIIXPCIB_IST_CALL;
regs 149 arch/i386/pci/piixpcib.c regs.edx = PIIXPCIB_ISGE;
regs 150 arch/i386/pci/piixpcib.c kvm86_simplecall(0x15, ®s);
regs 152 arch/i386/pci/piixpcib.c if (regs.eax == PIIXPCIB_ISGE) {
regs 153 arch/i386/pci/piixpcib.c sc->sc_sig = regs.eax;
regs 154 arch/i386/pci/piixpcib.c sc->sc_smi_port = regs.ebx & 0xff;
regs 156 arch/i386/pci/piixpcib.c cmd = (regs.ebx >> 16) & 0xff;
regs 162 arch/i386/pci/piixpcib.c sc->sc_smi_data = regs.ecx;
regs 163 arch/i386/pci/piixpcib.c sc->sc_flags = regs.edx;
regs 36 arch/i386/stand/libsa/cpuprobe.c cpuid(u_int32_t eax, u_int32_t *regs)
regs 45 arch/i386/stand/libsa/cpuprobe.c : "0" (eax), "S" (regs)
regs 55 arch/i386/stand/libsa/cpuprobe.c u_int32_t regs[4];
regs 88 arch/i386/stand/libsa/cpuprobe.c cpuid_max = cpuid(0, regs); /* Highest std call */
regs 90 arch/i386/stand/libsa/cpuprobe.c bcopy(®s[1], cpu_vendor, sizeof(regs[1]));
regs 91 arch/i386/stand/libsa/cpuprobe.c bcopy(®s[3], cpu_vendor + 4, sizeof(regs[3]));
regs 92 arch/i386/stand/libsa/cpuprobe.c bcopy(®s[2], cpu_vendor + 8, sizeof(regs[2]));
regs 98 arch/i386/stand/libsa/cpuprobe.c id = cpuid(1, regs); /* Get basic info */
regs 103 arch/i386/stand/libsa/cpuprobe.c feature_ecx = regs[2];
regs 104 arch/i386/stand/libsa/cpuprobe.c feature_edx = regs[3];
regs 107 arch/i386/stand/libsa/cpuprobe.c extended_max = cpuid(0x80000000, regs); /* Highest ext */
regs 110 arch/i386/stand/libsa/cpuprobe.c cpuid(0x80000001, regs);
regs 111 arch/i386/stand/libsa/cpuprobe.c feature_amd = regs[3];
regs 77 compat/freebsd/freebsd_ptrace.c struct reg regs;
regs 108 compat/freebsd/freebsd_ptrace.c SCARG(&npa, addr) = (caddr_t)&nrp->regs;
regs 118 compat/freebsd/freebsd_ptrace.c netbsd_to_freebsd_ptrace_regs(&nrp->regs, &nrp->fpregs, &fr);
regs 130 compat/freebsd/freebsd_ptrace.c &nrp->regs, &nrp->fpregs);
regs 133 compat/freebsd/freebsd_ptrace.c SCARG(&npa, addr) = (caddr_t)&nrp->regs;
regs 78 ddb/db_run.c db_stop_at_pc(db_regs_t *regs, boolean_t *is_breakpoint)
regs 85 ddb/db_run.c old_pc = pc = PC_REGS(regs);
regs 93 ddb/db_run.c FIXUP_PC_AFTER_BREAK(regs);
regs 94 ddb/db_run.c pc = PC_REGS(regs);
regs 104 ddb/db_run.c db_clear_single_step(regs);
regs 116 ddb/db_run.c PC_ADVANCE(regs);
regs 119 ddb/db_run.c SET_PC_REGS(regs, old_pc);
regs 121 ddb/db_run.c PC_REGS(regs) = old_pc;
regs 125 ddb/db_run.c db_clear_single_step(regs);
regs 184 ddb/db_run.c db_restart_at_pc(db_regs_t *regs, boolean_t watchpt)
regs 186 ddb/db_run.c db_addr_t pc = PC_REGS(regs);
regs 218 ddb/db_run.c db_set_single_step(regs);
regs 224 ddb/db_run.c db_set_single_step(regs);
regs 229 ddb/db_run.c db_single_step(db_regs_t *regs)
regs 233 ddb/db_run.c db_set_single_step(regs);
regs 352 ddb/db_run.c db_set_single_step(db_regs_t *regs)
regs 354 ddb/db_run.c db_addr_t pc = PC_REGS(regs);
regs 365 ddb/db_run.c brpc = branch_taken(inst, pc, getreg_val, regs);
regs 380 ddb/db_run.c db_clear_single_step(db_regs_t *regs)
regs 224 ddb/db_watch.c db_find_watchpoint(struct vm_map *map, db_addr_t addr, db_regs_t *regs)
regs 249 ddb/db_watch.c db_single_step(regs);
regs 179 dev/cardbus/if_rtw_cardbus.c rtw_cardbus_intr_ack(struct rtw_regs *regs)
regs 181 dev/cardbus/if_rtw_cardbus.c RTW_WRITE(regs, RTW_FER, RTW_FER_INTR);
regs 185 dev/cardbus/if_rtw_cardbus.c rtw_cardbus_funcregen(struct rtw_regs *regs, int enable)
regs 188 dev/cardbus/if_rtw_cardbus.c rtw_config0123_enable(regs, 1);
regs 189 dev/cardbus/if_rtw_cardbus.c reg = RTW_READ(regs, RTW_CONFIG3);
regs 191 dev/cardbus/if_rtw_cardbus.c RTW_WRITE(regs, RTW_CONFIG3, reg | RTW_CONFIG3_FUNCREGEN);
regs 193 dev/cardbus/if_rtw_cardbus.c RTW_WRITE(regs, RTW_CONFIG3, reg & ~RTW_CONFIG3_FUNCREGEN);
regs 195 dev/cardbus/if_rtw_cardbus.c rtw_config0123_enable(regs, 0);
regs 203 dev/cardbus/if_rtw_cardbus.c struct rtw_regs *regs = &sc->sc_regs;
regs 235 dev/cardbus/if_rtw_cardbus.c CARDBUS_MAPREG_TYPE_MEM, 0, ®s->r_bt, ®s->r_bh, &adr,
regs 245 dev/cardbus/if_rtw_cardbus.c CARDBUS_MAPREG_TYPE_IO, 0, ®s->r_bt, ®s->r_bh, &adr,
regs 276 dev/cardbus/if_rtw_cardbus.c rtw_cardbus_funcregen(regs, 1);
regs 278 dev/cardbus/if_rtw_cardbus.c RTW_WRITE(regs, RTW_FEMR, RTW_FEMR_INTR);
regs 279 dev/cardbus/if_rtw_cardbus.c RTW_WRITE(regs, RTW_FER, RTW_FER_INTR);
regs 292 dev/cardbus/if_rtw_cardbus.c struct rtw_regs *regs = &sc->sc_regs;
regs 305 dev/cardbus/if_rtw_cardbus.c rtw_cardbus_funcregen(regs, 0);
regs 318 dev/cardbus/if_rtw_cardbus.c regs->r_bt, regs->r_bh, csc->sc_mapsize);
regs 96 dev/ic/dp857xreg.h #define DP857X_GETTOD(sc, regs) \
regs 106 dev/ic/dp857xreg.h (*regs)[i] = dp857x_read(sc, i); \
regs 114 dev/ic/dp857xreg.h #define DP857X_PUTTOD(sc, regs) \
regs 125 dev/ic/dp857xreg.h dp857x_write(sc, i, (*regs)[i]); \
regs 163 dev/ic/mc146818reg.h #define MC146818_GETTOD(sc, regs) \
regs 173 dev/ic/mc146818reg.h (*regs)[i] = mc146818_read(sc, i); \
regs 180 dev/ic/mc146818reg.h #define MC146818_PUTTOD(sc, regs) \
regs 190 dev/ic/mc146818reg.h mc146818_write(sc, i, (*regs)[i]); \
regs 277 dev/ic/rtw.c struct rtw_regs *regs = &sc->sc_regs;
regs 280 dev/ic/rtw.c tcr = RTW_READ(regs, RTW_TCR);
regs 286 dev/ic/rtw.c RTW_WRITE(regs, RTW_TCR, tcr);
regs 287 dev/ic/rtw.c RTW_SYNC(regs, RTW_TCR, RTW_TCR);
regs 288 dev/ic/rtw.c rtw_set_access(regs, RTW_ACCESS_ANAPARM);
regs 290 dev/ic/rtw.c rtw_set_access(regs, RTW_ACCESS_ANAPARM);/* XXX Voodoo from Linux. */
regs 291 dev/ic/rtw.c rtw_set_access(regs, RTW_ACCESS_NONE);
regs 312 dev/ic/rtw.c rtw_set_access1(struct rtw_regs *regs, enum rtw_access naccess)
regs 315 dev/ic/rtw.c KASSERT(regs->r_access >= RTW_ACCESS_NONE &&
regs 316 dev/ic/rtw.c regs->r_access <= RTW_ACCESS_ANAPARM);
regs 318 dev/ic/rtw.c if (naccess == regs->r_access)
regs 323 dev/ic/rtw.c switch (regs->r_access) {
regs 325 dev/ic/rtw.c rtw_anaparm_enable(regs, 0);
regs 328 dev/ic/rtw.c rtw_config0123_enable(regs, 0);
regs 335 dev/ic/rtw.c switch (regs->r_access) {
regs 337 dev/ic/rtw.c rtw_config0123_enable(regs, 1);
regs 342 dev/ic/rtw.c rtw_anaparm_enable(regs, 0);
regs 347 dev/ic/rtw.c switch (regs->r_access) {
regs 349 dev/ic/rtw.c rtw_config0123_enable(regs, 1);
regs 352 dev/ic/rtw.c rtw_anaparm_enable(regs, 1);
regs 362 dev/ic/rtw.c rtw_set_access(struct rtw_regs *regs, enum rtw_access access)
regs 364 dev/ic/rtw.c rtw_set_access1(regs, access);
regs 367 dev/ic/rtw.c rtw_access_string(regs->r_access),
regs 369 dev/ic/rtw.c regs->r_access = access;
regs 376 dev/ic/rtw.c rtw_config0123_enable(struct rtw_regs *regs, int enable)
regs 379 dev/ic/rtw.c ecr = RTW_READ8(regs, RTW_9346CR);
regs 384 dev/ic/rtw.c RTW_WBW(regs, RTW_9346CR, MAX(RTW_CONFIG0, RTW_CONFIG3));
regs 387 dev/ic/rtw.c RTW_WRITE8(regs, RTW_9346CR, ecr);
regs 388 dev/ic/rtw.c RTW_SYNC(regs, RTW_9346CR, RTW_9346CR);
regs 393 dev/ic/rtw.c rtw_anaparm_enable(struct rtw_regs *regs, int enable)
regs 397 dev/ic/rtw.c cfg3 = RTW_READ8(regs, RTW_CONFIG3);
regs 403 dev/ic/rtw.c RTW_WRITE8(regs, RTW_CONFIG3, cfg3);
regs 404 dev/ic/rtw.c RTW_SYNC(regs, RTW_CONFIG3, RTW_CONFIG3);
regs 412 dev/ic/rtw.c struct rtw_regs *regs = &sc->sc_regs;
regs 414 dev/ic/rtw.c anaparm = RTW_READ(regs, RTW_ANAPARM_0);
regs 419 dev/ic/rtw.c RTW_WRITE(regs, RTW_ANAPARM_0, anaparm);
regs 420 dev/ic/rtw.c RTW_SYNC(regs, RTW_ANAPARM_0, RTW_ANAPARM_0);
regs 424 dev/ic/rtw.c rtw_chip_reset1(struct rtw_regs *regs, const char *dvname)
regs 429 dev/ic/rtw.c RTW_WRITE8(regs, RTW_CR, RTW_CR_RST);
regs 431 dev/ic/rtw.c RTW_WBR(regs, RTW_CR, RTW_CR);
regs 434 dev/ic/rtw.c if ((cr = RTW_READ8(regs, RTW_CR) & RTW_CR_RST) == 0) {
regs 439 dev/ic/rtw.c RTW_RBR(regs, RTW_CR, RTW_CR);
regs 448 dev/ic/rtw.c rtw_chip_reset(struct rtw_regs *regs, const char *dvname)
regs 456 dev/ic/rtw.c RTW_WRITE(regs, RTW_TCR, tcr);
regs 458 dev/ic/rtw.c RTW_WBW(regs, RTW_CR, RTW_TCR);
regs 460 dev/ic/rtw.c return rtw_chip_reset1(regs, dvname);
regs 464 dev/ic/rtw.c rtw_recall_eeprom(struct rtw_regs *regs, const char *dvname)
regs 469 dev/ic/rtw.c ecr = RTW_READ8(regs, RTW_9346CR);
regs 471 dev/ic/rtw.c RTW_WRITE8(regs, RTW_9346CR, ecr);
regs 473 dev/ic/rtw.c RTW_WBR(regs, RTW_9346CR, RTW_9346CR);
regs 477 dev/ic/rtw.c ecr = RTW_READ8(regs, RTW_9346CR);
regs 483 dev/ic/rtw.c RTW_RBR(regs, RTW_9346CR, RTW_9346CR);
regs 640 dev/ic/rtw.c rtw_srom_read(struct rtw_regs *regs, u_int32_t flags, struct rtw_srom *sr,
regs 649 dev/ic/rtw.c ecr = RTW_READ8(regs, RTW_9346CR);
regs 665 dev/ic/rtw.c RTW_WRITE8(regs, RTW_9346CR, ecr);
regs 680 dev/ic/rtw.c sd.sd_tag = regs->r_bt;
regs 681 dev/ic/rtw.c sd.sd_bsh = regs->r_bh;
regs 703 dev/ic/rtw.c RTW_WRITE8(regs, RTW_9346CR,
regs 705 dev/ic/rtw.c RTW_WBRW(regs, RTW_9346CR, RTW_9346CR);
regs 707 dev/ic/rtw.c if ((rc = rtw_recall_eeprom(regs, dvname)) != 0)
regs 728 dev/ic/rtw.c rtw_set_rfprog(struct rtw_regs *regs, int rfchipid,
regs 734 dev/ic/rtw.c cfg4 = RTW_READ8(regs, RTW_CONFIG4) & ~RTW_CONFIG4_RFTYPE_MASK;
regs 755 dev/ic/rtw.c RTW_WRITE8(regs, RTW_CONFIG4, cfg4);
regs 757 dev/ic/rtw.c RTW_WBR(regs, RTW_CONFIG4, RTW_CONFIG4);
regs 761 dev/ic/rtw.c RTW_READ8(regs, RTW_CONFIG4)));
regs 806 dev/ic/rtw.c rtw_identify_country(struct rtw_regs *regs, enum rtw_locale *locale)
regs 808 dev/ic/rtw.c u_int8_t cfg0 = RTW_READ8(regs, RTW_CONFIG0);
regs 828 dev/ic/rtw.c rtw_identify_sta(struct rtw_regs *regs, u_int8_t (*addr)[IEEE80211_ADDR_LEN],
regs 834 dev/ic/rtw.c u_int32_t idr0 = RTW_READ(regs, RTW_IDR0),
regs 835 dev/ic/rtw.c idr1 = RTW_READ(regs, RTW_IDR1);
regs 1100 dev/ic/rtw.c rtw_io_enable(struct rtw_regs *regs, u_int8_t flags, int enable)
regs 1107 dev/ic/rtw.c cr = RTW_READ8(regs, RTW_CR);
regs 1115 dev/ic/rtw.c RTW_RBW(regs, RTW_CR, RTW_CR); /* XXX paranoia? */
regs 1120 dev/ic/rtw.c RTW_WRITE8(regs, RTW_CR, cr);
regs 1121 dev/ic/rtw.c RTW_SYNC(regs, RTW_CR, RTW_CR);
regs 1606 dev/ic/rtw.c struct rtw_regs *regs = &sc->sc_regs;
regs 1620 dev/ic/rtw.c RTW_WRITE(regs, tdb->tdb_basereg, tdb->tdb_base);
regs 1626 dev/ic/rtw.c RTW_WRITE(regs, RTW_RDSAR, RTW_RING_BASE(sc, hd_rx));
regs 1632 dev/ic/rtw.c RTW_SYNC(regs, RTW_TLPDA, RTW_RDSAR);
regs 1680 dev/ic/rtw.c rtw_txring_next(struct rtw_regs *regs, struct rtw_txdesc_blk *tdb)
regs 1682 dev/ic/rtw.c return (letoh32(RTW_READ(regs, tdb->tdb_basereg)) - tdb->tdb_base) /
regs 1692 dev/ic/rtw.c struct rtw_regs *regs = &sc->sc_regs;
regs 1696 dev/ic/rtw.c next = rtw_txring_next(regs, tdb);
regs 1741 dev/ic/rtw.c struct rtw_regs *regs = &sc->sc_regs;
regs 1762 dev/ic/rtw.c rtw_io_enable(regs, cr, 0);
regs 1773 dev/ic/rtw.c RTW_WRITE16(regs, RTW_IMR, 0);
regs 1774 dev/ic/rtw.c RTW_SYNC(regs, RTW_IMR, RTW_IMR);
regs 1777 dev/ic/rtw.c rtw_chip_reset1(regs, sc->sc_dev.dv_xname);
regs 1786 dev/ic/rtw.c RTW_WRITE16(regs, RTW_IMR, sc->sc_inten);
regs 1787 dev/ic/rtw.c RTW_SYNC(regs, RTW_IMR, RTW_IMR);
regs 1790 dev/ic/rtw.c rtw_io_enable(regs, cr, 1);
regs 1835 dev/ic/rtw.c struct rtw_regs *regs = &sc->sc_regs;
regs 1851 dev/ic/rtw.c isr = RTW_READ16(regs, RTW_ISR);
regs 1853 dev/ic/rtw.c RTW_WRITE16(regs, RTW_ISR, isr);
regs 1854 dev/ic/rtw.c RTW_WBR(regs, RTW_ISR, RTW_ISR);
regs 1857 dev/ic/rtw.c (*sc->sc_intr_ack)(regs);
regs 1921 dev/ic/rtw.c struct rtw_regs *regs = &sc->sc_regs;
regs 1932 dev/ic/rtw.c RTW_WRITE16(regs, RTW_IMR, 0);
regs 1934 dev/ic/rtw.c RTW_WBW(regs, RTW_TPPOLL, RTW_IMR);
regs 1939 dev/ic/rtw.c RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL);
regs 1941 dev/ic/rtw.c RTW_SYNC(regs, RTW_TPPOLL, RTW_IMR);
regs 1985 dev/ic/rtw.c rtw_maxim_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power,
regs 1990 dev/ic/rtw.c anaparm = RTW_READ(regs, RTW_ANAPARM_0);
regs 2017 dev/ic/rtw.c RTW_WRITE(regs, RTW_ANAPARM_0, anaparm);
regs 2018 dev/ic/rtw.c RTW_SYNC(regs, RTW_ANAPARM_0, RTW_ANAPARM_0);
regs 2025 dev/ic/rtw.c rtw_rfmd_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power,
regs 2030 dev/ic/rtw.c anaparm = RTW_READ(regs, RTW_ANAPARM_0);
regs 2057 dev/ic/rtw.c RTW_WRITE(regs, RTW_ANAPARM_0, anaparm);
regs 2058 dev/ic/rtw.c RTW_SYNC(regs, RTW_ANAPARM_0, RTW_ANAPARM_0);
regs 2062 dev/ic/rtw.c rtw_philips_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power,
regs 2067 dev/ic/rtw.c anaparm = RTW_READ(regs, RTW_ANAPARM_0);
regs 2099 dev/ic/rtw.c RTW_WRITE(regs, RTW_ANAPARM_0, anaparm);
regs 2100 dev/ic/rtw.c RTW_SYNC(regs, RTW_ANAPARM_0, RTW_ANAPARM_0);
regs 2104 dev/ic/rtw.c rtw_rtl_pwrstate(struct rtw_regs *regs, enum rtw_pwrstate power,
regs 2114 dev/ic/rtw.c struct rtw_regs *regs = &sc->sc_regs;
regs 2116 dev/ic/rtw.c rtw_set_access(regs, RTW_ACCESS_ANAPARM);
regs 2118 dev/ic/rtw.c (*sc->sc_pwrstate_cb)(regs, power, before_rf, digphy);
regs 2120 dev/ic/rtw.c rtw_set_access(regs, RTW_ACCESS_NONE);
regs 2246 dev/ic/rtw.c struct rtw_regs *regs = &sc->sc_regs;
regs 2249 dev/ic/rtw.c tcr = RTW_READ(regs, RTW_TCR);
regs 2265 dev/ic/rtw.c RTW_WRITE(regs, RTW_TCR, tcr);
regs 2266 dev/ic/rtw.c RTW_SYNC(regs, RTW_TCR, RTW_TCR);
regs 2272 dev/ic/rtw.c struct rtw_regs *regs = &sc->sc_regs;
regs 2277 dev/ic/rtw.c RTW_WRITE16(regs, RTW_IMR, sc->sc_inten);
regs 2278 dev/ic/rtw.c RTW_WBW(regs, RTW_IMR, RTW_ISR);
regs 2279 dev/ic/rtw.c RTW_WRITE16(regs, RTW_ISR, 0xffff);
regs 2280 dev/ic/rtw.c RTW_SYNC(regs, RTW_IMR, RTW_ISR);
regs 2284 dev/ic/rtw.c (*sc->sc_intr_ack)(regs);
regs 2321 dev/ic/rtw.c struct rtw_regs *regs = &sc->sc_regs;
regs 2394 dev/ic/rtw.c RTW_WRITE(regs, RTW_MAR0, hashes[0]);
regs 2395 dev/ic/rtw.c RTW_WRITE(regs, RTW_MAR1, hashes[1]);
regs 2396 dev/ic/rtw.c RTW_WRITE(regs, RTW_RCR, sc->sc_rcr);
regs 2397 dev/ic/rtw.c RTW_SYNC(regs, RTW_MAR0, RTW_RCR); /* RTW_MAR0 < RTW_MAR1 < RTW_RCR */
regs 2401 dev/ic/rtw.c sc->sc_dev.dv_xname, RTW_READ(regs, RTW_MAR0),
regs 2402 dev/ic/rtw.c RTW_READ(regs, RTW_MAR1), RTW_READ(regs, RTW_RCR)));
regs 2413 dev/ic/rtw.c struct rtw_regs *regs = &sc->sc_regs;
regs 2435 dev/ic/rtw.c rtw_set_access(regs, RTW_ACCESS_CONFIG);
regs 2437 dev/ic/rtw.c RTW_WRITE8(regs, RTW_MSR, 0x0); /* no link */
regs 2438 dev/ic/rtw.c RTW_WBW(regs, RTW_MSR, RTW_BRSR);
regs 2442 dev/ic/rtw.c RTW_WRITE16(regs, RTW_BRSR, RTW8185_BRSR_MBR_2MBPS);
regs 2444 dev/ic/rtw.c RTW_WRITE16(regs, RTW_BRSR, RTW8180_BRSR_MBR_2MBPS);
regs 2445 dev/ic/rtw.c RTW_SYNC(regs, RTW_BRSR, RTW_BRSR);
regs 2447 dev/ic/rtw.c rtw_set_access(regs, RTW_ACCESS_ANAPARM);
regs 2448 dev/ic/rtw.c rtw_set_access(regs, RTW_ACCESS_NONE);
regs 2451 dev/ic/rtw.c RTW_WRITE(regs, RTW_FEMR, 0xffff);
regs 2452 dev/ic/rtw.c RTW_SYNC(regs, RTW_FEMR, RTW_FEMR);
regs 2454 dev/ic/rtw.c rtw_set_rfprog(regs, sc->sc_rfchipid, sc->sc_dev.dv_xname);
regs 2456 dev/ic/rtw.c RTW_WRITE8(regs, RTW_PHYDELAY, sc->sc_phydelay);
regs 2458 dev/ic/rtw.c RTW_WRITE8(regs, RTW_CRCOUNT, RTW_CRCOUNT_MAGIC);
regs 2460 dev/ic/rtw.c RTW_SYNC(regs, RTW_PHYDELAY, RTW_CRCOUNT);
regs 2468 dev/ic/rtw.c rtw_io_enable(regs, RTW_CR_RE|RTW_CR_TE, 1);
regs 2473 dev/ic/rtw.c RTW_WRITE16(regs, RTW_BSSID16, 0x0);
regs 2474 dev/ic/rtw.c RTW_WRITE(regs, RTW_BSSID32, 0x0);
regs 2491 dev/ic/rtw.c rtw_led_init(struct rtw_regs *regs)
regs 2495 dev/ic/rtw.c rtw_set_access(regs, RTW_ACCESS_CONFIG);
regs 2497 dev/ic/rtw.c cfg0 = RTW_READ8(regs, RTW_CONFIG0);
regs 2499 dev/ic/rtw.c RTW_WRITE8(regs, RTW_CONFIG0, cfg0);
regs 2501 dev/ic/rtw.c cfg1 = RTW_READ8(regs, RTW_CONFIG1);
regs 2507 dev/ic/rtw.c RTW_WRITE8(regs, RTW_CONFIG1, cfg1);
regs 2509 dev/ic/rtw.c rtw_set_access(regs, RTW_ACCESS_NONE);
regs 2555 dev/ic/rtw.c rtw_led_set(struct rtw_led_state *ls, struct rtw_regs *regs, u_int hwverid)
regs 2591 dev/ic/rtw.c val = RTW_READ8(regs, ofs);
regs 2597 dev/ic/rtw.c RTW_WRITE8(regs, ofs, val);
regs 2601 dev/ic/rtw.c RTW_SYNC(regs, ofs, ofs);
regs 3344 dev/ic/rtw.c rtw_idle(struct rtw_regs *regs)
regs 3350 dev/ic/rtw.c RTW_WRITE8(regs, RTW_TPPOLL, RTW_TPPOLL_SALL);
regs 3351 dev/ic/rtw.c RTW_WBR(regs, RTW_TPPOLL, RTW_TPPOLL);
regs 3354 dev/ic/rtw.c (RTW_READ8(regs, RTW_TPPOLL) & RTW_TPPOLL_ACTIVE) != 0; active++)
regs 3427 dev/ic/rtw.c struct rtw_regs *regs = &sc->sc_regs;
regs 3430 dev/ic/rtw.c RTW_WRITE8(regs, RTW_BSSID + i, bssid[i]);
regs 3432 dev/ic/rtw.c RTW_SYNC(regs, RTW_BSSID16, RTW_BSSID32);
regs 3434 dev/ic/rtw.c rtw_set_access(regs, RTW_ACCESS_CONFIG);
regs 3438 dev/ic/rtw.c bcnitv = RTW_READ16(regs, RTW_BCNITV) & ~RTW_BCNITV_BCNITV_MASK;
regs 3440 dev/ic/rtw.c RTW_WRITE16(regs, RTW_BCNITV, bcnitv);
regs 3442 dev/ic/rtw.c bintritv = RTW_READ16(regs, RTW_BINTRITV) & ~RTW_BINTRITV_BINTRITV;
regs 3444 dev/ic/rtw.c RTW_WRITE16(regs, RTW_BINTRITV, bintritv);
regs 3446 dev/ic/rtw.c RTW_WRITE16(regs, RTW_ATIMWND, LSHIFT(1, RTW_ATIMWND_ATIMWND));
regs 3447 dev/ic/rtw.c RTW_WRITE16(regs, RTW_ATIMTRITV, LSHIFT(2, RTW_ATIMTRITV_ATIMTRITV));
regs 3448 dev/ic/rtw.c rtw_set_access(regs, RTW_ACCESS_NONE);
regs 3451 dev/ic/rtw.c RTW_WRITE8(regs, RTW8180_SCR, 0);
regs 3453 dev/ic/rtw.c rtw_io_enable(regs, RTW_CR_RE | RTW_CR_TE, 1);
regs 3523 dev/ic/rtw.c rtw_tsf_extend(struct rtw_regs *regs, u_int32_t rstamp)
regs 3527 dev/ic/rtw.c tsfth = RTW_READ(regs, RTW_TSFTRH);
regs 3528 dev/ic/rtw.c tsftl = RTW_READ(regs, RTW_TSFTRL);
regs 3907 dev/ic/rtw.c rtw_check_phydelay(struct rtw_regs *regs, u_int32_t rcr0)
regs 3914 dev/ic/rtw.c RTW_WRITE(regs, RTW_RCR, REVAB);
regs 3915 dev/ic/rtw.c RTW_WBW(regs, RTW_RCR, RTW_RCR);
regs 3916 dev/ic/rtw.c RTW_WRITE(regs, RTW_RCR, REVC);
regs 3918 dev/ic/rtw.c RTW_WBR(regs, RTW_RCR, RTW_RCR);
regs 3919 dev/ic/rtw.c if ((RTW_READ(regs, RTW_RCR) & REVC) == REVC)
regs 3922 dev/ic/rtw.c RTW_WRITE(regs, RTW_RCR, rcr0); /* restore RCR */
regs 3923 dev/ic/rtw.c RTW_SYNC(regs, RTW_RCR, RTW_RCR);
regs 4214 dev/ic/rtw.c rtw_bbp_preinit(struct rtw_regs *regs, u_int antatten0, int dflantb,
regs 4222 dev/ic/rtw.c return rtw_bbp_write(regs, RTW_BBP_ANTATTEN, antatten);
regs 4226 dev/ic/rtw.c rtw_bbp_init(struct rtw_regs *regs, struct rtw_bbpset *bb, int antdiv,
regs 4239 dev/ic/rtw.c if ((rc = rtw_bbp_write(regs, reg, val)) != 0) \
regs 4249 dev/ic/rtw.c if ((rc = rtw_bbp_preinit(regs, bb->bb_antatten, dflantb, freq)) != 0)
regs 4749 dev/ic/rtw.c struct rtw_regs *regs = &sc->sc_regs;
regs 4766 dev/ic/rtw.c if ((rc = rtw_bbp_preinit(regs, sc->sc_bbpset.bb_antatten, dflantb,
regs 4778 dev/ic/rtw.c return rtw_bbp_init(regs, &sc->sc_bbpset, antdiv, dflantb,
regs 4787 dev/ic/rtw.c rtw_bbp_write(struct rtw_regs *regs, u_int addr, u_int val)
regs 4810 dev/ic/rtw.c RTW_RBW(regs, RTW_BB, RTW_BB);
regs 4811 dev/ic/rtw.c RTW_WRITE(regs, RTW_BB, wrbbp);
regs 4812 dev/ic/rtw.c RTW_SYNC(regs, RTW_BB, RTW_BB);
regs 4813 dev/ic/rtw.c RTW_WRITE(regs, RTW_BB, rdbbp);
regs 4814 dev/ic/rtw.c RTW_SYNC(regs, RTW_BB, RTW_BB);
regs 4816 dev/ic/rtw.c if (MASK_AND_RSHIFT(RTW_READ(regs, RTW_BB),
regs 4831 dev/ic/rtw.c rtw_rf_hostbangbits(struct rtw_regs *regs, u_int32_t bits, int lo_to_hi,
regs 4844 dev/ic/rtw.c RTW_WRITE(regs, RTW8180_PHYCFG, reg);
regs 4845 dev/ic/rtw.c RTW_SYNC(regs, RTW8180_PHYCFG, RTW8180_PHYCFG);
regs 4863 dev/ic/rtw.c RTW_WRITE(regs, RTW8180_PHYCFG, reg);
regs 4864 dev/ic/rtw.c RTW_SYNC(regs, RTW8180_PHYCFG, RTW8180_PHYCFG);
regs 4869 dev/ic/rtw.c RTW_WRITE(regs, RTW8180_PHYCFG, reg);
regs 4870 dev/ic/rtw.c RTW_SYNC(regs, RTW8180_PHYCFG, RTW8180_PHYCFG);
regs 4880 dev/ic/rtw.c RTW_WRITE(regs, RTW8180_PHYCFG, reg);
regs 4881 dev/ic/rtw.c RTW_SYNC(regs, RTW8180_PHYCFG, RTW8180_PHYCFG);
regs 4886 dev/ic/rtw.c rtw_rf_rtl8225_hostbangbits(struct rtw_regs *regs, u_int32_t bits, int lo_to_hi,
regs 4895 dev/ic/rtw.c page = RTW_READ8(regs, RTW_PSR);
regs 4896 dev/ic/rtw.c RTW_WRITE8(regs, RTW_PSR, page & ~RTW_PSR_PSEN);
regs 4899 dev/ic/rtw.c reg0 = RTW_READ16(regs, RTW8185_RFPINSOUTPUT) &
regs 4901 dev/ic/rtw.c reg1 = RTW_READ16(regs, RTW8185_RFPINSENABLE);
regs 4902 dev/ic/rtw.c RTW_WRITE16(regs, RTW8185_RFPINSENABLE,
regs 4904 dev/ic/rtw.c reg2 = RTW_READ16(regs, RTW8185_RFPINSSELECT);
regs 4905 dev/ic/rtw.c RTW_WRITE16(regs, RTW8185_RFPINSSELECT,
regs 4909 dev/ic/rtw.c RTW_WRITE16(regs, RTW8185_RFPINSOUTPUT, reg0);
regs 4928 dev/ic/rtw.c RTW_WRITE(regs, RTW8180_PHYCFG, reg);
regs 4929 dev/ic/rtw.c RTW_SYNC(regs, RTW8180_PHYCFG, RTW8180_PHYCFG);
regs 4934 dev/ic/rtw.c RTW_WRITE(regs, RTW8180_PHYCFG, reg);
regs 4935 dev/ic/rtw.c RTW_SYNC(regs, RTW8180_PHYCFG, RTW8180_PHYCFG);
regs 4944 dev/ic/rtw.c RTW_WRITE8(regs, RTW_PSR, page);
regs 4952 dev/ic/rtw.c rtw_rf_macbangbits(struct rtw_regs *regs, u_int32_t reg)
regs 4958 dev/ic/rtw.c RTW_WRITE(regs, RTW8180_PHYCFG, RTW8180_PHYCFG_MAC_POLL | reg);
regs 4960 dev/ic/rtw.c RTW_WBR(regs, RTW8180_PHYCFG, RTW8180_PHYCFG);
regs 4963 dev/ic/rtw.c if ((RTW_READ(regs, RTW8180_PHYCFG) &
regs 4970 dev/ic/rtw.c RTW_RBR(regs, RTW8180_PHYCFG, RTW8180_PHYCFG);
regs 5135 dev/ic/rtw.c struct rtw_regs *regs = (struct rtw_regs *)arg;
regs 5136 dev/ic/rtw.c return (bus_space_read_1(regs->r_bt, regs->r_bh, off));
regs 5142 dev/ic/rtw.c struct rtw_regs *regs = (struct rtw_regs *)arg;
regs 5143 dev/ic/rtw.c return (bus_space_read_2(regs->r_bt, regs->r_bh, off));
regs 5149 dev/ic/rtw.c struct rtw_regs *regs = (struct rtw_regs *)arg;
regs 5150 dev/ic/rtw.c return (bus_space_read_4(regs->r_bt, regs->r_bh, off));
regs 5156 dev/ic/rtw.c struct rtw_regs *regs = (struct rtw_regs *)arg;
regs 5157 dev/ic/rtw.c bus_space_write_1(regs->r_bt, regs->r_bh, off, val);
regs 5163 dev/ic/rtw.c struct rtw_regs *regs = (struct rtw_regs *)arg;
regs 5164 dev/ic/rtw.c bus_space_write_2(regs->r_bt, regs->r_bh, off, val);
regs 5170 dev/ic/rtw.c struct rtw_regs *regs = (struct rtw_regs *)arg;
regs 5171 dev/ic/rtw.c bus_space_write_4(regs->r_bt, regs->r_bh, off, val);
regs 5177 dev/ic/rtw.c struct rtw_regs *regs = (struct rtw_regs *)arg;
regs 5178 dev/ic/rtw.c bus_space_barrier(regs->r_bt, regs->r_bh, MIN(reg0, reg1),
regs 1122 dev/ic/rtwreg.h #define RTW_READ8(regs, ofs) \
regs 1123 dev/ic/rtwreg.h ((*(regs)->r_read8)(regs, ofs))
regs 1125 dev/ic/rtwreg.h #define RTW_READ16(regs, ofs) \
regs 1126 dev/ic/rtwreg.h ((*(regs)->r_read16)(regs, ofs))
regs 1128 dev/ic/rtwreg.h #define RTW_READ(regs, ofs) \
regs 1129 dev/ic/rtwreg.h ((*(regs)->r_read32)(regs, ofs))
regs 1131 dev/ic/rtwreg.h #define RTW_WRITE8(regs, ofs, val) \
regs 1132 dev/ic/rtwreg.h ((*(regs)->r_write8)(regs, ofs, val))
regs 1134 dev/ic/rtwreg.h #define RTW_WRITE16(regs, ofs, val) \
regs 1135 dev/ic/rtwreg.h ((*(regs)->r_write16)(regs, ofs, val))
regs 1137 dev/ic/rtwreg.h #define RTW_WRITE(regs, ofs, val) \
regs 1138 dev/ic/rtwreg.h ((*(regs)->r_write32)(regs, ofs, val))
regs 1140 dev/ic/rtwreg.h #define RTW_ISSET(regs, reg, mask) \
regs 1141 dev/ic/rtwreg.h (RTW_READ((regs), (reg)) & (mask))
regs 1143 dev/ic/rtwreg.h #define RTW_CLR(regs, reg, mask) \
regs 1144 dev/ic/rtwreg.h RTW_WRITE((regs), (reg), RTW_READ((regs), (reg)) & ~(mask))
regs 1174 dev/ic/rtwreg.h #define RTW_BARRIER(regs, reg0, reg1, flags) \
regs 1175 dev/ic/rtwreg.h ((*(regs)->r_barrier)(regs, reg0, reg1, flags))
regs 1181 dev/ic/rtwreg.h #define RTW_SYNC(regs, reg0, reg1) \
regs 1182 dev/ic/rtwreg.h RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_SYNC)
regs 1185 dev/ic/rtwreg.h #define RTW_WBW(regs, reg0, reg1) \
regs 1186 dev/ic/rtwreg.h RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE)
regs 1189 dev/ic/rtwreg.h #define RTW_WBR(regs, reg0, reg1) \
regs 1190 dev/ic/rtwreg.h RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_READ)
regs 1193 dev/ic/rtwreg.h #define RTW_RBR(regs, reg0, reg1) \
regs 1194 dev/ic/rtwreg.h RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_READ)
regs 1197 dev/ic/rtwreg.h #define RTW_RBW(regs, reg0, reg1) \
regs 1198 dev/ic/rtwreg.h RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_WRITE)
regs 1200 dev/ic/rtwreg.h #define RTW_WBRW(regs, reg0, reg1) \
regs 1201 dev/ic/rtwreg.h RTW_BARRIER(regs, reg0, reg1, \
regs 150 dev/microcode/siop/ncr53cxxx.c struct ncrregs regs[] = {
regs 747 dev/microcode/siop/ncr53cxxx.c for (i = 0; i < (sizeof(regs) / sizeof(regs[0])); i++) {
regs 748 dev/microcode/siop/ncr53cxxx.c if (regs[i].addr[arch - 1] >= 0 && reserved(regs[i].name, t))
regs 749 dev/microcode/siop/ncr53cxxx.c return regs[i].addr[arch-1];
regs 156 dev/pci/if_rtw_pci.c struct rtw_regs *regs = &sc->sc_regs;
regs 226 dev/pci/if_rtw_pci.c regs->r_bt = memt;
regs 227 dev/pci/if_rtw_pci.c regs->r_bh = memh;
regs 229 dev/pci/if_rtw_pci.c regs->r_bt = iot;
regs 230 dev/pci/if_rtw_pci.c regs->r_bh = ioh;
regs 4214 dev/pci/pciide.c size, &sl->regs[chan].dma_iohs[reg]) != 0) {
regs 4284 dev/pci/pciide.c sl->regs[chan].cmd_iot = sl->ba5_st;
regs 4287 dev/pci/pciide.c 9, &sl->regs[chan].cmd_baseioh) != 0) {
regs 4293 dev/pci/pciide.c sl->regs[chan].ctl_iot = sl->ba5_st;
regs 4301 dev/pci/pciide.c sl->regs[chan].ctl_ioh = cp->ctl_baseioh;
regs 4304 dev/pci/pciide.c if (bus_space_subregion(sl->regs[chan].cmd_iot,
regs 4305 dev/pci/pciide.c sl->regs[chan].cmd_baseioh,
regs 4307 dev/pci/pciide.c &sl->regs[chan].cmd_iohs[i]) != 0) {
regs 4314 dev/pci/pciide.c sl->regs[chan].cmd_iohs[wdr_status & _WDC_REGMASK] =
regs 4315 dev/pci/pciide.c sl->regs[chan].cmd_iohs[wdr_command & _WDC_REGMASK];
regs 4316 dev/pci/pciide.c sl->regs[chan].cmd_iohs[wdr_features & _WDC_REGMASK] =
regs 4317 dev/pci/pciide.c sl->regs[chan].cmd_iohs[wdr_error & _WDC_REGMASK];
regs 4318 dev/pci/pciide.c wdc_cp->data32iot = wdc_cp->cmd_iot = sl->regs[chan].cmd_iot;
regs 4319 dev/pci/pciide.c wdc_cp->data32ioh = wdc_cp->cmd_ioh = sl->regs[chan].cmd_iohs[0];
regs 4333 dev/pci/pciide.c return (bus_space_read_1(sl->regs[chp->channel].ctl_iot,
regs 4334 dev/pci/pciide.c sl->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK));
regs 4336 dev/pci/pciide.c return (bus_space_read_1(sl->regs[chp->channel].cmd_iot,
regs 4337 dev/pci/pciide.c sl->regs[chp->channel].cmd_iohs[reg & _WDC_REGMASK], 0));
regs 4348 dev/pci/pciide.c bus_space_write_1(sl->regs[chp->channel].ctl_iot,
regs 4349 dev/pci/pciide.c sl->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK, val);
regs 4351 dev/pci/pciide.c bus_space_write_1(sl->regs[chp->channel].cmd_iot,
regs 4352 dev/pci/pciide.c sl->regs[chp->channel].cmd_iohs[reg & _WDC_REGMASK],
regs 4362 dev/pci/pciide.c sl->regs[chan].dma_iohs[IDEDMA_CMD(0)], 0));
regs 4371 dev/pci/pciide.c sl->regs[chan].dma_iohs[IDEDMA_CMD(0)], 0, val);
regs 4380 dev/pci/pciide.c sl->regs[chan].dma_iohs[IDEDMA_CTL(0)], 0));
regs 4389 dev/pci/pciide.c sl->regs[chan].dma_iohs[IDEDMA_CTL(0)], 0, val);
regs 4398 dev/pci/pciide.c sl->regs[chan].dma_iohs[IDEDMA_TBL(0)], 0, val);
regs 6492 dev/pci/pciide.c ps->regs[channel].ctl_iot = ps->ba5_st;
regs 6493 dev/pci/pciide.c ps->regs[channel].cmd_iot = ps->ba5_st;
regs 6497 dev/pci/pciide.c &ps->regs[channel].ctl_ioh) != 0) {
regs 6506 dev/pci/pciide.c &ps->regs[channel].cmd_iohs[i]) != 0) {
regs 6514 dev/pci/pciide.c ps->regs[channel].cmd_iohs[wdr_status & _WDC_REGMASK] =
regs 6515 dev/pci/pciide.c ps->regs[channel].cmd_iohs[wdr_command & _WDC_REGMASK];
regs 6516 dev/pci/pciide.c ps->regs[channel].cmd_iohs[wdr_features & _WDC_REGMASK] =
regs 6517 dev/pci/pciide.c ps->regs[channel].cmd_iohs[wdr_error & _WDC_REGMASK];
regs 6519 dev/pci/pciide.c ps->regs[channel].cmd_iot;
regs 6521 dev/pci/pciide.c ps->regs[channel].cmd_iohs[0];
regs 6532 dev/pci/pciide.c &ps->regs[channel].dma_iohs[IDEDMA_CMD(0)]) != 0) {
regs 6540 dev/pci/pciide.c &ps->regs[channel].dma_iohs[IDEDMA_TBL(0)]) != 0) {
regs 6549 dev/pci/pciide.c ps->regs[channel].dma_iohs[IDEDMA_CMD(0)], 0,
regs 6551 dev/pci/pciide.c ps->regs[channel].dma_iohs[IDEDMA_CMD(0)],
regs 6658 dev/pci/pciide.c ps->regs[chan].dma_iohs[IDEDMA_CMD(0)], 0,
regs 6660 dev/pci/pciide.c ps->regs[chan].dma_iohs[IDEDMA_CMD(0)],
regs 6676 dev/pci/pciide.c ps->regs[channel].dma_iohs[IDEDMA_TBL(0)], 0,
regs 6681 dev/pci/pciide.c ps->regs[channel].dma_iohs[IDEDMA_CMD(0)], 0,
regs 6683 dev/pci/pciide.c ps->regs[channel].dma_iohs[IDEDMA_CMD(0)],
regs 6697 dev/pci/pciide.c ps->regs[channel].dma_iohs[IDEDMA_CMD(0)], 0,
regs 6699 dev/pci/pciide.c ps->regs[channel].dma_iohs[IDEDMA_CMD(0)],
regs 6721 dev/pci/pciide.c return (bus_space_read_1(ps->regs[chp->channel].ctl_iot,
regs 6722 dev/pci/pciide.c ps->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK));
regs 6724 dev/pci/pciide.c val = bus_space_read_1(ps->regs[chp->channel].cmd_iot,
regs 6725 dev/pci/pciide.c ps->regs[chp->channel].cmd_iohs[reg & _WDC_REGMASK], 0);
regs 6738 dev/pci/pciide.c bus_space_write_1(ps->regs[chp->channel].ctl_iot,
regs 6739 dev/pci/pciide.c ps->regs[chp->channel].ctl_ioh, reg & _WDC_REGMASK, val);
regs 6741 dev/pci/pciide.c bus_space_write_1(ps->regs[chp->channel].cmd_iot,
regs 6742 dev/pci/pciide.c ps->regs[chp->channel].cmd_iohs[reg & _WDC_REGMASK],
regs 6813 dev/pci/pciide.c iohs = ps->regs[chp->channel].cmd_iohs;
regs 169 dev/pci/pciide_pdc202xx_reg.h } regs[PDC203xx_NCHANNELS];
regs 337 dev/pci/pciide_sii3112_reg.h } regs[4];
regs 152 dev/sbus/stp4020.c return (bus_space_read_2(h->tag, h->regs, o));
regs 162 dev/sbus/stp4020.c bus_space_write_2(h->tag, h->regs, o, v);
regs 173 dev/sbus/stp4020.c return (bus_space_read_2(h->tag, h->regs, o));
regs 185 dev/sbus/stp4020.c bus_space_write_2(h->tag, h->regs, o, v);
regs 57 dev/sbus/stp4020var.h bus_space_handle_t regs; /* */
regs 50 dev/sdmmc/sdhc.c u_int8_t regs[14]; /* host controller state */
regs 274 dev/sdmmc/sdhc.c for (i = 0; i < sizeof hp->regs; i++)
regs 275 dev/sdmmc/sdhc.c hp->regs[i] = HREAD1(hp, i);
regs 284 dev/sdmmc/sdhc.c for (i = 0; i < sizeof hp->regs; i++)
regs 285 dev/sdmmc/sdhc.c HWRITE1(hp, i, hp->regs[i]);
regs 830 dev/usb/if_zyd.c uint16_t regs[2];
regs 833 dev/usb/if_zyd.c regs[0] = htole16(ZYD_REG32_HI(reg));
regs 834 dev/usb/if_zyd.c regs[1] = htole16(ZYD_REG32_LO(reg));
regs 835 dev/usb/if_zyd.c error = zyd_cmd(sc, ZYD_CMD_IORD, regs, sizeof regs, tmp, sizeof tmp,
regs 300 kern/kgdb_stub.c kgdb_trap(int type, db_regs_t *regs)
regs 315 kern/kgdb_stub.c type, (void *)PC_REGS(regs));
regs 347 kern/kgdb_stub.c FIXUP_PC_AFTER_BREAK(regs);
regs 351 kern/kgdb_stub.c PC_ADVANCE(regs);
regs 353 kern/kgdb_stub.c PC_REGS(regs) += BKPT_SIZE;
regs 363 kern/kgdb_stub.c kgdb_getregs(regs, gdb_regs);
regs 401 kern/kgdb_stub.c kgdb_setregs(regs, gdb_regs);
regs 464 kern/kgdb_stub.c db_clear_single_step(regs);
regs 471 kern/kgdb_stub.c db_clear_single_step(regs);
regs 482 kern/kgdb_stub.c PC_REGS(regs) = addr;
regs 484 kern/kgdb_stub.c db_clear_single_step(regs);
regs 495 kern/kgdb_stub.c PC_REGS(regs) = addr;
regs 497 kern/kgdb_stub.c db_set_single_step(regs);
regs 88 kern/sys_process.c struct reg *regs;
regs 446 kern/sys_process.c regs = malloc(sizeof(*regs), M_TEMP, M_WAITOK);
regs 447 kern/sys_process.c error = copyin(SCARG(uap, addr), regs, sizeof(*regs));
regs 449 kern/sys_process.c error = process_write_regs(t, regs);
regs 451 kern/sys_process.c free(regs, M_TEMP);
regs 458 kern/sys_process.c regs = malloc(sizeof(*regs), M_TEMP, M_WAITOK);
regs 459 kern/sys_process.c error = process_read_regs(t, regs);
regs 461 kern/sys_process.c error = copyout(regs,
regs 462 kern/sys_process.c SCARG(uap, addr), sizeof (*regs));
regs 463 kern/sys_process.c free(regs, M_TEMP);
regs 100 sys/ptrace.h int process_read_fpregs(struct proc *p, struct fpreg *regs);
regs 102 sys/ptrace.h int process_read_regs(struct proc *p, struct reg *regs);
regs 106 sys/ptrace.h int process_write_fpregs(struct proc *p, struct fpreg *regs);
regs 108 sys/ptrace.h int process_write_regs(struct proc *p, struct reg *regs);