1 /* $OpenBSD: rtwreg.h,v 1.13 2006/01/05 05:40:35 jsg Exp $ */
2 /* $NetBSD: rtwreg.h,v 1.12 2005/01/16 11:50:43 dyoung Exp $ */
3 /*-
4 * Copyright (c) 2004, 2005 David Young. All rights reserved.
5 *
6 * Programmed for NetBSD by David Young.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The name of David Young may not be used to endorse or promote
17 * products derived from this software without specific prior
18 * written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
23 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David
24 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
26 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
31 * OF SUCH DAMAGE.
32 */
33 /* Macros for bit twiddling. */
34 /* TBD factor w/ dev/ic/atwreg.h. */
35
36 #ifndef _BIT_TWIDDLE
37 #define _BIT_TWIDDLE
38 /* nth bit, BIT(0) == 0x1. */
39 #define BIT(n) (((n) == 32) ? 0 : ((u_int32_t)1 << (n)))
40
41 /* bits m through n, m < n. */
42 #define BITS(m, n) ((BIT(MAX((m), (n)) + 1) - 1) ^ (BIT(MIN((m), (n))) - 1))
43
44 /* find least significant bit that is set */
45 #define LOWEST_SET_BIT(x) ((((x) - 1) & (x)) ^ (x))
46
47 /* for x a power of two and p a non-negative integer, is x a greater
48 * power than 2**p?
49 */
50 #define GTEQ_POWER(x, p) (((u_long)(x) >> (p)) != 0)
51
52 #define MASK_TO_SHIFT2(m) (GTEQ_POWER(LOWEST_SET_BIT((m)), 1) ? 1 : 0)
53
54 #define MASK_TO_SHIFT4(m) \
55 (GTEQ_POWER(LOWEST_SET_BIT((m)), 2) \
56 ? 2 + MASK_TO_SHIFT2((m) >> 2) \
57 : MASK_TO_SHIFT2((m)))
58
59 #define MASK_TO_SHIFT8(m) \
60 (GTEQ_POWER(LOWEST_SET_BIT((m)), 4) \
61 ? 4 + MASK_TO_SHIFT4((m) >> 4) \
62 : MASK_TO_SHIFT4((m)))
63
64 #define MASK_TO_SHIFT16(m) \
65 (GTEQ_POWER(LOWEST_SET_BIT((m)), 8) \
66 ? 8 + MASK_TO_SHIFT8((m) >> 8) \
67 : MASK_TO_SHIFT8((m)))
68
69 #define MASK_TO_SHIFT(m) \
70 (GTEQ_POWER(LOWEST_SET_BIT((m)), 16) \
71 ? 16 + MASK_TO_SHIFT16((m) >> 16) \
72 : MASK_TO_SHIFT16((m)))
73
74 #define MASK_AND_RSHIFT(x, mask) (((x) & (mask)) >> MASK_TO_SHIFT(mask))
75 #define LSHIFT(x, mask) ((x) << MASK_TO_SHIFT(mask))
76 #define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask))
77 #define PRESHIFT(m) MASK_AND_RSHIFT((m), (m))
78
79 #endif /* _BIT_TWIDDLE */
80
81 /* RTL8180/RTL8185 Host Control and Status Registers */
82
83 #define RTW_IDR0 0x00 /* ID Register: MAC addr, 6 bytes.
84 * Auto-loaded from EEPROM. Read by byte,
85 * by word, or by double word, but write
86 * only by double word.
87 */
88 #define RTW_IDR1 0x04
89
90 #define RTW_MAR0 0x08 /* Multicast filter, 64b. */
91 #define RTW_MAR1 0x0c
92
93 #define RTW_TSFTRL 0x18 /* Timing Synchronization Function Timer
94 * Register, low word, 32b, read-only.
95 */
96 #define RTW_TSFTRH 0x1c /* High word, 32b, read-only. */
97 #define RTW_TLPDA 0x20 /* Transmit Low Priority Descriptors Start
98 * Address, 32b, 256-byte alignment.
99 */
100 #define RTW_TNPDA 0x24 /* Transmit Normal Priority Descriptors Start
101 * Address, 32b, 256-byte alignment.
102 */
103 #define RTW_THPDA 0x28 /* Transmit High Priority Descriptors Start
104 * Address, 32b, 256-byte alignment.
105 */
106
107 #define RTW_BRSR 0x2c /* Basic Rate Set Register, 16b */
108 #define RTW8180_BRSR_BPLCP BIT(8) /* 1: Short PLCP CTS/ACK header */
109 #define RTW8180_BRSR_MBR_MASK BITS(1,0) /* Basic Service Rate */
110 #define RTW8180_BRSR_MBR_1MBPS LSHIFT(0, RTW8180_BRSR_MBR_MASK)
111 #define RTW8180_BRSR_MBR_2MBPS LSHIFT(1, RTW8180_BRSR_MBR_MASK)
112 #define RTW8180_BRSR_MBR_5MBPS LSHIFT(2, RTW8180_BRSR_MBR_MASK)
113 #define RTW8180_BRSR_MBR_11MBPS LSHIFT(3, RTW8180_BRSR_MBR_MASK)
114 #define RTW8185_BRSR_MBR_MASK BITS(11, 0) /* Basic Service Rate */
115 #define RTW8185_BRSR_MBR_1MBPS BIT(0)
116 #define RTW8185_BRSR_MBR_2MBPS BIT(1)
117 #define RTW8185_BRSR_MBR_5MBPS BIT(2)
118 #define RTW8185_BRSR_MBR_11MBPS BIT(3)
119 #define RTW8185_BRSR_MBR_6MBPS BIT(4)
120 #define RTW8185_BRSR_MBR_9MBPS BIT(5)
121 #define RTW8185_BRSR_MBR_12MBPS BIT(6)
122 #define RTW8185_BRSR_MBR_18MBPS BIT(7)
123 #define RTW8185_BRSR_MBR_24MBPS BIT(8)
124 #define RTW8185_BRSR_MBR_36MBPS BIT(9)
125 #define RTW8185_BRSR_MBR_48MBPS BIT(10)
126 #define RTW8185_BRSR_MBR_54MBPS BIT(11)
127
128 #define RTW_BSSID 0x2e
129 /* BSSID, 6 bytes */
130 #define RTW_BSSID16 0x2e /* first two bytes */
131 #define RTW_BSSID32 (0x2e + 4) /* remaining four bytes */
132 #define RTW_BSSID0 RTW_BSSID16 /* BSSID[0], 8b */
133 #define RTW_BSSID1 (RTW_BSSID0 + 1) /* BSSID[1], 8b */
134 #define RTW_BSSID2 (RTW_BSSID1 + 1) /* BSSID[2], 8b */
135 #define RTW_BSSID3 (RTW_BSSID2 + 1) /* BSSID[3], 8b */
136 #define RTW_BSSID4 (RTW_BSSID3 + 1) /* BSSID[4], 8b */
137 #define RTW_BSSID5 (RTW_BSSID4 + 1) /* BSSID[5], 8b */
138
139 #define RTW8185_RR 0x34 /* Response Rate Register, 8b */
140 #define RTW8185_RR_MAX BIT(7, 4)
141 #define RTW8185_RR_MAX_1MPBS LSHIFT(0, RTW8185_RR_MAX_MASK)
142 #define RTW8185_RR_MAX_2MPBS LSHIFT(1, RTW8185_RR_MAX_MASK)
143 #define RTW8185_RR_MAX_5MPBS LSHIFT(2, RTW8185_RR_MAX_MASK)
144 #define RTW8185_RR_MAX_11MPBS LSHIFT(3, RTW8185_RR_MAX_MASK)
145 #define RTW8185_RR_MAX_6MPBS LSHIFT(4, RTW8185_RR_MAX_MASK)
146 #define RTW8185_RR_MAX_9MPBS LSHIFT(5, RTW8185_RR_MAX_MASK)
147 #define RTW8185_RR_MAX_12MPBS LSHIFT(6, RTW8185_RR_MAX_MASK)
148 #define RTW8185_RR_MAX_18MPBS LSHIFT(7, RTW8185_RR_MAX_MASK)
149 #define RTW8185_RR_MAX_24MPBS LSHIFT(8, RTW8185_RR_MAX_MASK)
150 #define RTW8185_RR_MAX_36MPBS LSHIFT(9, RTW8185_RR_MAX_MASK)
151 #define RTW8185_RR_MAX_48MPBS LSHIFT(10, RTW8185_RR_MAX_MASK)
152 #define RTW8185_RR_MAX_54MPBS LSHIFT(11, RTW8185_RR_MAX_MASK)
153 #define RTW8185_RR_MIN_MASK BIT(3, 0)
154 #define RTW8185_RR_MIN_1MPBS LSHIFT(0, RTW8185_RR_MIN_MASK)
155 #define RTW8185_RR_MIN_2MPBS LSHIFT(1, RTW8185_RR_MIN_MASK)
156 #define RTW8185_RR_MIN_5MPBS LSHIFT(2, RTW8185_RR_MIN_MASK)
157 #define RTW8185_RR_MIN_11MPBS LSHIFT(3, RTW8185_RR_MIN_MASK)
158 #define RTW8185_RR_MIN_6MPBS LSHIFT(4, RTW8185_RR_MIN_MASK)
159 #define RTW8185_RR_MIN_9MPBS LSHIFT(5, RTW8185_RR_MIN_MASK)
160 #define RTW8185_RR_MIN_12MPBS LSHIFT(6, RTW8185_RR_MIN_MASK)
161 #define RTW8185_RR_MIN_18MPBS LSHIFT(7, RTW8185_RR_MIN_MASK)
162 #define RTW8185_RR_MIN_24MPBS LSHIFT(8, RTW8185_RR_MIN_MASK)
163 #define RTW8185_RR_MIN_36MPBS LSHIFT(9, RTW8185_RR_MIN_MASK)
164 #define RTW8185_RR_MIN_48MPBS LSHIFT(10, RTW8185_RR_MIN_MASK)
165 #define RTW8185_RR_MIN_54MPBS LSHIFT(11, RTW8185_RR_MIN_MASK)
166
167 #define RTW8185_EIFS_TIMER 0x35 /* Extended IFS Register, 16b ??? */
168
169 #define RTW_CR 0x37 /* Command Register, 8b */
170 #define RTW_CR_RST BIT(4) /* Reset: host sets to 1 to disable
171 * transmitter & receiver, reinitialize FIFO.
172 * RTL8180L sets to 0 to signal completion.
173 */
174 #define RTW_CR_RE BIT(3) /* Receiver Enable: host enables receiver
175 * by writing 1. RTL8180L indicates receiver
176 * is active with 1. After power-up, host
177 * must wait for reset before writing.
178 */
179 #define RTW_CR_TE BIT(2) /* Transmitter Enable: host enables transmitter
180 * by writing 1. RTL8180L indicates transmitter
181 * is active with 1. After power-up, host
182 * must wait for reset before writing.
183 */
184 #define RTW_CR_MULRW BIT(0) /* PCI Multiple Read/Write enable: 1 enables,
185 * 0 disables. XXX RTL8180, only?
186 */
187
188 #define RTW_IMR 0x3c /* Interrupt Mask Register, 16b */
189 #define RTW_ISR 0x3e /* Interrupt status register, 16b */
190
191 #define RTW_INTR_TXFOVW BIT(15) /* Tx FIFO underrflow */
192 #define RTW_INTR_TIMEOUT BIT(14) /* Time Out: 1 indicates
193 * RTW_TSFTR[0:31] = RTW_TINT
194 */
195 #define RTW_INTR_BCNINT BIT(13) /* Beacon Time Out: time for host to
196 * prepare beacon:
197 * RTW_TSFTR % (RTW_BCNITV_BCNITV * TU) =
198 * (RTW_BCNITV_BCNITV * TU - RTW_BINTRITV)
199 */
200 #define RTW_INTR_ATIMINT BIT(12)
201 /* ATIM Time Out: ATIM interval will pass,
202 * RTW_TSFTR % (RTW_BCNITV_BCNITV * TU) =
203 * (RTW_ATIMWND_ATIMWND * TU - RTW_ATIMTRITV)
204 */
205 #define RTW_INTR_TBDER BIT(11) /* Tx Beacon Descriptor Error:
206 * beacon transmission aborted because
207 * frame Rx'd
208 */
209 #define RTW_INTR_TBDOK BIT(10) /* Tx Beacon Descriptor OK */
210 #define RTW_INTR_THPDER BIT(9) /* Tx High Priority Descriptor Error:
211 * reached short/long retry limit
212 */
213 #define RTW_INTR_THPDOK BIT(8) /* Tx High Priority Descriptor OK */
214 #define RTW_INTR_TNPDER BIT(7) /* Tx Normal Priority Descriptor Error:
215 * reached short/long retry limit
216 */
217 #define RTW_INTR_TNPDOK BIT(6) /* Tx Normal Priority Descriptor OK */
218 #define RTW_INTR_RXFOVW BIT(5) /* Rx FIFO Overflow: either RDU (see below)
219 * or PCI bus too slow/busy
220 */
221 #define RTW_INTR_RDU BIT(4) /* Rx Descriptor Unavailable */
222 #define RTW_INTR_TLPDER BIT(3) /* Tx Normal Priority Descriptor Error
223 * reached short/long retry limit
224 */
225 #define RTW_INTR_TLPDOK BIT(2) /* Tx Normal Priority Descriptor OK */
226 #define RTW_INTR_RER BIT(1) /* Rx Error: CRC32 or ICV error */
227 #define RTW_INTR_ROK BIT(0) /* Rx OK */
228
229 /* Convenient interrupt conjunctions. */
230 #define RTW_INTR_RX (RTW_INTR_RER|RTW_INTR_ROK)
231 #define RTW_INTR_TX (RTW_INTR_TLPDER|RTW_INTR_TLPDOK|RTW_INTR_THPDER|\
232 RTW_INTR_THPDOK|RTW_INTR_TNPDER|RTW_INTR_TNPDOK|\
233 RTW_INTR_TBDER|RTW_INTR_TBDOK)
234 #define RTW_INTR_BEACON (RTW_INTR_BCNINT|RTW_INTR_TBDER|RTW_INTR_TBDOK)
235 #define RTW_INTR_IOERROR (RTW_INTR_TXFOVW|RTW_INTR_RXFOVW|RTW_INTR_RDU)
236
237 #define RTW_TCR 0x40 /* Transmit Configuration Register, 32b */
238 #define RTW_TCR_CWMIN BIT(31) /* 1: CWmin = 8, 0: CWmin = 32. */
239 #define RTW_TCR_SWSEQ BIT(30) /* 1: host assigns 802.11 sequence number,
240 * 0: hardware assigns sequence number
241 */
242 #define RTW8185_TCR_NOPROBERSPTO BIT(29) /* No Probe Rsp timeout */
243 /* Hardware version ID, read-only */
244 #define RTW_TCR_HWVERID_MASK BITS(27, 25)
245 #define RTW_TCR_HWVERID_RTL8180D BIT(26)
246 #define RTW_TCR_HWVERID_RTL8180F BITS(26, 25)
247 #define RTW_TCR_HWVERID_RTL8185 (BIT(27) | BIT(25))
248 /* Set ACK/CTS Timeout (EIFS).
249 * 1: ACK rate = max(RTW_BRSR_MBR, Rx rate) (XXX not min? typo in datasheet?)
250 * 0: ACK rate = 1Mbps
251 */
252 #define RTW8180_TCR_SAT BIT(24)
253 /* 1: Software PLCP length,
254 * 0: Hardware PLCP length
255 */
256 #define RTW8185_TCR_PLCPLENGTH BIT(24)
257 /* Max DMA Burst Size per Tx DMA Burst */
258 #define RTW_TCR_MXDMA_MASK BITS(23,21)
259 #define RTW_TCR_MXDMA_16 LSHIFT(0, RTW_TCR_MXDMA_MASK)
260 #define RTW_TCR_MXDMA_32 LSHIFT(1, RTW_TCR_MXDMA_MASK)
261 #define RTW_TCR_MXDMA_64 LSHIFT(2, RTW_TCR_MXDMA_MASK)
262 #define RTW_TCR_MXDMA_128 LSHIFT(3, RTW_TCR_MXDMA_MASK)
263 #define RTW_TCR_MXDMA_256 LSHIFT(4, RTW_TCR_MXDMA_MASK)
264 #define RTW_TCR_MXDMA_512 LSHIFT(5, RTW_TCR_MXDMA_MASK)
265 #define RTW_TCR_MXDMA_1024 LSHIFT(6, RTW_TCR_MXDMA_MASK)
266 #define RTW_TCR_MXDMA_2048 LSHIFT(7, RTW_TCR_MXDMA_MASK)
267
268 #define RTW_TCR_DISCW BIT(20) /* disable 802.11 random backoff */
269
270 #define RTW_TCR_ICV BIT(19) /* host lets RTL8180 append ICV to
271 * WEP packets
272 */
273
274 /* Loopback Test: disables TXI/TXQ outputs. */
275 #define RTW_TCR_LBK_MASK BITS(18,17)
276 #define RTW_TCR_LBK_NORMAL LSHIFT(0, RTW_TCR_LBK_MASK) /* normal ops */
277 #define RTW_TCR_LBK_MAC LSHIFT(1, RTW_TCR_LBK_MASK) /* MAC loopback */
278 #define RTW_TCR_LBK_BBP LSHIFT(2, RTW_TCR_LBK_MASK) /* baseband loop. */
279 #define RTW_TCR_LBK_CONT LSHIFT(3, RTW_TCR_LBK_MASK) /* continuous Tx */
280
281 #define RTW_TCR_CRC BIT(16) /* 0: RTL8180 appends CRC32
282 * 1: host appends CRC32
283 *
284 * (I *think* this is right.
285 * The docs have a mysterious
286 * description in the
287 * passive voice.)
288 */
289 #define RTW_TCR_SRL_MASK BITS(15,8) /* Short Retry Limit */
290 #define RTW_TCR_LRL_MASK BITS(7,0) /* Long Retry Limit */
291
292 #define RTW_RCR 0x44 /* Receive Configuration Register, 32b */
293 #define RTW_RCR_ONLYERLPKT BIT(31) /* only do Early Rx on packets
294 * longer than 1536 bytes
295 */
296 #define RTW_RCR_ENCS2 BIT(30) /* enable carrier sense method 2 */
297 #define RTW_RCR_ENCS1 BIT(29) /* enable carrier sense method 1 */
298 #define RTW_RCR_ENMARP BIT(28) /* enable MAC auto-reset PHY */
299 #define RTW_RCR_CBSSID BIT(23) /* Check BSSID/ToDS/FromDS: set
300 * "Link On" when received BSSID
301 * matches RTW_BSSID and received
302 * ToDS/FromDS are appropriate
303 * according to RTW_MSR_NETYPE.
304 */
305 #define RTW_RCR_APWRMGT BIT(22) /* accept packets w/ PWRMGMT bit set */
306 #define RTW_RCR_ADD3 BIT(21) /* when RTW_MSR_NETYPE ==
307 * RTW_MSR_NETYPE_INFRA_OK, accept
308 * broadcast/multicast packets whose
309 * 3rd address matches RTL8180's MAC.
310 */
311 #define RTW_RCR_AMF BIT(20) /* accept management frames */
312 #define RTW_RCR_ACF BIT(19) /* accept control frames */
313 #define RTW_RCR_ADF BIT(18) /* accept data frames */
314 /* Rx FIFO Threshold: RTL8180 begins PCI transfer when this many data
315 * bytes are received
316 */
317 #define RTW8180_RCR_RXFTH_MASK BITS(15,13)
318 #define RTW8180_RCR_RXFTH_64 LSHIFT(2, RTW8180_RCR_RXFTH_MASK)
319 #define RTW8180_RCR_RXFTH_128 LSHIFT(3, RTW8180_RCR_RXFTH_MASK)
320 #define RTW8180_RCR_RXFTH_256 LSHIFT(4, RTW8180_RCR_RXFTH_MASK)
321 #define RTW8180_RCR_RXFTH_512 LSHIFT(5, RTW8180_RCR_RXFTH_MASK)
322 #define RTW8180_RCR_RXFTH_1024 LSHIFT(6, RTW8180_RCR_RXFTH_MASK)
323 #define RTW8180_RCR_RXFTH_WHOLE LSHIFT(7, RTW8180_RCR_RXFTH_MASK)
324
325 #define RTW_RCR_AICV BIT(12) /* accept frames w/ ICV errors */
326
327 /* Max DMA Burst Size per Rx DMA Burst */
328 #define RTW_RCR_MXDMA_MASK BITS(10,8)
329 #define RTW_RCR_MXDMA_16 LSHIFT(0, RTW_RCR_MXDMA_MASK)
330 #define RTW_RCR_MXDMA_32 LSHIFT(1, RTW_RCR_MXDMA_MASK)
331 #define RTW_RCR_MXDMA_64 LSHIFT(2, RTW_RCR_MXDMA_MASK)
332 #define RTW_RCR_MXDMA_128 LSHIFT(3, RTW_RCR_MXDMA_MASK)
333 #define RTW_RCR_MXDMA_256 LSHIFT(4, RTW_RCR_MXDMA_MASK)
334 #define RTW_RCR_MXDMA_512 LSHIFT(5, RTW_RCR_MXDMA_MASK)
335 #define RTW_RCR_MXDMA_1024 LSHIFT(6, RTW_RCR_MXDMA_MASK)
336 #define RTW_RCR_MXDMA_UNLIMITED LSHIFT(7, RTW_RCR_MXDMA_MASK)
337
338 /* EEPROM type, read-only. 1: EEPROM is 93c56, 0: 93c46 */
339 #define RTW_RCR_9356SEL BIT(6)
340
341 #define RTW_RCR_ACRC32 BIT(5) /* accept frames w/ CRC32 errors */
342 #define RTW_RCR_AB BIT(3) /* accept broadcast frames */
343 #define RTW_RCR_AM BIT(2) /* accept multicast frames */
344 /* accept physical match frames. XXX means PLCP header ok? */
345 #define RTW_RCR_APM BIT(1)
346 #define RTW_RCR_AAP BIT(0) /* accept frames w/ destination */
347
348 /* Additional bits to set in monitor mode. */
349 #define RTW_RCR_MONITOR ( \
350 RTW_RCR_AAP | \
351 RTW_RCR_ACF | \
352 RTW_RCR_ACRC32 | \
353 RTW_RCR_AICV | \
354 0)
355
356 /* The packet filter bits. */
357 #define RTW_RCR_PKTFILTER_MASK (\
358 RTW_RCR_AAP | \
359 RTW_RCR_AB | \
360 RTW_RCR_ACF | \
361 RTW_RCR_ACRC32 | \
362 RTW_RCR_ADD3 | \
363 RTW_RCR_ADF | \
364 RTW_RCR_AICV | \
365 RTW_RCR_AM | \
366 RTW_RCR_AMF | \
367 RTW_RCR_APM | \
368 RTW_RCR_APWRMGT | \
369 0)
370
371 /* Receive power-management frames and mgmt/ctrl/data frames. */
372 #define RTW_RCR_PKTFILTER_DEFAULT ( \
373 RTW_RCR_ADF | \
374 RTW_RCR_AMF | \
375 RTW_RCR_APM | \
376 RTW_RCR_APWRMGT | \
377 0)
378
379 #define RTW_TINT 0x48 /* Timer Interrupt Register, 32b */
380 #define RTW_TBDA 0x4c /* Transmit Beacon Descriptor Start Address,
381 * 32b, 256-byte alignment
382 */
383 #define RTW_9346CR 0x50 /* 93c46/93c56 Command Register, 8b */
384 #define RTW_9346CR_EEM_MASK BITS(7,6) /* Operating Mode */
385 #define RTW_9346CR_EEM_NORMAL LSHIFT(0, RTW_9346CR_EEM_MASK)
386 /* Load the EEPROM. Reset registers to defaults.
387 * Takes ~2ms. RTL8180 indicates completion with RTW_9346CR_EEM_NORMAL.
388 * XXX RTL8180 only?
389 */
390 #define RTW_9346CR_EEM_AUTOLOAD LSHIFT(1, RTW_9346CR_EEM_MASK)
391 /* Disable network & bus-master operations and enable
392 * _EECS, _EESK, _EEDI, _EEDO.
393 * XXX RTL8180 only?
394 */
395 #define RTW_9346CR_EEM_PROGRAM LSHIFT(2, RTW_9346CR_EEM_MASK)
396 /* Enable RTW_CONFIG[0123] registers. */
397 #define RTW_9346CR_EEM_CONFIG LSHIFT(3, RTW_9346CR_EEM_MASK)
398 /* EEPROM pin status/control in _EEM_CONFIG, _EEM_AUTOLOAD modes.
399 * XXX RTL8180 only?
400 */
401 #define RTW_9346CR_EECS BIT(3)
402 #define RTW_9346CR_EESK BIT(2)
403 #define RTW_9346CR_EEDI BIT(1)
404 #define RTW_9346CR_EEDO BIT(0) /* read-only */
405
406 #define RTW_CONFIG0 0x51 /* Configuration Register 0, 8b */
407 #define RTW8180_CONFIG0_WEP40 BIT(7) /* implements 40-bit WEP,
408 */
409 #define RTW8180_CONFIG0_WEP104 BIT(6) /* implements 104-bit WEP,
410 * from EEPROM, read-only
411 */
412 #define RTW8180_CONFIG0_LEDGPOEN BIT(4) /* 1: RTW_PSR_LEDGPO[01] control
413 * LED[01] pins.
414 * 0: LED behavior defined by
415 * RTW_CONFIG1_LEDS10_MASK
416 */
417 /* auxiliary power is present, read-only */
418 #define RTW_CONFIG0_AUXPWR BIT(3)
419 /* Geographic Location, read-only */
420 #define RTW8180_CONFIG0_GL_MASK BITS(1,0)
421 #define RTW8180_CONFIG0_GL_USA LSHIFT(3, RTW8180_CONFIG0_GL_MASK)
422 #define RTW8180_CONFIG0_GL_EUROPE LSHIFT(2, RTW8180_CONFIG0_GL_MASK)
423 #define RTW8180_CONFIG0_GL_JAPAN LSHIFT(1, RTW8180_CONFIG0_GL_MASK)
424 #define RTW8180_CONFIG0_GL_JAPAN2 LSHIFT(0, RTW8180_CONFIG0_GL_MASK)
425 /* RTL8181 datasheet says RTW_CONFIG0_GL_JAPAN = 0. */
426
427 #define RTW_CONFIG1 0x52 /* Configuration Register 1, 8b */
428
429 /* LED configuration. From EEPROM. Read/write.
430 *
431 * Setting LED0 LED1
432 * ------- ---- ----
433 * RTW_CONFIG1_LEDS_ACT_INFRA Activity Infrastructure
434 * RTW_CONFIG1_LEDS_ACT_LINK Activity Link
435 * RTW_CONFIG1_LEDS_TX_RX Tx Rx
436 * RTW_CONFIG1_LEDS_LINKACT_INFRA Link/Activity Infrastructure
437 */
438 #define RTW_CONFIG1_LEDS_MASK BITS(7,6)
439 #define RTW_CONFIG1_LEDS_ACT_INFRA LSHIFT(0, RTW_CONFIG1_LEDS_MASK)
440 #define RTW_CONFIG1_LEDS_ACT_LINK LSHIFT(1, RTW_CONFIG1_LEDS_MASK)
441 #define RTW_CONFIG1_LEDS_TX_RX LSHIFT(2, RTW_CONFIG1_LEDS_MASK)
442 #define RTW_CONFIG1_LEDS_LINKACT_INFRA LSHIFT(3, RTW_CONFIG1_LEDS_MASK)
443
444 /* LWAKE Output Signal. Only applicable to Cardbus. Pulse width is 150ms.
445 *
446 * RTW_CONFIG1_LWACT
447 * 0 1
448 * RTW_CONFIG4_LWPTN 0 active high active low
449 * 1 positive pulse negative pulse
450 */
451 #define RTW_CONFIG1_LWACT BIT(4)
452
453 #define RTW_CONFIG1_MEMMAP BIT(3) /* using PCI memory space, read-only */
454 #define RTW_CONFIG1_IOMAP BIT(2) /* using PCI I/O space, read-only */
455 #define RTW_CONFIG1_VPD BIT(1) /* if set, VPD from offsets
456 * 0x40-0x7f in EEPROM are at
457 * registers 0x60-0x67 of PCI
458 * Configuration Space (XXX huh?)
459 */
460 #define RTW_CONFIG1_PMEN BIT(0) /* Power Management Enable: TBD */
461
462 #define RTW_CONFIG2 0x53 /* Configuration Register 2, 8b */
463 #define RTW_CONFIG2_LCK BIT(7) /* clocks are locked, read-only:
464 * Tx frequency & symbol clocks
465 * are derived from the same OSC
466 */
467 #define RTW8180_CONFIG2_ANT BIT(6) /* diversity enabled, read-only */
468 #define RTW_CONFIG2_DPS BIT(3) /* Descriptor Polling State: enable
469 * test mode.
470 */
471 #define RTW_CONFIG2_PAPESIGN BIT(2) /* TBD, from EEPROM */
472 #define RTW_CONFIG2_PAPETIME_MASK BITS(1,0) /* TBD, from EEPROM */
473
474 #define RTW_ANAPARM_0 0x54 /* Analog parameter, 32b */
475 #define RTW8185_ANAPARM_1 0x60
476
477 #define RTW_ANAPARM_RFPOW0_MASK BITS(30,28) /* undocumented bits
478 * which appear to
479 * control the power
480 * state of the RF
481 * components
482 */
483 #define RTW_ANAPARM_RFPOW_MASK \
484 (RTW_ANAPARM_RFPOW0_MASK|RTW_ANAPARM_RFPOW1_MASK)
485
486 #define RTW_ANAPARM_TXDACOFF BIT(27) /* 1: disable Tx DAC,
487 * 0: enable
488 */
489 #define RTW_ANAPARM_RFPOW1_MASK BITS(26,20) /* undocumented bits
490 * which appear to
491 * control the power
492 * state of the RF
493 * components
494 */
495
496 /*
497 * Maxim On/Sleep/Off control
498 */
499 #define RTW_ANAPARM_RFPOW_MAXIM_ON LSHIFT(0x8, RTW_ANAPARM_RFPOW1_MASK)
500
501 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */
502 #define RTW_ANAPARM_RFPOW_MAXIM_SLEEP LSHIFT(0x378, RTW_ANAPARM_RFPOW1_MASK)
503
504 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */
505 #define RTW_ANAPARM_RFPOW_MAXIM_OFF LSHIFT(0x379, RTW_ANAPARM_RFPOW1_MASK)
506
507 /*
508 * RFMD On/Sleep/Off control
509 */
510 #define RTW_ANAPARM_RFPOW_RFMD_ON LSHIFT(0x408, RTW_ANAPARM_RFPOW1_MASK)
511
512 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */
513 #define RTW_ANAPARM_RFPOW_RFMD_SLEEP LSHIFT(0x378, RTW_ANAPARM_RFPOW1_MASK)
514
515 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */
516 #define RTW_ANAPARM_RFPOW_RFMD_OFF LSHIFT(0x379, RTW_ANAPARM_RFPOW1_MASK)
517
518 /*
519 * Philips On/Sleep/Off control
520 */
521 #define RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON \
522 LSHIFT(0x328, RTW_ANAPARM_RFPOW1_MASK)
523 #define RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON \
524 LSHIFT(0x008, RTW_ANAPARM_RFPOW1_MASK)
525
526 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */
527 #define RTW_ANAPARM_RFPOW_PHILIPS_SLEEP\
528 LSHIFT(0x378, RTW_ANAPARM_RFPOW1_MASK)
529
530 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */
531 #define RTW_ANAPARM_RFPOW_PHILIPS_OFF\
532 LSHIFT(0x379, RTW_ANAPARM_RFPOW1_MASK)
533
534 #define RTW_ANAPARM_RFPOW_PHILIPS_ON LSHIFT(0x328, RTW_ANAPARM_RFPOW1_MASK)
535
536 #define RTW_ANAPARM_CARDSP_MASK BITS(19,0) /* undocumented
537 * card-specific
538 * bits from the
539 * EEPROM.
540 */
541
542 #define RTW_MSR 0x58 /* Media Status Register, 8b */
543 /* Network Type and Link Status */
544 #define RTW_MSR_NETYPE_MASK BITS(3,2)
545 /* AP, XXX RTL8181 only? */
546 #define RTW_MSR_NETYPE_AP_OK LSHIFT(3, RTW_MSR_NETYPE_MASK)
547 /* infrastructure link ok */
548 #define RTW_MSR_NETYPE_INFRA_OK LSHIFT(2, RTW_MSR_NETYPE_MASK)
549 /* ad-hoc link ok */
550 #define RTW_MSR_NETYPE_ADHOC_OK LSHIFT(1, RTW_MSR_NETYPE_MASK)
551 /* no link */
552 #define RTW_MSR_NETYPE_NOLINK LSHIFT(0, RTW_MSR_NETYPE_MASK)
553
554 #define RTW_CONFIG3 0x59 /* Configuration Register 3, 8b */
555 #define RTW_CONFIG3_GNTSEL BIT(7) /* Grant Select, read-only */
556 #define RTW_CONFIG3_PARMEN BIT(6) /* Set RTW_CONFIG3_PARMEN and
557 * RTW_9346CR_EEM_CONFIG to
558 * allow RTW_ANAPARM writes.
559 */
560 #define RTW_CONFIG3_MAGIC BIT(5) /* Valid when RTW_CONFIG1_PMEN is
561 * set. If set, RTL8180 wakes up
562 * OS when Magic Packet is Rx'd.
563 */
564 #define RTW_CONFIG3_CARDBEN BIT(3) /* Cardbus-related registers
565 * and functions are enabled,
566 * read-only. XXX RTL8180 only.
567 */
568 #define RTW_CONFIG3_CLKRUNEN BIT(2) /* CLKRUN enabled, read-only.
569 * XXX RTL8180 only.
570 */
571 #define RTW_CONFIG3_FUNCREGEN BIT(1) /* Function Registers Enabled,
572 * read-only. XXX RTL8180 only.
573 */
574 #define RTW_CONFIG3_FBTBEN BIT(0) /* Fast back-to-back enabled,
575 * read-only.
576 */
577 #define RTW_CONFIG4 0x5A /* Configuration Register 4, 8b */
578 #define RTW_CONFIG4_VCOPDN BIT(7) /* VCO Power Down
579 * 0: normal operation
580 * (power-on default)
581 * 1: power-down VCO, RF front-end,
582 * and most RTL8180 components.
583 */
584 #define RTW_CONFIG4_PWROFF BIT(6) /* Power Off
585 * 0: normal operation
586 * (power-on default)
587 * 1: power-down RF front-end,
588 * and most RTL8180 components,
589 * but leave VCO on.
590 *
591 * XXX RFMD front-end only?
592 */
593 #define RTW_CONFIG4_PWRMGT BIT(5) /* Power Management
594 * 0: normal operation
595 * (power-on default)
596 * 1: set Tx packet's PWRMGMT bit.
597 */
598 #define RTW_CONFIG4_LWPME BIT(4) /* LANWAKE vs. PMEB: Cardbus-only
599 * 0: LWAKE & PMEB asserted
600 * simultaneously
601 * 1: LWAKE asserted only if
602 * both PMEB is asserted and
603 * ISOLATEB is low.
604 * XXX RTL8180 only.
605 */
606 #define RTW_CONFIG4_LWPTN BIT(2) /* see RTW_CONFIG1_LWACT
607 * XXX RTL8180 only.
608 */
609 /* Radio Front-End Programming Method */
610 #define RTW_CONFIG4_RFTYPE_MASK BITS(1,0)
611 #define RTW_CONFIG4_RFTYPE_INTERSIL LSHIFT(1, RTW_CONFIG4_RFTYPE_MASK)
612 #define RTW_CONFIG4_RFTYPE_RFMD LSHIFT(2, RTW_CONFIG4_RFTYPE_MASK)
613 #define RTW_CONFIG4_RFTYPE_PHILIPS LSHIFT(3, RTW_CONFIG4_RFTYPE_MASK)
614
615 #define RTW_TESTR 0x5B /* TEST mode register, 8b */
616
617 #define RTW_PSR 0x5e /* Page Select Register, 8b */
618 #define RTW_PSR_GPO BIT(7) /* Control/status of pin 52. */
619 #define RTW_PSR_GPI BIT(6) /* Status of pin 64. */
620 #define RTW_PSR_LEDGPO1 BIT(5) /* Status/control of LED1 pin if
621 * RTW_CONFIG0_LEDGPOEN is set.
622 */
623 #define RTW_PSR_LEDGPO0 BIT(4) /* Status/control of LED0 pin if
624 * RTW_CONFIG0_LEDGPOEN is set.
625 */
626 #define RTW_PSR_UWF BIT(1) /* Enable Unicast Wakeup Frame */
627 #define RTW_PSR_PSEN BIT(0) /* 1: page 1, 0: page 0 */
628
629 #define RTW8180_SCR 0x5f /* Security Configuration Register, 8b */
630 #define RTW8180_SCR_KM_MASK BITS(5,4) /* Key Mode */
631 #define RTW8180_SCR_KM_WEP104 LSHIFT(1, RTW8180_SCR_KM_MASK)
632 #define RTW8180_SCR_KM_WEP40 LSHIFT(0, RTW8180_SCR_KM_MASK)
633 #define RTW8180_SCR_TXSECON BIT(1) /* Enable Tx WEP. Invalid if
634 * neither RTW_CONFIG0_WEP40 nor
635 * RTW_CONFIG0_WEP104 is set.
636 */
637 #define RTW8180_SCR_RXSECON BIT(0) /* Enable Rx WEP. Invalid if
638 * neither RTW_CONFIG0_WEP40 nor
639 * RTW_CONFIG0_WEP104 is set.
640 */
641
642 #define RTW8185_RFPARM 0x60 /* RF Parameter Register, 32b */
643
644 #define RTW_BCNITV 0x70 /* Beacon Interval Register, 16b */
645 #define RTW_BCNITV_BCNITV_MASK BITS(9,0) /* TU between TBTT, written
646 * by host.
647 */
648 #define RTW_ATIMWND 0x72 /* ATIM Window Register, 16b */
649 #define RTW_ATIMWND_ATIMWND BITS(9,0) /* ATIM Window length in TU,
650 * written by host.
651 */
652
653 #define RTW_BINTRITV 0x74 /* Beacon Interrupt Interval Register, 16b */
654 #define RTW_BINTRITV_BINTRITV BITS(9,0) /* RTL8180 wakes host with
655 * RTW_INTR_BCNINT at BINTRITV
656 * microseconds before TBTT
657 */
658 #define RTW_ATIMTRITV 0x76 /* ATIM Interrupt Interval Register, 16b */
659 #define RTW_ATIMTRITV_ATIMTRITV BITS(9,0) /* RTL8180 wakes host with
660 * RTW_INTR_ATIMINT at ATIMTRITV
661 * microseconds before end of
662 * ATIM Window
663 */
664
665 #define RTW_PHYDELAY 0x78 /* PHY Delay Register, 8b */
666 #define RTW_PHYDELAY_REVC_MAGIC BIT(3) /* Rev. C magic from reference
667 * driver
668 */
669 #define RTW_PHYDELAY_PHYDELAY BITS(2,0) /* microsecond Tx delay between
670 * MAC and RF front-end
671 */
672 #define RTW_CRCOUNT 0x79 /* Carrier Sense Counter, 8b */
673 #define RTW_CRCOUNT_MAGIC 0x4c
674
675 #define RTW_CRC16ERR 0x7a /* CRC16 error count, 16b, XXX RTL8181 only? */
676
677 #define RTW_BB 0x7c /* Baseband interface, 32b */
678 /* used for writing RTL8180's integrated baseband processor */
679 #define RTW_BB_RD_MASK BITS(23,16) /* data to read */
680 #define RTW_BB_WR_MASK BITS(15,8) /* data to write */
681 #define RTW_BB_WREN BIT(7) /* write enable */
682 #define RTW_BB_ADDR_MASK BITS(6,0) /* address */
683
684 #define RTW_PHYADDR 0x7c /* Address register for PHY interface, 8b */
685 #define RTW_PHYDATAW 0x7d /* Write data to PHY, 8b, write-only */
686 #define RTW_PHYDATAR 0x7e /* Read data from PHY, 8b (?), read-only */
687
688 #define RTW8180_PHYCFG 0x80 /* PHY Configuration Register, 32b */
689 #define RTW8180_PHYCFG_MAC_POLL BIT(31) /* if !RTW8180_PHYCFG_HST,
690 * host sets. MAC clears
691 * after banging bits.
692 */
693 #define RTW8180_PHYCFG_HST BIT(30) /* 1: host bangs bits
694 * 0: MAC bangs bits
695 */
696 #define RTW8180_PHYCFG_MAC_RFTYPE_MASK BITS(29,28)
697 #define RTW8180_PHYCFG_MAC_RFTYPE_INTERSIL \
698 LSHIFT(0, RTW8180_PHYCFG_MAC_RFTYPE_MASK)
699 #define RTW8180_PHYCFG_MAC_RFTYPE_RFMD \
700 LSHIFT(1, RTW8180_PHYCFG_MAC_RFTYPE_MASK)
701 #define RTW8180_PHYCFG_MAC_RFTYPE_GCT \
702 RTW8180_PHYCFG_MAC_RFTYPE_RFMD
703 #define RTW8180_PHYCFG_MAC_RFTYPE_PHILIPS \
704 LSHIFT(3, RTW8180_PHYCFG_MAC_RFTYPE_MASK)
705 #define RTW8180_PHYCFG_MAC_PHILIPS_ADDR_MASK BITS(27,24)
706 #define RTW8180_PHYCFG_MAC_PHILIPS_DATA_MASK BITS(23,0)
707 #define RTW8180_PHYCFG_MAC_MAXIM_LODATA_MASK BITS(27,24)
708 #define RTW8180_PHYCFG_MAC_MAXIM_ADDR_MASK BITS(11,8)
709 #define RTW8180_PHYCFG_MAC_MAXIM_HIDATA_MASK BITS(7,0)
710 #define RTW8180_PHYCFG_HST_EN BIT(2)
711 #define RTW8180_PHYCFG_HST_CLK BIT(1)
712 #define RTW8180_PHYCFG_HST_DATA BIT(0)
713
714 #define RTW8185_RFPINSOUTPUT 0x80
715 #define RTW8185_RFPINSOUTPUT_MASK 0xfff3
716
717 #define RTW8185_RFPINSENABLE 0x82
718 #define RTW8185_RFPINSENABLE_ENABLE 0x0007
719
720 #define RTW8185_INSSELECT 0x84
721 #define RTW8185_SW_GPIO 0x400
722
723 #define RTW_MAXIM_HIDATA_MASK BITS(11,4)
724 #define RTW_MAXIM_LODATA_MASK BITS(3,0)
725
726 /**
727 ** 0x84 - 0xD3, page 1, selected when RTW_PSR[PSEN] == 1.
728 **/
729
730 #define RTW_WAKEUP0L 0x84 /* Power Management Wakeup Frame */
731 #define RTW_WAKEUP0H 0x88 /* 32b */
732
733 #define RTW_WAKEUP1L 0x8c
734 #define RTW_WAKEUP1H 0x90
735
736 #define RTW_WAKEUP2LL 0x94
737 #define RTW_WAKEUP2LH 0x98
738
739 #define RTW_WAKEUP2HL 0x9c
740 #define RTW_WAKEUP2HH 0xa0
741
742 #define RTW_WAKEUP3LL 0xa4
743 #define RTW_WAKEUP3LH 0xa8
744
745 #define RTW_WAKEUP3HL 0xac
746 #define RTW_WAKEUP3HH 0xb0
747
748 #define RTW_WAKEUP4LL 0xb4
749 #define RTW_WAKEUP4LH 0xb8
750
751 #define RTW_WAKEUP4HL 0xbc
752 #define RTW_WAKEUP4HH 0xc0
753
754 #define RTW_CRC0 0xc4 /* CRC of wakeup frame 0, 16b */
755 #define RTW_CRC1 0xc6 /* CRC of wakeup frame 1, 16b */
756 #define RTW_CRC2 0xc8 /* CRC of wakeup frame 2, 16b */
757 #define RTW_CRC3 0xca /* CRC of wakeup frame 3, 16b */
758 #define RTW_CRC4 0xcc /* CRC of wakeup frame 4, 16b */
759
760 /**
761 ** 0x84 - 0xD3, page 0, selected when RTW_PSR[PSEN] == 0.
762 **/
763
764 /* Default Key Registers, each 128b
765 *
766 * If RTW8180_SCR_KM_WEP104, 104 lsb are the key.
767 * If RTW8180_SCR_KM_WEP40, 40 lsb are the key.
768 */
769 #define RTW8180_DK0 0x90 /* Default Key 0 Register, 128b */
770 #define RTW8180_DK1 0xa0 /* Default Key 1 Register, 128b */
771 #define RTW8180_DK2 0xb0 /* Default Key 2 Register, 128b */
772 #define RTW8180_DK3 0xc0 /* Default Key 3 Register, 128b */
773
774 #define RTW8185_RFPINSSELECT 0x84
775 #define RTW8185_RFPINSSELECT_ENABLE 0x0007
776
777 #define RTW8185_RFPINSINPUT 0x86
778 #define RTW8185_RFPARA 0x88
779 #define RTW8185_RFTIMING 0x8c
780 #define RTW8185_GPO 0x90
781 #define RTW8185_GPE 0x91
782 #define RTW8185_GPI 0x92
783 #define RTW8185_TXAGCCTL 0x9c
784 #define RTW8185_CCKTXAGC 0x9d
785 #define RTW8185_OFDMTXAGC 0x9e
786 #define RTW8185_ANTSEL 0x9f
787
788 #define RTW8185_CAMRW 0xa0 /* CAM R/W Register, 32b */
789 #define RTW8185_CAMRW_POOLING BIT(31) /* Pooling bit */
790 #define RTW8185_CAMRW_WRITE BIT(16) /* Write enable */
791 #define RTW8185_CAMRW_ADDRESS BITS(6, 0) /* CAM address */
792
793 #define RTW8185_CAMOUTPUT 0xa4
794 #define RTW8185_CAMINPUT 0xa8
795
796 #define RTW8185_CAMDEBUG 0xac /* CAM Debug Interface, 32b */
797 #define RTW8185_CAMDEBUG_SELTXRXINFO BIT(31)
798 #define RTW8185_CAMDEBUG_KEYFOUND BIT(30)
799 #define RTW8185_CAMDEBUG_WPACONFIG BITS(29, 24)
800 #define RTW8185_CAMDEBUG_CAMKEY BITS(23, 0)
801
802 #define RTW8185_WPACONFIG 0xb0 /* WPA Config Register, 16b */
803 #define RTW8185_WPACONFIG_RXWPADUMMY BIT(8)
804 #define RTW8185_WPACONFIG_DISRX_AESMIC BIT(3)
805 #define RTW8185_WPACONFIG_RXDECRYPT BIT(2)
806 #define RTW8185_WPACONFIG_TXENCRYPT BIT(1)
807 #define RTW8185_WPACONFIG_USEDEFAULTKEY BIT(0)
808
809 #define RTW8185_AESMASK 0xb2
810 #define RTW8185_SIFS 0xb4
811 #define RTW8185_DIFS 0xb5
812 #define RTW8185_SLOTTIME 0xb6
813 #define RTW8185_UTUNE 0xb7
814
815 #define RTW8185_CWCONFIG 0xbc /* CW Config Register, 8b */
816 #define RTW8185_CWCONFIG_PPRETRYLIMIT BIT(1) /* Per-Packet Retry Limit */
817 #define RTW8185_CWCONFIG_PPCW BIT(1) /* Per-Packet Cont. Window */
818
819 #define RTW8185_CWVALUES 0xbd /* CW Values, 8b */
820 #define RTW8185_CWVALUES_CWMAX BITS(7, 4) /* Max Contention Window */
821 #define RTW8185_CWVALUES_CWMIN BITS(3, 0) /* Min Contention Window */
822
823 #define RTW8185_RATEFALLBACKCTL 0xbe /* Auto Rate Fallback, 8b */
824 #define RTW8185_RATEFALLBACKCTL_ENABLE BIT(7)
825 #define RTW8185_RATEFALLBACKCTL_STEP BITS(1, 0)
826
827 #define RTW_CONFIG5 0xd8 /* Configuration Register 5, 8b */
828 #define RTW_CONFIG5_TXFIFOOK BIT(7) /* Tx FIFO self-test pass, read-only */
829 #define RTW_CONFIG5_RXFIFOOK BIT(6) /* Rx FIFO self-test pass, read-only */
830 #define RTW_CONFIG5_CALON BIT(5) /* 1: start calibration cycle
831 * and raise AGCRESET pin.
832 * 0: lower AGCRESET pin
833 */
834 #define RTW_CONFIG5_EACPI BIT(2) /* Enable ACPI Wake up, default 0 */
835 #define RTW_CONFIG5_LANWAKE BIT(1) /* Enable LAN Wake signal,
836 * from EEPROM
837 */
838 #define RTW_CONFIG5_PMESTS BIT(0) /* 1: both software & PCI Reset
839 * reset PME_Status
840 * 0: only software resets PME_Status
841 *
842 * From EEPROM.
843 */
844
845 #define RTW_TPPOLL 0xd9 /* Transmit Priority Polling Register, 8b,
846 * write-only.
847 */
848 #define RTW_TPPOLL_BQ BIT(7) /* RTL8180 clears to notify host of a beacon
849 * Tx. Host writes have no effect.
850 */
851 #define RTW_TPPOLL_HPQ BIT(6) /* Host writes 1 to notify RTL8180 of
852 * high-priority Tx packets, RTL8180 clears
853 * to after high-priority Tx is complete.
854 */
855 #define RTW_TPPOLL_NPQ BIT(5) /* If RTW_CONFIG2_DPS is set,
856 * host writes 1 to notify RTL8180 of
857 * normal-priority Tx packets, RTL8180 clears
858 * after normal-priority Tx is complete.
859 *
860 * If RTW_CONFIG2_DPS is clear, host writes
861 * have no effect. RTL8180 clears after
862 * normal-priority Tx is complete.
863 */
864 #define RTW_TPPOLL_LPQ BIT(4) /* Host writes 1 to notify RTL8180 of
865 * low-priority Tx packets, RTL8180 clears
866 * after low-priority Tx is complete.
867 */
868 #define RTW_TPPOLL_SBQ BIT(3) /* Host writes 1 to tell RTL8180 to
869 * stop beacon DMA. This bit is invalid
870 * when RTW_CONFIG2_DPS is set.
871 */
872 #define RTW_TPPOLL_SHPQ BIT(2) /* Host writes 1 to tell RTL8180 to
873 * stop high-priority DMA.
874 */
875 #define RTW_TPPOLL_SNPQ BIT(1) /* Host writes 1 to tell RTL8180 to
876 * stop normal-priority DMA. This bit is invalid
877 * when RTW_CONFIG2_DPS is set.
878 */
879 #define RTW_TPPOLL_SLPQ BIT(0) /* Host writes 1 to tell RTL8180 to
880 * stop low-priority DMA.
881 */
882
883 /* Start all queues. */
884 #define RTW_TPPOLL_ALL (RTW_TPPOLL_BQ | RTW_TPPOLL_HPQ | \
885 RTW_TPPOLL_NPQ | RTW_TPPOLL_LPQ)
886 /* Check all queues' activity. */
887 #define RTW_TPPOLL_ACTIVE RTW_TPPOLL_ALL
888 /* Stop all queues. */
889 #define RTW_TPPOLL_SALL (RTW_TPPOLL_SBQ | RTW_TPPOLL_SHPQ | \
890 RTW_TPPOLL_SNPQ | RTW_TPPOLL_SLPQ)
891
892 #define RTW_CWR 0xdc /* Contention Window Register, 16b, read-only */
893 /* Contention Window: indicates number of contention windows before Tx
894 */
895 #define RTW_CWR_CW BITS(9,0)
896
897 /* Retry Count Register, 16b, read-only */
898 #define RTW_RETRYCTR 0xde
899 /* Retry Count: indicates number of retries after Tx */
900 #define RTW_RETRYCTR_RETRYCT BITS(7,0)
901
902 #define RTW_RDSAR 0xe4 /* Receive descriptor Start Address Register,
903 * 32b, 256-byte alignment.
904 */
905 /* Function Event Register, 32b, Cardbus only. Only valid when
906 * both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN are set.
907 */
908 #define RTW_FER 0xf0
909 #define RTW_FER_INTR BIT(15) /* set when RTW_FFER_INTR is set */
910 #define RTW_FER_GWAKE BIT(4) /* General Wakeup */
911 /* Function Event Mask Register, 32b, Cardbus only. Only valid when
912 * both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN are set.
913 */
914 #define RTW_FEMR 0xf4
915 #define RTW_FEMR_INTR BIT(15) /* set when RTW_FFER_INTR is set */
916 #define RTW_FEMR_WKUP BIT(14) /* Wakeup Mask */
917 #define RTW_FEMR_GWAKE BIT(4) /* General Wakeup */
918 /* Function Present State Register, 32b, read-only, Cardbus only.
919 * Only valid when both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN
920 * are set.
921 */
922 #define RTW_FPSR 0xf8
923 #define RTW_FPSR_INTR BIT(15) /* TBD */
924 #define RTW_FPSR_GWAKE BIT(4) /* General Wakeup: TBD */
925 /* Function Force Event Register, 32b, write-only, Cardbus only.
926 * Only valid when both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN
927 * are set.
928 */
929 #define RTW_FFER 0xfc
930 #define RTW_FFER_INTR BIT(15) /* TBD */
931 #define RTW_FFER_GWAKE BIT(4) /* General Wakeup: TBD */
932
933 /* Serial EEPROM offsets */
934 #define RTW_SR_ID 0x00 /* 16b */
935 #define RTW_SR_VID 0x02 /* 16b */
936 #define RTW_SR_DID 0x04 /* 16b */
937 #define RTW_SR_SVID 0x06 /* 16b */
938 #define RTW_SR_SMID 0x08 /* 16b */
939 #define RTW_SR_MNGNT 0x0a
940 #define RTW_SR_MXLAT 0x0b
941 #define RTW_SR_RFCHIPID 0x0c
942 #define RTW_SR_CONFIG3 0x0d
943 #define RTW_SR_MAC 0x0e /* 6 bytes */
944 #define RTW_SR_CONFIG0 0x14
945 #define RTW_SR_CONFIG1 0x15
946 #define RTW_SR_PMC 0x16 /* Power Management Capabilities, 16b */
947 #define RTW_SR_CONFIG2 0x18
948 #define RTW_SR_CONFIG4 0x19
949 #define RTW_SR_ANAPARM 0x1a /* Analog Parameters, 32b */
950 #define RTW_SR_TESTR 0x1e
951 #define RTW_SR_CONFIG5 0x1f
952 #define RTW_SR_TXPOWER1 0x20
953 #define RTW_SR_TXPOWER2 0x21
954 #define RTW_SR_TXPOWER3 0x22
955 #define RTW_SR_TXPOWER4 0x23
956 #define RTW_SR_TXPOWER5 0x24
957 #define RTW_SR_TXPOWER6 0x25
958 #define RTW_SR_TXPOWER7 0x26
959 #define RTW_SR_TXPOWER8 0x27
960 #define RTW_SR_TXPOWER9 0x28
961 #define RTW_SR_TXPOWER10 0x29
962 #define RTW_SR_TXPOWER11 0x2a
963 #define RTW_SR_TXPOWER12 0x2b
964 #define RTW_SR_TXPOWER13 0x2c
965 #define RTW_SR_TXPOWER14 0x2d
966 #define RTW_SR_CHANNELPLAN 0x2e /* bitmap of channels to scan */
967 #define RTW_SR_ENERGYDETTHR 0x2f /* energy-detect threshold */
968 #define RTW_SR_ENERGYDETTHR_DEFAULT 0x0c /* use this if old SROM */
969 #define RTW_SR_CISPOINTER 0x30 /* 16b */
970 #define RTW_SR_RFPARM 0x32 /* RF-specific parameter */
971 #define RTW_SR_RFPARM_DIGPHY BIT(0) /* 1: digital PHY */
972 #define RTW_SR_RFPARM_DFLANTB BIT(1) /* 1: antenna B is default */
973 #define RTW_SR_RFPARM_CS_MASK BITS(2,3) /* carrier-sense type */
974 #define RTW_SR_VERSION 0x3c /* EEPROM content version, 16b */
975 #define RTW_SR_CRC 0x3e /* EEPROM content CRC, 16b */
976 #define RTW_SR_VPD 0x40 /* Vital Product Data, 64 bytes */
977 #define RTW_SR_CIS 0x80 /* CIS Data, 93c56 only, 128 bytes*/
978
979 /*
980 * RTL8180 Transmit/Receive Descriptors
981 */
982
983 /* the first descriptor in each ring must be on a 256-byte boundary */
984 #define RTW_DESC_ALIGNMENT 256
985
986 /* Tx descriptor */
987 struct rtw_txdesc {
988 u_int32_t td_ctl0;
989 u_int32_t td_ctl1;
990 u_int32_t td_buf;
991 u_int32_t td_len;
992 u_int32_t td_next;
993 u_int32_t td_rsvd[3];
994 };
995
996 #define td_stat td_ctl0
997
998 #define RTW_TXCTL0_OWN BIT(31) /* 1: ready to Tx */
999 #define RTW_TXCTL0_RSVD0 BIT(30) /* reserved */
1000 #define RTW_TXCTL0_FS BIT(29) /* first segment */
1001 #define RTW_TXCTL0_LS BIT(28) /* last segment */
1002
1003 #define RTW_TXCTL0_RATE_MASK BITS(27,24) /* Tx rate */
1004 #define RTW_TXCTL0_RATE_1MBPS LSHIFT(0, RTW_TXCTL0_RATE_MASK)
1005 #define RTW_TXCTL0_RATE_2MBPS LSHIFT(1, RTW_TXCTL0_RATE_MASK)
1006 #define RTW_TXCTL0_RATE_5MBPS LSHIFT(2, RTW_TXCTL0_RATE_MASK)
1007 #define RTW_TXCTL0_RATE_11MBPS LSHIFT(3, RTW_TXCTL0_RATE_MASK)
1008
1009 #define RTW_TXCTL0_RTSEN BIT(23) /* RTS Enable */
1010
1011 #define RTW_TXCTL0_RTSRATE_MASK BITS(22,19) /* Tx rate */
1012 #define RTW_TXCTL0_RTSRATE_1MBPS LSHIFT(0, RTW_TXCTL0_RTSRATE_MASK)
1013 #define RTW_TXCTL0_RTSRATE_2MBPS LSHIFT(1, RTW_TXCTL0_RTSRATE_MASK)
1014 #define RTW_TXCTL0_RTSRATE_5MBPS LSHIFT(2, RTW_TXCTL0_RTSRATE_MASK)
1015 #define RTW_TXCTL0_RTSRATE_11MBPS LSHIFT(3, RTW_TXCTL0_RTSRATE_MASK)
1016
1017 #define RTW_TXCTL0_BEACON BIT(18) /* packet is a beacon */
1018 #define RTW_TXCTL0_MOREFRAG BIT(17) /* another fragment follows */
1019 #define RTW_TXCTL0_SPLCP BIT(16) /* add short PLCP preamble
1020 * and header
1021 */
1022 #define RTW_TXCTL0_KEYID_MASK BITS(15,14) /* default key id */
1023 #define RTW_TXCTL0_RSVD1_MASK BITS(13,12) /* reserved */
1024 #define RTW_TXCTL0_TPKTSIZE_MASK BITS(11,0) /* Tx packet size
1025 * in bytes
1026 */
1027
1028 #define RTW_TXSTAT_OWN RTW_TXCTL0_OWN
1029 #define RTW_TXSTAT_RSVD0 RTW_TXCTL0_RSVD0
1030 #define RTW_TXSTAT_FS RTW_TXCTL0_FS
1031 #define RTW_TXSTAT_LS RTW_TXCTL0_LS
1032 #define RTW_TXSTAT_RSVD1_MASK BITS(27,16)
1033 #define RTW_TXSTAT_TOK BIT(15)
1034 #define RTW_TXSTAT_RTSRETRY_MASK BITS(14,8) /* RTS retry count */
1035 #define RTW_TXSTAT_DRC_MASK BITS(7,0) /* Data retry count */
1036
1037 #define RTW_TXCTL1_LENGEXT BIT(31) /* supplements _LENGTH
1038 * in packets sent 5.5Mb/s or
1039 * faster
1040 */
1041 #define RTW_TXCTL1_LENGTH_MASK BITS(30,16) /* PLCP length (microseconds) */
1042 #define RTW_TXCTL1_RTSDUR_MASK BITS(15,0) /* RTS Duration
1043 * (microseconds)
1044 */
1045
1046 #define RTW_TXLEN_LENGTH_MASK BITS(11,0) /* Tx buffer length in bytes */
1047
1048 /* Rx descriptor */
1049 struct rtw_rxdesc {
1050 u_int32_t rd_ctl;
1051 u_int32_t rd_rsvd0;
1052 u_int32_t rd_buf;
1053 u_int32_t rd_rsvd1;
1054 };
1055
1056 #define rd_stat rd_ctl
1057 #define rd_rssi rd_rsvd0
1058 #define rd_tsftl rd_buf /* valid only when RTW_RXSTAT_LS is set */
1059 #define rd_tsfth rd_rsvd1 /* valid only when RTW_RXSTAT_LS is set */
1060
1061 #define RTW_RXCTL_OWN BIT(31) /* 1: owned by NIC */
1062 #define RTW_RXCTL_EOR BIT(30) /* end of ring */
1063 #define RTW_RXCTL_FS BIT(29) /* first segment */
1064 #define RTW_RXCTL_LS BIT(28) /* last segment */
1065 #define RTW_RXCTL_RSVD0_MASK BITS(29,12) /* reserved */
1066 #define RTW_RXCTL_LENGTH_MASK BITS(11,0) /* Rx buffer length */
1067
1068 #define RTW_RXSTAT_OWN RTW_RXCTL_OWN
1069 #define RTW_RXSTAT_EOR RTW_RXCTL_EOR
1070 #define RTW_RXSTAT_FS RTW_RXCTL_FS /* first segment */
1071 #define RTW_RXSTAT_LS RTW_RXCTL_LS /* last segment */
1072 #define RTW_RXSTAT_DMAFAIL BIT(27) /* DMA failure on this pkt */
1073 #define RTW_RXSTAT_BOVF BIT(26) /* buffer overflow XXX means
1074 * FIFO exhausted?
1075 */
1076 #define RTW_RXSTAT_SPLCP BIT(25) /* Rx'd with short preamble
1077 * and PLCP header
1078 */
1079 #define RTW_RXSTAT_RSVD1 BIT(24) /* reserved */
1080 #define RTW_RXSTAT_RATE_MASK BITS(23,20) /* Rx rate */
1081 #define RTW_RXSTAT_RATE_1MBPS LSHIFT(0, RTW_RXSTAT_RATE_MASK)
1082 #define RTW_RXSTAT_RATE_2MBPS LSHIFT(1, RTW_RXSTAT_RATE_MASK)
1083 #define RTW_RXSTAT_RATE_5MBPS LSHIFT(2, RTW_RXSTAT_RATE_MASK)
1084 #define RTW_RXSTAT_RATE_11MBPS LSHIFT(3, RTW_RXSTAT_RATE_MASK)
1085 #define RTW_RXSTAT_MIC BIT(19) /* XXX from reference driver */
1086 #define RTW_RXSTAT_MAR BIT(18) /* is multicast */
1087 #define RTW_RXSTAT_PAR BIT(17) /* matches RTL8180's MAC */
1088 #define RTW_RXSTAT_BAR BIT(16) /* is broadcast */
1089 #define RTW_RXSTAT_RES BIT(15) /* error summary. valid when
1090 * RTW_RXSTAT_LS set. indicates
1091 * that either RTW_RXSTAT_CRC32
1092 * or RTW_RXSTAT_ICV is set.
1093 */
1094 #define RTW_RXSTAT_PWRMGT BIT(14) /* 802.11 PWRMGMT bit is set */
1095 #define RTW_RXSTAT_CRC16 BIT(14) /* XXX CRC16 error, from
1096 * reference driver
1097 */
1098 #define RTW_RXSTAT_CRC32 BIT(13) /* CRC32 error */
1099 #define RTW_RXSTAT_ICV BIT(12) /* ICV error */
1100 #define RTW_RXSTAT_LENGTH_MASK BITS(11,0) /* frame length, including
1101 * CRC32
1102 */
1103
1104 /* Convenient status conjunction. */
1105 #define RTW_RXSTAT_ONESEG (RTW_RXSTAT_FS|RTW_RXSTAT_LS)
1106 /* Convenient status disjunctions. */
1107 #define RTW_RXSTAT_IOERROR (RTW_RXSTAT_DMAFAIL|RTW_RXSTAT_BOVF)
1108 #define RTW_RXSTAT_DEBUG (RTW_RXSTAT_SPLCP|RTW_RXSTAT_MAR|\
1109 RTW_RXSTAT_PAR|RTW_RXSTAT_BAR|\
1110 RTW_RXSTAT_PWRMGT|RTW_RXSTAT_CRC32|\
1111 RTW_RXSTAT_ICV)
1112
1113
1114 #define RTW_RXRSSI_VLAN BITS(32,16) /* XXX from reference driver */
1115 /* for Philips RF front-ends */
1116 #define RTW_RXRSSI_RSSI BITS(15,8) /* RF energy at the PHY */
1117 /* for RF front-ends by Intersil, Maxim, RFMD */
1118 #define RTW_RXRSSI_IMR_RSSI BITS(15,9) /* RF energy at the PHY */
1119 #define RTW_RXRSSI_IMR_LNA BIT(8) /* 1: LNA activated */
1120 #define RTW_RXRSSI_SQ BITS(7,0) /* Barker code-lock quality */
1121
1122 #define RTW_READ8(regs, ofs) \
1123 ((*(regs)->r_read8)(regs, ofs))
1124
1125 #define RTW_READ16(regs, ofs) \
1126 ((*(regs)->r_read16)(regs, ofs))
1127
1128 #define RTW_READ(regs, ofs) \
1129 ((*(regs)->r_read32)(regs, ofs))
1130
1131 #define RTW_WRITE8(regs, ofs, val) \
1132 ((*(regs)->r_write8)(regs, ofs, val))
1133
1134 #define RTW_WRITE16(regs, ofs, val) \
1135 ((*(regs)->r_write16)(regs, ofs, val))
1136
1137 #define RTW_WRITE(regs, ofs, val) \
1138 ((*(regs)->r_write32)(regs, ofs, val))
1139
1140 #define RTW_ISSET(regs, reg, mask) \
1141 (RTW_READ((regs), (reg)) & (mask))
1142
1143 #define RTW_CLR(regs, reg, mask) \
1144 RTW_WRITE((regs), (reg), RTW_READ((regs), (reg)) & ~(mask))
1145
1146 /* bus_space(9) lied? */
1147 #ifndef BUS_SPACE_BARRIER_SYNC
1148 #define BUS_SPACE_BARRIER_SYNC (BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
1149 #endif
1150
1151 #ifndef BUS_SPACE_BARRIER_READ_BEFORE_READ
1152 #define BUS_SPACE_BARRIER_READ_BEFORE_READ BUS_SPACE_BARRIER_READ
1153 #endif
1154
1155 #ifndef BUS_SPACE_BARRIER_READ_BEFORE_WRITE
1156 #define BUS_SPACE_BARRIER_READ_BEFORE_WRITE BUS_SPACE_BARRIER_READ
1157 #endif
1158
1159 #ifndef BUS_SPACE_BARRIER_WRITE_BEFORE_READ
1160 #define BUS_SPACE_BARRIER_WRITE_BEFORE_READ BUS_SPACE_BARRIER_WRITE
1161 #endif
1162
1163 #ifndef BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE
1164 #define BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE BUS_SPACE_BARRIER_WRITE
1165 #endif
1166
1167 /*
1168 * Bus barrier
1169 *
1170 * Complete outstanding read and/or write ops on [reg0, reg1]
1171 * ([reg1, reg0]) before starting new ops on the same region. See
1172 * acceptable bus_space_barrier(9) for the flag definitions.
1173 */
1174 #define RTW_BARRIER(regs, reg0, reg1, flags) \
1175 ((*(regs)->r_barrier)(regs, reg0, reg1, flags))
1176
1177 /*
1178 * Barrier convenience macros.
1179 */
1180 /* sync */
1181 #define RTW_SYNC(regs, reg0, reg1) \
1182 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_SYNC)
1183
1184 /* write-before-write */
1185 #define RTW_WBW(regs, reg0, reg1) \
1186 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE)
1187
1188 /* write-before-read */
1189 #define RTW_WBR(regs, reg0, reg1) \
1190 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_READ)
1191
1192 /* read-before-read */
1193 #define RTW_RBR(regs, reg0, reg1) \
1194 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_READ)
1195
1196 /* read-before-read */
1197 #define RTW_RBW(regs, reg0, reg1) \
1198 RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_WRITE)
1199
1200 #define RTW_WBRW(regs, reg0, reg1) \
1201 RTW_BARRIER(regs, reg0, reg1, \
1202 BUS_SPACE_BARRIER_WRITE_BEFORE_READ | \
1203 BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE)
1204
1205 /*
1206 * Registers for RTL8180L's built-in baseband modem.
1207 */
1208 #define RTW_BBP_SYS1 0x00
1209 #define RTW_BBP_TXAGC 0x03 /* guess: transmit auto gain control */
1210 #define RTW_BBP_LNADET 0x04 /* guess: low-noise amplifier activation
1211 * threshold
1212 */
1213 #define RTW_BBP_IFAGCINI 0x05 /* guess: intermediate frequency (IF)
1214 * auto-gain control (AGC) initial value
1215 */
1216 #define RTW_BBP_IFAGCLIMIT 0x06 /* guess: IF AGC maximum value */
1217 #define RTW_BBP_IFAGCDET 0x07 /* guess: activation threshold for
1218 * IF AGC loop
1219 */
1220
1221 #define RTW_BBP_ANTATTEN 0x10 /* guess: antenna & attenuation */
1222 #define RTW_BBP_ANTATTEN_PHILIPS_MAGIC 0x91
1223 #define RTW_BBP_ANTATTEN_INTERSIL_MAGIC 0x92
1224 #define RTW_BBP_ANTATTEN_RFMD_MAGIC 0x93
1225 #define RTW_BBP_ANTATTEN_GCT_MAGIC 0xa3
1226 #define RTW_BBP_ANTATTEN_MAXIM_MAGIC 0xb3
1227 #define RTW_BBP_ANTATTEN_DFLANTB 0x40
1228 #define RTW_BBP_ANTATTEN_CHAN14 0x0c
1229
1230 #define RTW_BBP_TRL 0x11 /* guess: transmit/receive
1231 * switch latency
1232 */
1233 #define RTW_BBP_SYS2 0x12
1234 #define RTW_BBP_SYS2_ANTDIV 0x80 /* enable antenna diversity */
1235 #define RTW_BBP_SYS2_RATE_MASK BITS(5,4) /* loopback rate?
1236 * 0: 1Mbps
1237 * 1: 2Mbps
1238 * 2: 5.5Mbps
1239 * 3: 11Mbps
1240 */
1241 #define RTW_BBP_SYS3 0x13
1242 /* carrier-sense threshold */
1243 #define RTW_BBP_SYS3_CSTHRESH_MASK BITS(0,3)
1244 #define RTW_BBP_CHESTLIM 0x19 /* guess: channel energy-detect
1245 * threshold
1246 */
1247 #define RTW_BBP_CHSQLIM 0x1a /* guess: channel signal-quality
1248 * threshold
1249 */