BIT 1991 dev/ic/atw.c for (mask = BIT(nbits - 1); mask != 0; mask >>= 1) {
BIT 59 dev/ic/atwreg.h #define BITS(m, n) ((BIT(MAX((m), (n)) + 1) - 1) ^ (BIT(MIN((m), (n))) - 1))
BIT 185 dev/ic/atwreg.h #define ATW_PAR_MWIE BIT(24) /* memory write and invalidate
BIT 188 dev/ic/atwreg.h #define ATW_PAR_MRLE BIT(23) /* memory read line enable */
BIT 189 dev/ic/atwreg.h #define ATW_PAR_MRME BIT(21) /* memory read multiple
BIT 211 dev/ic/atwreg.h #define ATW_PAR_BLE BIT(7) /* big/little endian selection */
BIT 213 dev/ic/atwreg.h #define ATW_PAR_BAR BIT(1) /* bus arbitration */
BIT 214 dev/ic/atwreg.h #define ATW_PAR_SWR BIT(0) /* software reset */
BIT 216 dev/ic/atwreg.h #define ATW_FRCTL_PWRMGMT BIT(31) /* power management */
BIT 218 dev/ic/atwreg.h #define ATW_FRCTL_ORDER BIT(28) /* order bit */
BIT 219 dev/ic/atwreg.h #define ATW_FRCTL_MAXPSP BIT(27) /* maximum power saving */
BIT 220 dev/ic/atwreg.h #define ATW_C_FRCTL_PRSP BIT(26) /* 1: driver sends probe
BIT 224 dev/ic/atwreg.h #define ATW_C_FRCTL_DRVBCON BIT(25) /* 1: driver sends beacons
BIT 227 dev/ic/atwreg.h #define ATW_C_FRCTL_DRVLINKCTRL BIT(24) /* 1: driver controls link LED
BIT 230 dev/ic/atwreg.h #define ATW_C_FRCTL_DRVLINKON BIT(23) /* 1: turn on link LED
BIT 233 dev/ic/atwreg.h #define ATW_C_FRCTL_CTX_DATA BIT(22) /* 0: set by CSR28
BIT 236 dev/ic/atwreg.h #define ATW_C_FRCTL_RSVFRM BIT(21) /* 1: receive "reserved"
BIT 240 dev/ic/atwreg.h #define ATW_C_FRCTL_CFEND BIT(19) /* write to send CF_END,
BIT 243 dev/ic/atwreg.h #define ATW_FRCTL_DOZEFRM BIT(18) /* select pre-sleep frame */
BIT 244 dev/ic/atwreg.h #define ATW_FRCTL_PSAWAKE BIT(17) /* MAC is awake (?) */
BIT 245 dev/ic/atwreg.h #define ATW_FRCTL_PSMODE BIT(16) /* MAC is power-saving (?) */
BIT 248 dev/ic/atwreg.h #define ATW_INTR_PCF BIT(31) /* started/ended CFP */
BIT 249 dev/ic/atwreg.h #define ATW_INTR_BCNTC BIT(30) /* transmitted IBSS beacon */
BIT 250 dev/ic/atwreg.h #define ATW_INTR_GPINT BIT(29) /* GPIO interrupt */
BIT 251 dev/ic/atwreg.h #define ATW_INTR_LINKOFF BIT(28) /* lost ATW_WCSR_BLN beacons */
BIT 252 dev/ic/atwreg.h #define ATW_INTR_ATIMTC BIT(27) /* transmitted ATIM */
BIT 253 dev/ic/atwreg.h #define ATW_INTR_TSFTF BIT(26) /* TSFT out of range */
BIT 254 dev/ic/atwreg.h #define ATW_INTR_TSCZ BIT(25) /* TSC countdown expired */
BIT 255 dev/ic/atwreg.h #define ATW_INTR_LINKON BIT(24) /* matched SSID, BSSID */
BIT 256 dev/ic/atwreg.h #define ATW_INTR_SQL BIT(23) /* Marvel signal quality */
BIT 257 dev/ic/atwreg.h #define ATW_INTR_WEPTD BIT(22) /* switched WEP table */
BIT 258 dev/ic/atwreg.h #define ATW_INTR_ATIME BIT(21) /* ended ATIM window */
BIT 259 dev/ic/atwreg.h #define ATW_INTR_TBTT BIT(20) /* (TBTT) Target Beacon TX Time
BIT 262 dev/ic/atwreg.h #define ATW_INTR_NISS BIT(16) /* normal interrupt status
BIT 266 dev/ic/atwreg.h #define ATW_INTR_AISS BIT(15) /* abnormal interrupt status
BIT 271 dev/ic/atwreg.h #define ATW_INTR_TEIS BIT(14) /* transmit early interrupt
BIT 275 dev/ic/atwreg.h #define ATW_INTR_FBE BIT(13) /* fatal bus error */
BIT 276 dev/ic/atwreg.h #define ATW_INTR_REIS BIT(12) /* receive early interrupt
BIT 280 dev/ic/atwreg.h #define ATW_INTR_GPTT BIT(11) /* general purpose timer expired */
BIT 281 dev/ic/atwreg.h #define ATW_INTR_RPS BIT(8) /* stopped receive process */
BIT 282 dev/ic/atwreg.h #define ATW_INTR_RDU BIT(7) /* receive descriptor
BIT 285 dev/ic/atwreg.h #define ATW_INTR_RCI BIT(6) /* completed packet reception */
BIT 286 dev/ic/atwreg.h #define ATW_INTR_TUF BIT(5) /* transmit underflow */
BIT 287 dev/ic/atwreg.h #define ATW_INTR_TRT BIT(4) /* transmit retry count
BIT 290 dev/ic/atwreg.h #define ATW_INTR_TLT BIT(3) /* transmit lifetime exceeded */
BIT 291 dev/ic/atwreg.h #define ATW_INTR_TDU BIT(2) /* transmit descriptor
BIT 294 dev/ic/atwreg.h #define ATW_INTR_TPS BIT(1) /* stopped transmit process */
BIT 295 dev/ic/atwreg.h #define ATW_INTR_TCI BIT(0) /* completed transmit */
BIT 296 dev/ic/atwreg.h #define ATW_NAR_TXCF BIT(31) /* stop process on TX failure */
BIT 297 dev/ic/atwreg.h #define ATW_NAR_HF BIT(30) /* flush TX FIFO to host (?) */
BIT 298 dev/ic/atwreg.h #define ATW_NAR_UTR BIT(29) /* select retry count source */
BIT 299 dev/ic/atwreg.h #define ATW_NAR_PCF BIT(28) /* use one/both transmit
BIT 302 dev/ic/atwreg.h #define ATW_NAR_CFP BIT(27) /* indicate more TX data to
BIT 305 dev/ic/atwreg.h #define ATW_C_NAR_APSTA BIT(26) /* 0: STA mode
BIT 308 dev/ic/atwreg.h #define ATW_C_NAR_TDBBE BIT(25) /* 0: disable TDBB
BIT 311 dev/ic/atwreg.h #define ATW_C_NAR_TDBHE BIT(24) /* 0: disable TDBH
BIT 314 dev/ic/atwreg.h #define ATW_C_NAR_TDBHT BIT(23) /* write 1 to make ASIC
BIT 317 dev/ic/atwreg.h #define ATW_NAR_SF BIT(21) /* store and forward: ignore
BIT 327 dev/ic/atwreg.h #define ATW_NAR_ST BIT(13) /* start/stop transmit */
BIT 331 dev/ic/atwreg.h #define ATW_NAR_MM BIT(7) /* RX any multicast */
BIT 332 dev/ic/atwreg.h #define ATW_NAR_PR BIT(6) /* promiscuous mode */
BIT 333 dev/ic/atwreg.h #define ATW_NAR_EA BIT(5) /* match ad hoc packets (?) */
BIT 334 dev/ic/atwreg.h #define ATW_NAR_DISPCF BIT(4) /* 1: PCF *not* supported
BIT 337 dev/ic/atwreg.h #define ATW_NAR_PB BIT(3) /* pass bad packets */
BIT 338 dev/ic/atwreg.h #define ATW_NAR_STPDMA BIT(2) /* stop DMA, abort packet */
BIT 339 dev/ic/atwreg.h #define ATW_NAR_SR BIT(1) /* start/stop receive */
BIT 340 dev/ic/atwreg.h #define ATW_NAR_CTX BIT(0) /* continuous TX mode */
BIT 344 dev/ic/atwreg.h #define ATW_IER_NIE BIT(16) /* normal interrupt enable */
BIT 345 dev/ic/atwreg.h #define ATW_IER_AIE BIT(15) /* abnormal interrupt enable */
BIT 347 dev/ic/atwreg.h #define ATW_IER_PCFIE BIT(31) /* STA entered CFP */
BIT 348 dev/ic/atwreg.h #define ATW_IER_BCNTCIE BIT(30) /* STA TX'd beacon */
BIT 349 dev/ic/atwreg.h #define ATW_IER_ATIMTCIE BIT(27) /* transmitted ATIM */
BIT 350 dev/ic/atwreg.h #define ATW_IER_LINKONIE BIT(24) /* matched beacon */
BIT 351 dev/ic/atwreg.h #define ATW_IER_ATIMIE BIT(21) /* ended ATIM window */
BIT 352 dev/ic/atwreg.h #define ATW_IER_TBTTIE BIT(20) /* TBTT */
BIT 353 dev/ic/atwreg.h #define ATW_IER_TEIE BIT(14) /* moved TX packet to FIFO */
BIT 354 dev/ic/atwreg.h #define ATW_IER_REIE BIT(12) /* RX packet filled its first
BIT 357 dev/ic/atwreg.h #define ATW_IER_RCIE BIT(6) /* completed RX */
BIT 358 dev/ic/atwreg.h #define ATW_IER_TDUIE BIT(2) /* transmit descriptor
BIT 361 dev/ic/atwreg.h #define ATW_IER_TCIE BIT(0) /* completed TX */
BIT 363 dev/ic/atwreg.h #define ATW_IER_GPIE BIT(29) /* GPIO interrupt */
BIT 364 dev/ic/atwreg.h #define ATW_IER_LINKOFFIE BIT(28) /* lost beacon */
BIT 365 dev/ic/atwreg.h #define ATW_IER_TSFTFIE BIT(26) /* TSFT out of range */
BIT 366 dev/ic/atwreg.h #define ATW_IER_TSCIE BIT(25) /* TSC countdown expired */
BIT 367 dev/ic/atwreg.h #define ATW_IER_SQLIE BIT(23) /* signal quality */
BIT 368 dev/ic/atwreg.h #define ATW_IER_WEPIE BIT(22) /* finished WEP table switch */
BIT 369 dev/ic/atwreg.h #define ATW_IER_FBEIE BIT(13) /* fatal bus error */
BIT 370 dev/ic/atwreg.h #define ATW_IER_GPTIE BIT(11) /* general purpose timer expired */
BIT 371 dev/ic/atwreg.h #define ATW_IER_RPSIE BIT(8) /* stopped receive process */
BIT 372 dev/ic/atwreg.h #define ATW_IER_RUIE BIT(7) /* receive descriptor unavailable */
BIT 373 dev/ic/atwreg.h #define ATW_IER_TUIE BIT(5) /* transmit underflow */
BIT 374 dev/ic/atwreg.h #define ATW_IER_TRTIE BIT(4) /* exceeded transmit retry count */
BIT 375 dev/ic/atwreg.h #define ATW_IER_TLTTIE BIT(3) /* transmit lifetime exceeded */
BIT 376 dev/ic/atwreg.h #define ATW_IER_TPSIE BIT(1) /* stopped transmit process */
BIT 379 dev/ic/atwreg.h #define ATW_LPC_LPCO BIT(16) /* lost packet counter overflow */
BIT 382 dev/ic/atwreg.h #define ATW_TEST1_CONTROL BIT(31) /* "0: read from dxfer_control,
BIT 408 dev/ic/atwreg.h #define ATW_SPR_SRS BIT(11) /* activate SEEPROM access */
BIT 409 dev/ic/atwreg.h #define ATW_SPR_SDO BIT(3) /* data out of SEEPROM */
BIT 410 dev/ic/atwreg.h #define ATW_SPR_SDI BIT(2) /* data into SEEPROM */
BIT 411 dev/ic/atwreg.h #define ATW_SPR_SCLK BIT(1) /* SEEPROM clock */
BIT 412 dev/ic/atwreg.h #define ATW_SPR_SCS BIT(0) /* SEEPROM chip select */
BIT 461 dev/ic/atwreg.h #define ATW_TEST0_EPNE BIT(18) /* SEEPROM not detected */
BIT 462 dev/ic/atwreg.h #define ATW_TEST0_EPSNM BIT(17) /* SEEPROM bad signature */
BIT 463 dev/ic/atwreg.h #define ATW_TEST0_EPTYP_MASK BIT(16) /* SEEPROM type
BIT 469 dev/ic/atwreg.h #define ATW_TEST0_EPRLD BIT(15) /* recall SEEPROM (write 1) */
BIT 471 dev/ic/atwreg.h #define ATW_WCSR_CRCT BIT(30) /* CRC-16 type */
BIT 472 dev/ic/atwreg.h #define ATW_WCSR_WP1E BIT(29) /* match wake-up pattern 1 */
BIT 473 dev/ic/atwreg.h #define ATW_WCSR_WP2E BIT(28) /* match wake-up pattern 2 */
BIT 474 dev/ic/atwreg.h #define ATW_WCSR_WP3E BIT(27) /* match wake-up pattern 3 */
BIT 475 dev/ic/atwreg.h #define ATW_WCSR_WP4E BIT(26) /* match wake-up pattern 4 */
BIT 476 dev/ic/atwreg.h #define ATW_WCSR_WP5E BIT(25) /* match wake-up pattern 5 */
BIT 480 dev/ic/atwreg.h #define ATW_WCSR_TSFTWE BIT(20) /* wake up on TSFT out of
BIT 483 dev/ic/atwreg.h #define ATW_WCSR_TIMWE BIT(19) /* wake up on TIM */
BIT 484 dev/ic/atwreg.h #define ATW_WCSR_ATIMWE BIT(18) /* wake up on ATIM */
BIT 485 dev/ic/atwreg.h #define ATW_WCSR_KEYWE BIT(17) /* wake up on key update */
BIT 486 dev/ic/atwreg.h #define ATW_WCSR_WFRE BIT(10) /* wake up on wake-up frame */
BIT 487 dev/ic/atwreg.h #define ATW_WCSR_MPRE BIT(9) /* wake up on magic packet */
BIT 488 dev/ic/atwreg.h #define ATW_WCSR_LSOE BIT(8) /* wake up on link loss */
BIT 490 dev/ic/atwreg.h #define ATW_WCSR_KEYUP BIT(6) /* */
BIT 491 dev/ic/atwreg.h #define ATW_WCSR_TSFTW BIT(5) /* */
BIT 492 dev/ic/atwreg.h #define ATW_WCSR_TIMW BIT(4) /* */
BIT 493 dev/ic/atwreg.h #define ATW_WCSR_ATIMW BIT(3) /* */
BIT 494 dev/ic/atwreg.h #define ATW_WCSR_WFR BIT(2) /* */
BIT 495 dev/ic/atwreg.h #define ATW_WCSR_MPR BIT(1) /* */
BIT 496 dev/ic/atwreg.h #define ATW_WCSR_LSO BIT(0) /* */
BIT 498 dev/ic/atwreg.h #define ATW_GPTMR_COM_MASK BIT(16) /* continuous operation mode */
BIT 508 dev/ic/atwreg.h #define ATW_BBPCTL_TWI BIT(31) /* Intersil 3-wire interface */
BIT 511 dev/ic/atwreg.h #define ATW_BBPCTL_NEGEDGE_DO BIT(23) /* data-out on negative edge */
BIT 512 dev/ic/atwreg.h #define ATW_BBPCTL_NEGEDGE_DI BIT(22) /* data-in on negative edge */
BIT 513 dev/ic/atwreg.h #define ATW_BBPCTL_CCA_ACTLO BIT(21) /* CCA low when busy */
BIT 515 dev/ic/atwreg.h #define ATW_BBPCTL_WR BIT(17) /* start write; reset on
BIT 518 dev/ic/atwreg.h #define ATW_BBPCTL_RD BIT(16) /* start read; reset on
BIT 524 dev/ic/atwreg.h #define ATW_SYNCTL_WR BIT(31) /* start write; reset on
BIT 527 dev/ic/atwreg.h #define ATW_SYNCTL_RD BIT(30) /* start read; reset on
BIT 530 dev/ic/atwreg.h #define ATW_SYNCTL_CS0 BIT(29) /* chip select */
BIT 531 dev/ic/atwreg.h #define ATW_SYNCTL_CS1 BIT(28)
BIT 532 dev/ic/atwreg.h #define ATW_SYNCTL_CAL BIT(27) /* generate RF CAL pulse after
BIT 535 dev/ic/atwreg.h #define ATW_SYNCTL_SELCAL BIT(26) /* RF CAL source, 0: CAL bit,
BIT 539 dev/ic/atwreg.h #define ATW_C_SYNCTL_MMICE BIT(25) /* ADM8211C/CR define this
BIT 556 dev/ic/atwreg.h #define ATW_PLCPHD_PMBL BIT(15) /* 0: long preamble, 1: short */
BIT 613 dev/ic/atwreg.h #define ATW_MMIRADDR2_PROREXT BIT(15) /* Probe Response
BIT 621 dev/ic/atwreg.h #define ATW_TXBR_ALCUPDATE_MASK BIT(31) /* auto-update BBP with ALCSET */
BIT 626 dev/ic/atwreg.h #define ATW_ALCSTAT_MCOV_MASK BIT(27) /* MPDU count overflow */
BIT 627 dev/ic/atwreg.h #define ATW_ALCSTAT_ESOV_MASK BIT(26) /* error sum overflow */
BIT 663 dev/ic/atwreg.h #define ATW_CMDR_PM BIT(19) /* enables power mgmt
BIT 666 dev/ic/atwreg.h #define ATW_CMDR_APM BIT(18) /* APM mode, effective when
BIT 669 dev/ic/atwreg.h #define ATW_CMDR_RTE BIT(4) /* enable Rx FIFO threshold */
BIT 679 dev/ic/atwreg.h #define ATW_CMDR_SINT_MASK BIT(1) /* software interrupt---huh? */
BIT 737 dev/ic/atwreg.h #define ATW_C_BCNT_EXTEN1 BIT(31) /* 11M beacon len. extension */
BIT 740 dev/ic/atwreg.h #define ATW_C_BCNT_EXTEN0 BIT(15) /* 11M beacon len. extension */
BIT 741 dev/ic/atwreg.h #define ATW_C_BCNT_BEANLEN0 BIT(14,0) /* beacon length in us */
BIT 747 dev/ic/atwreg.h #define ATW_C_TSC_TIMTABSEL BIT(4) /* select TIM table 0 or 1 */
BIT 752 dev/ic/atwreg.h #define ATW_SYNRF_SELSYN BIT(31) /* 0: MAC controls SYN IF pins,
BIT 755 dev/ic/atwreg.h #define ATW_SYNRF_SELRF BIT(30) /* 0: MAC controls RF IF pins,
BIT 758 dev/ic/atwreg.h #define ATW_SYNRF_LERF BIT(29) /* if SELSYN = 1, direct control of
BIT 761 dev/ic/atwreg.h #define ATW_SYNRF_LEIF BIT(28) /* if SELSYN = 1, direct control of
BIT 764 dev/ic/atwreg.h #define ATW_SYNRF_SYNCLK BIT(27) /* if SELSYN = 1, direct control of
BIT 767 dev/ic/atwreg.h #define ATW_SYNRF_SYNDATA BIT(26) /* if SELSYN = 1, direct control of
BIT 770 dev/ic/atwreg.h #define ATW_SYNRF_PE1 BIT(25) /* if SELRF = 1, direct control of
BIT 773 dev/ic/atwreg.h #define ATW_SYNRF_PE2 BIT(24) /* if SELRF = 1, direct control of
BIT 776 dev/ic/atwreg.h #define ATW_SYNRF_PAPE BIT(23) /* if SELRF = 1, direct control of
BIT 779 dev/ic/atwreg.h #define ATW_C_SYNRF_TRSW BIT(22) /* if SELRF = 1, direct control of
BIT 782 dev/ic/atwreg.h #define ATW_C_SYNRF_TRSWN BIT(21) /* if SELRF = 1, direct control of
BIT 785 dev/ic/atwreg.h #define ATW_SYNRF_INTERSIL_EN BIT(20) /* if SELRF = 1, enables
BIT 790 dev/ic/atwreg.h #define ATW_SYNRF_PHYRST BIT(18) /* if SELRF = 1, direct control of
BIT 812 dev/ic/atwreg.h #define ATW_CAP0_RCVDTIM BIT(4) /* receive every DTIM */
BIT 818 dev/ic/atwreg.h #define ATW_RMD_ATIMST BIT(31) /* ATIM frame TX status */
BIT 819 dev/ic/atwreg.h #define ATW_RMD_CFP BIT(30) /* CFP indicator */
BIT 862 dev/ic/atwreg.h #define ATW_WEPCTL_WEPENABLE BIT(31) /* enable WEP engine */
BIT 863 dev/ic/atwreg.h #define ATW_WEPCTL_AUTOSWITCH BIT(30) /* auto-switch enable (huh?) */
BIT 864 dev/ic/atwreg.h #define ATW_WEPCTL_CURTBL BIT(29) /* current table in use */
BIT 865 dev/ic/atwreg.h #define ATW_WEPCTL_WR BIT(28) /* */
BIT 866 dev/ic/atwreg.h #define ATW_WEPCTL_RD BIT(27) /* */
BIT 867 dev/ic/atwreg.h #define ATW_WEPCTL_WEPRXBYP BIT(25) /* bypass WEP on RX */
BIT 868 dev/ic/atwreg.h #define ATW_WEPCTL_SHKEY BIT(24) /* 1: pass to host if tbl
BIT 872 dev/ic/atwreg.h #define ATW_WEPCTL_UNKNOWN0 BIT(23) /* has something to do with
BIT 882 dev/ic/atwreg.h #define ATW_WEP_ENABLED BIT(7)
BIT 883 dev/ic/atwreg.h #define ATW_WEP_104BIT BIT(6)
BIT 888 dev/ic/atwreg.h #define ATW_MACTEST_FORCE_IV BIT(23)
BIT 889 dev/ic/atwreg.h #define ATW_MACTEST_FORCE_KEYID BIT(22)
BIT 891 dev/ic/atwreg.h #define ATW_MACTEST_MMI_USETXCLK BIT(11)
BIT 895 dev/ic/atwreg.h #define ATW_FER_INTR BIT(15) /* interrupt: set regardless of mask */
BIT 896 dev/ic/atwreg.h #define ATW_FER_GWAKE BIT(4) /* general wake-up: set regardless of mask */
BIT 898 dev/ic/atwreg.h #define ATW_FEMR_INTR_EN BIT(15) /* enable INTA# */
BIT 899 dev/ic/atwreg.h #define ATW_FEMR_WAKEUP_EN BIT(14) /* enable wake-up */
BIT 900 dev/ic/atwreg.h #define ATW_FEMR_GWAKE_EN BIT(4) /* enable general wake-up */
BIT 902 dev/ic/atwreg.h #define ATW_FPSR_INTR_STATUS BIT(15) /* interrupt status */
BIT 903 dev/ic/atwreg.h #define ATW_FPSR_WAKEUP_STATUS BIT(4) /* CSTSCHG state */
BIT 904 dev/ic/atwreg.h #define ATW_FFER_INTA_FORCE BIT(15) /* activate INTA (if not masked) */
BIT 905 dev/ic/atwreg.h #define ATW_FFER_GWAKE_FORCE BIT(4) /* activate CSTSCHG (if not masked) */
BIT 963 dev/ic/atwreg.h #define ATW_TXCTL_OWN BIT(31) /* 1: ready to transmit */
BIT 964 dev/ic/atwreg.h #define ATW_TXCTL_DONE BIT(30) /* 0: not processed */
BIT 970 dev/ic/atwreg.h #define ATW_TXSTAT_ES BIT(29) /* 0: TX successful */
BIT 971 dev/ic/atwreg.h #define ATW_TXSTAT_TLT BIT(28) /* TX lifetime expired */
BIT 972 dev/ic/atwreg.h #define ATW_TXSTAT_TRT BIT(27) /* TX retry limit expired */
BIT 973 dev/ic/atwreg.h #define ATW_TXSTAT_TUF BIT(26) /* TX under-run error */
BIT 974 dev/ic/atwreg.h #define ATW_TXSTAT_TRO BIT(25) /* TX over-run error */
BIT 975 dev/ic/atwreg.h #define ATW_TXSTAT_SOFBR BIT(24) /* packet size != buffer size
BIT 980 dev/ic/atwreg.h #define ATW_TXFLAG_IC BIT(31) /* interrupt on completion */
BIT 981 dev/ic/atwreg.h #define ATW_TXFLAG_LS BIT(30) /* packet's last descriptor */
BIT 982 dev/ic/atwreg.h #define ATW_TXFLAG_FS BIT(29) /* packet's first descriptor */
BIT 983 dev/ic/atwreg.h #define ATW_TXFLAG_TER BIT(25) /* end of ring */
BIT 984 dev/ic/atwreg.h #define ATW_TXFLAG_TCH BIT(24) /* at_buf2 is 2nd chain */
BIT 998 dev/ic/atwreg.h #define ATW_RXCTL_RER BIT(25) /* end of ring */
BIT 999 dev/ic/atwreg.h #define ATW_RXCTL_RCH BIT(24) /* ar_buf2 is 2nd chain */
BIT 1003 dev/ic/atwreg.h #define ATW_RXSTAT_OWN BIT(31) /* 1: NIC may fill descriptor */
BIT 1004 dev/ic/atwreg.h #define ATW_RXSTAT_ES BIT(30) /* error summary, 0 on
BIT 1007 dev/ic/atwreg.h #define ATW_RXSTAT_SQL BIT(29) /* has signal quality (?) */
BIT 1008 dev/ic/atwreg.h #define ATW_RXSTAT_DE BIT(28) /* descriptor error---packet is
BIT 1012 dev/ic/atwreg.h #define ATW_RXSTAT_FS BIT(27) /* packet's first descriptor */
BIT 1013 dev/ic/atwreg.h #define ATW_RXSTAT_LS BIT(26) /* packet's last descriptor */
BIT 1014 dev/ic/atwreg.h #define ATW_RXSTAT_PCF BIT(25) /* received during CFP */
BIT 1015 dev/ic/atwreg.h #define ATW_RXSTAT_SFDE BIT(24) /* PLCP SFD error */
BIT 1016 dev/ic/atwreg.h #define ATW_RXSTAT_SIGE BIT(23) /* PLCP signal error */
BIT 1017 dev/ic/atwreg.h #define ATW_RXSTAT_CRC16E BIT(22) /* PLCP CRC16 error */
BIT 1018 dev/ic/atwreg.h #define ATW_RXSTAT_RXTOE BIT(21) /* RX time-out, last descriptor
BIT 1021 dev/ic/atwreg.h #define ATW_RXSTAT_CRC32E BIT(20) /* CRC32 error */
BIT 1022 dev/ic/atwreg.h #define ATW_RXSTAT_ICVE BIT(19) /* WEP ICV error */
BIT 1023 dev/ic/atwreg.h #define ATW_RXSTAT_DA1 BIT(17) /* DA bit 1, admin'd address */
BIT 1024 dev/ic/atwreg.h #define ATW_RXSTAT_DA0 BIT(16) /* DA bit 0, group address */
BIT 358 dev/ic/atwvar.h #define ATW_HDRCTL_SHORT_PREAMBLE BIT(0) /* use short preamble */
BIT 359 dev/ic/atwvar.h #define ATW_HDRCTL_RTSCTS BIT(4) /* send RTS */
BIT 360 dev/ic/atwvar.h #define ATW_HDRCTL_WEP BIT(5)
BIT 361 dev/ic/atwvar.h #define ATW_HDRCTL_UNKNOWN1 BIT(15) /* MAC adds FCS? */
BIT 362 dev/ic/atwvar.h #define ATW_HDRCTL_UNKNOWN2 BIT(8)
BIT 53 dev/ic/max2820reg.h #define MAX2820_ENABLE_RSVD1 BIT(11) /* reserved */
BIT 54 dev/ic/max2820reg.h #define MAX2820_ENABLE_PAB BIT(10) /* Transmit Baseband Filters
BIT 60 dev/ic/max2820reg.h #define MAX2820_ENABLE_TXFLT BIT(9) /* Transmit Baseband Filters
BIT 66 dev/ic/max2820reg.h #define MAX2820_ENABLE_TXUVD BIT(8) /* Tx Upconverter, VGA, and
BIT 72 dev/ic/max2820reg.h #define MAX2820_ENABLE_DET BIT(7) /* Receive Detector Enable
BIT 77 dev/ic/max2820reg.h #define MAX2820_ENABLE_RXDFA BIT(6) /* Rx Downconverter, Filters,
BIT 83 dev/ic/max2820reg.h #define MAX2820_ENABLE_RXLNA BIT(5) /* Receive LNA Enable
BIT 88 dev/ic/max2820reg.h #define MAX2820_ENABLE_AT BIT(4) /* Auto-tuner Enable
BIT 93 dev/ic/max2820reg.h #define MAX2820_ENABLE_CP BIT(3) /* PLL Charge-Pump Enable
BIT 97 dev/ic/max2820reg.h #define MAX2820_ENABLE_PLL BIT(2) /* PLL Enable
BIT 101 dev/ic/max2820reg.h #define MAX2820_ENABLE_VCO BIT(1) /* VCO Enable
BIT 105 dev/ic/max2820reg.h #define MAX2820_ENABLE_RSVD0 BIT(0) /* reserved */
BIT 111 dev/ic/max2820reg.h #define MAX2820_SYNTH_ICP BIT(6) /* Charge-Pump Current Select
BIT 147 dev/ic/max2820reg.h #define MAX2820_RECEIVE_SF BIT(3) /* Special Function Select
BIT 64 dev/ic/rf3000reg.h #define RF3000_RXSTAT_SHORTPRE BIT(3) /* 1: short preamble */
BIT 65 dev/ic/rf3000reg.h #define RF3000_RXSTAT_ACQ BIT(2) /* 1: acquired */
BIT 66 dev/ic/rf3000reg.h #define RF3000_RXSTAT_SFD BIT(1) /* 1: SFD detected */
BIT 67 dev/ic/rf3000reg.h #define RF3000_RXSTAT_CRC BIT(0) /* 1: CRC invalid */
BIT 77 dev/ic/rf3000reg.h #define RF3000_DIVCTL_ENABLE BIT(7) /* enable diversity */
BIT 78 dev/ic/rf3000reg.h #define RF3000_DIVCTL_ANTSEL BIT(6) /* if ENABLE = 0, set
BIT 85 dev/ic/rf3000reg.h #define RF3000_GAINCTL_SCRAMBLER BIT(1)
BIT 90 dev/ic/rf3000reg.h #define RF3000_HIGAINCAL_DSSSPAD BIT(6) /* 6dB gain pad for DSSS
BIT 97 dev/ic/rf3000reg.h #define RF3000_OPTIONS1_SAT_THRESH_SIGN BIT(7)
BIT 99 dev/ic/rf3000reg.h #define RF3000_OPTIONS1_ALTAGC BIT(4) /* 1: retrigger AGC
BIT 103 dev/ic/rf3000reg.h #define RF3000_OPTIONS1_ALTBUS BIT(3) /* 1: enable alternate
BIT 111 dev/ic/rf3000reg.h #define RF3000_OPTIONS2_LNAGS_DELAY BIT(7)
BIT 114 dev/ic/rf3000reg.h #define RF3000_OPTIONS2_RTG_THRESH BIT(2)
BIT 42 dev/ic/rtwreg.h #define BITS(m, n) ((BIT(MAX((m), (n)) + 1) - 1) ^ (BIT(MIN((m), (n))) - 1))
BIT 108 dev/ic/rtwreg.h #define RTW8180_BRSR_BPLCP BIT(8) /* 1: Short PLCP CTS/ACK header */
BIT 115 dev/ic/rtwreg.h #define RTW8185_BRSR_MBR_1MBPS BIT(0)
BIT 116 dev/ic/rtwreg.h #define RTW8185_BRSR_MBR_2MBPS BIT(1)
BIT 117 dev/ic/rtwreg.h #define RTW8185_BRSR_MBR_5MBPS BIT(2)
BIT 118 dev/ic/rtwreg.h #define RTW8185_BRSR_MBR_11MBPS BIT(3)
BIT 119 dev/ic/rtwreg.h #define RTW8185_BRSR_MBR_6MBPS BIT(4)
BIT 120 dev/ic/rtwreg.h #define RTW8185_BRSR_MBR_9MBPS BIT(5)
BIT 121 dev/ic/rtwreg.h #define RTW8185_BRSR_MBR_12MBPS BIT(6)
BIT 122 dev/ic/rtwreg.h #define RTW8185_BRSR_MBR_18MBPS BIT(7)
BIT 123 dev/ic/rtwreg.h #define RTW8185_BRSR_MBR_24MBPS BIT(8)
BIT 124 dev/ic/rtwreg.h #define RTW8185_BRSR_MBR_36MBPS BIT(9)
BIT 125 dev/ic/rtwreg.h #define RTW8185_BRSR_MBR_48MBPS BIT(10)
BIT 126 dev/ic/rtwreg.h #define RTW8185_BRSR_MBR_54MBPS BIT(11)
BIT 140 dev/ic/rtwreg.h #define RTW8185_RR_MAX BIT(7, 4)
BIT 153 dev/ic/rtwreg.h #define RTW8185_RR_MIN_MASK BIT(3, 0)
BIT 170 dev/ic/rtwreg.h #define RTW_CR_RST BIT(4) /* Reset: host sets to 1 to disable
BIT 174 dev/ic/rtwreg.h #define RTW_CR_RE BIT(3) /* Receiver Enable: host enables receiver
BIT 179 dev/ic/rtwreg.h #define RTW_CR_TE BIT(2) /* Transmitter Enable: host enables transmitter
BIT 184 dev/ic/rtwreg.h #define RTW_CR_MULRW BIT(0) /* PCI Multiple Read/Write enable: 1 enables,
BIT 191 dev/ic/rtwreg.h #define RTW_INTR_TXFOVW BIT(15) /* Tx FIFO underrflow */
BIT 192 dev/ic/rtwreg.h #define RTW_INTR_TIMEOUT BIT(14) /* Time Out: 1 indicates
BIT 195 dev/ic/rtwreg.h #define RTW_INTR_BCNINT BIT(13) /* Beacon Time Out: time for host to
BIT 200 dev/ic/rtwreg.h #define RTW_INTR_ATIMINT BIT(12)
BIT 205 dev/ic/rtwreg.h #define RTW_INTR_TBDER BIT(11) /* Tx Beacon Descriptor Error:
BIT 209 dev/ic/rtwreg.h #define RTW_INTR_TBDOK BIT(10) /* Tx Beacon Descriptor OK */
BIT 210 dev/ic/rtwreg.h #define RTW_INTR_THPDER BIT(9) /* Tx High Priority Descriptor Error:
BIT 213 dev/ic/rtwreg.h #define RTW_INTR_THPDOK BIT(8) /* Tx High Priority Descriptor OK */
BIT 214 dev/ic/rtwreg.h #define RTW_INTR_TNPDER BIT(7) /* Tx Normal Priority Descriptor Error:
BIT 217 dev/ic/rtwreg.h #define RTW_INTR_TNPDOK BIT(6) /* Tx Normal Priority Descriptor OK */
BIT 218 dev/ic/rtwreg.h #define RTW_INTR_RXFOVW BIT(5) /* Rx FIFO Overflow: either RDU (see below)
BIT 221 dev/ic/rtwreg.h #define RTW_INTR_RDU BIT(4) /* Rx Descriptor Unavailable */
BIT 222 dev/ic/rtwreg.h #define RTW_INTR_TLPDER BIT(3) /* Tx Normal Priority Descriptor Error
BIT 225 dev/ic/rtwreg.h #define RTW_INTR_TLPDOK BIT(2) /* Tx Normal Priority Descriptor OK */
BIT 226 dev/ic/rtwreg.h #define RTW_INTR_RER BIT(1) /* Rx Error: CRC32 or ICV error */
BIT 227 dev/ic/rtwreg.h #define RTW_INTR_ROK BIT(0) /* Rx OK */
BIT 238 dev/ic/rtwreg.h #define RTW_TCR_CWMIN BIT(31) /* 1: CWmin = 8, 0: CWmin = 32. */
BIT 239 dev/ic/rtwreg.h #define RTW_TCR_SWSEQ BIT(30) /* 1: host assigns 802.11 sequence number,
BIT 242 dev/ic/rtwreg.h #define RTW8185_TCR_NOPROBERSPTO BIT(29) /* No Probe Rsp timeout */
BIT 245 dev/ic/rtwreg.h #define RTW_TCR_HWVERID_RTL8180D BIT(26)
BIT 247 dev/ic/rtwreg.h #define RTW_TCR_HWVERID_RTL8185 (BIT(27) | BIT(25))
BIT 252 dev/ic/rtwreg.h #define RTW8180_TCR_SAT BIT(24)
BIT 256 dev/ic/rtwreg.h #define RTW8185_TCR_PLCPLENGTH BIT(24)
BIT 268 dev/ic/rtwreg.h #define RTW_TCR_DISCW BIT(20) /* disable 802.11 random backoff */
BIT 270 dev/ic/rtwreg.h #define RTW_TCR_ICV BIT(19) /* host lets RTL8180 append ICV to
BIT 281 dev/ic/rtwreg.h #define RTW_TCR_CRC BIT(16) /* 0: RTL8180 appends CRC32
BIT 293 dev/ic/rtwreg.h #define RTW_RCR_ONLYERLPKT BIT(31) /* only do Early Rx on packets
BIT 296 dev/ic/rtwreg.h #define RTW_RCR_ENCS2 BIT(30) /* enable carrier sense method 2 */
BIT 297 dev/ic/rtwreg.h #define RTW_RCR_ENCS1 BIT(29) /* enable carrier sense method 1 */
BIT 298 dev/ic/rtwreg.h #define RTW_RCR_ENMARP BIT(28) /* enable MAC auto-reset PHY */
BIT 299 dev/ic/rtwreg.h #define RTW_RCR_CBSSID BIT(23) /* Check BSSID/ToDS/FromDS: set
BIT 305 dev/ic/rtwreg.h #define RTW_RCR_APWRMGT BIT(22) /* accept packets w/ PWRMGMT bit set */
BIT 306 dev/ic/rtwreg.h #define RTW_RCR_ADD3 BIT(21) /* when RTW_MSR_NETYPE ==
BIT 311 dev/ic/rtwreg.h #define RTW_RCR_AMF BIT(20) /* accept management frames */
BIT 312 dev/ic/rtwreg.h #define RTW_RCR_ACF BIT(19) /* accept control frames */
BIT 313 dev/ic/rtwreg.h #define RTW_RCR_ADF BIT(18) /* accept data frames */
BIT 325 dev/ic/rtwreg.h #define RTW_RCR_AICV BIT(12) /* accept frames w/ ICV errors */
BIT 339 dev/ic/rtwreg.h #define RTW_RCR_9356SEL BIT(6)
BIT 341 dev/ic/rtwreg.h #define RTW_RCR_ACRC32 BIT(5) /* accept frames w/ CRC32 errors */
BIT 342 dev/ic/rtwreg.h #define RTW_RCR_AB BIT(3) /* accept broadcast frames */
BIT 343 dev/ic/rtwreg.h #define RTW_RCR_AM BIT(2) /* accept multicast frames */
BIT 345 dev/ic/rtwreg.h #define RTW_RCR_APM BIT(1)
BIT 346 dev/ic/rtwreg.h #define RTW_RCR_AAP BIT(0) /* accept frames w/ destination */
BIT 401 dev/ic/rtwreg.h #define RTW_9346CR_EECS BIT(3)
BIT 402 dev/ic/rtwreg.h #define RTW_9346CR_EESK BIT(2)
BIT 403 dev/ic/rtwreg.h #define RTW_9346CR_EEDI BIT(1)
BIT 404 dev/ic/rtwreg.h #define RTW_9346CR_EEDO BIT(0) /* read-only */
BIT 407 dev/ic/rtwreg.h #define RTW8180_CONFIG0_WEP40 BIT(7) /* implements 40-bit WEP,
BIT 409 dev/ic/rtwreg.h #define RTW8180_CONFIG0_WEP104 BIT(6) /* implements 104-bit WEP,
BIT 412 dev/ic/rtwreg.h #define RTW8180_CONFIG0_LEDGPOEN BIT(4) /* 1: RTW_PSR_LEDGPO[01] control
BIT 418 dev/ic/rtwreg.h #define RTW_CONFIG0_AUXPWR BIT(3)
BIT 451 dev/ic/rtwreg.h #define RTW_CONFIG1_LWACT BIT(4)
BIT 453 dev/ic/rtwreg.h #define RTW_CONFIG1_MEMMAP BIT(3) /* using PCI memory space, read-only */
BIT 454 dev/ic/rtwreg.h #define RTW_CONFIG1_IOMAP BIT(2) /* using PCI I/O space, read-only */
BIT 455 dev/ic/rtwreg.h #define RTW_CONFIG1_VPD BIT(1) /* if set, VPD from offsets
BIT 460 dev/ic/rtwreg.h #define RTW_CONFIG1_PMEN BIT(0) /* Power Management Enable: TBD */
BIT 463 dev/ic/rtwreg.h #define RTW_CONFIG2_LCK BIT(7) /* clocks are locked, read-only:
BIT 467 dev/ic/rtwreg.h #define RTW8180_CONFIG2_ANT BIT(6) /* diversity enabled, read-only */
BIT 468 dev/ic/rtwreg.h #define RTW_CONFIG2_DPS BIT(3) /* Descriptor Polling State: enable
BIT 471 dev/ic/rtwreg.h #define RTW_CONFIG2_PAPESIGN BIT(2) /* TBD, from EEPROM */
BIT 486 dev/ic/rtwreg.h #define RTW_ANAPARM_TXDACOFF BIT(27) /* 1: disable Tx DAC,
BIT 555 dev/ic/rtwreg.h #define RTW_CONFIG3_GNTSEL BIT(7) /* Grant Select, read-only */
BIT 556 dev/ic/rtwreg.h #define RTW_CONFIG3_PARMEN BIT(6) /* Set RTW_CONFIG3_PARMEN and
BIT 560 dev/ic/rtwreg.h #define RTW_CONFIG3_MAGIC BIT(5) /* Valid when RTW_CONFIG1_PMEN is
BIT 564 dev/ic/rtwreg.h #define RTW_CONFIG3_CARDBEN BIT(3) /* Cardbus-related registers
BIT 568 dev/ic/rtwreg.h #define RTW_CONFIG3_CLKRUNEN BIT(2) /* CLKRUN enabled, read-only.
BIT 571 dev/ic/rtwreg.h #define RTW_CONFIG3_FUNCREGEN BIT(1) /* Function Registers Enabled,
BIT 574 dev/ic/rtwreg.h #define RTW_CONFIG3_FBTBEN BIT(0) /* Fast back-to-back enabled,
BIT 578 dev/ic/rtwreg.h #define RTW_CONFIG4_VCOPDN BIT(7) /* VCO Power Down
BIT 584 dev/ic/rtwreg.h #define RTW_CONFIG4_PWROFF BIT(6) /* Power Off
BIT 593 dev/ic/rtwreg.h #define RTW_CONFIG4_PWRMGT BIT(5) /* Power Management
BIT 598 dev/ic/rtwreg.h #define RTW_CONFIG4_LWPME BIT(4) /* LANWAKE vs. PMEB: Cardbus-only
BIT 606 dev/ic/rtwreg.h #define RTW_CONFIG4_LWPTN BIT(2) /* see RTW_CONFIG1_LWACT
BIT 618 dev/ic/rtwreg.h #define RTW_PSR_GPO BIT(7) /* Control/status of pin 52. */
BIT 619 dev/ic/rtwreg.h #define RTW_PSR_GPI BIT(6) /* Status of pin 64. */
BIT 620 dev/ic/rtwreg.h #define RTW_PSR_LEDGPO1 BIT(5) /* Status/control of LED1 pin if
BIT 623 dev/ic/rtwreg.h #define RTW_PSR_LEDGPO0 BIT(4) /* Status/control of LED0 pin if
BIT 626 dev/ic/rtwreg.h #define RTW_PSR_UWF BIT(1) /* Enable Unicast Wakeup Frame */
BIT 627 dev/ic/rtwreg.h #define RTW_PSR_PSEN BIT(0) /* 1: page 1, 0: page 0 */
BIT 633 dev/ic/rtwreg.h #define RTW8180_SCR_TXSECON BIT(1) /* Enable Tx WEP. Invalid if
BIT 637 dev/ic/rtwreg.h #define RTW8180_SCR_RXSECON BIT(0) /* Enable Rx WEP. Invalid if
BIT 666 dev/ic/rtwreg.h #define RTW_PHYDELAY_REVC_MAGIC BIT(3) /* Rev. C magic from reference
BIT 681 dev/ic/rtwreg.h #define RTW_BB_WREN BIT(7) /* write enable */
BIT 689 dev/ic/rtwreg.h #define RTW8180_PHYCFG_MAC_POLL BIT(31) /* if !RTW8180_PHYCFG_HST,
BIT 693 dev/ic/rtwreg.h #define RTW8180_PHYCFG_HST BIT(30) /* 1: host bangs bits
BIT 710 dev/ic/rtwreg.h #define RTW8180_PHYCFG_HST_EN BIT(2)
BIT 711 dev/ic/rtwreg.h #define RTW8180_PHYCFG_HST_CLK BIT(1)
BIT 712 dev/ic/rtwreg.h #define RTW8180_PHYCFG_HST_DATA BIT(0)
BIT 789 dev/ic/rtwreg.h #define RTW8185_CAMRW_POOLING BIT(31) /* Pooling bit */
BIT 790 dev/ic/rtwreg.h #define RTW8185_CAMRW_WRITE BIT(16) /* Write enable */
BIT 797 dev/ic/rtwreg.h #define RTW8185_CAMDEBUG_SELTXRXINFO BIT(31)
BIT 798 dev/ic/rtwreg.h #define RTW8185_CAMDEBUG_KEYFOUND BIT(30)
BIT 803 dev/ic/rtwreg.h #define RTW8185_WPACONFIG_RXWPADUMMY BIT(8)
BIT 804 dev/ic/rtwreg.h #define RTW8185_WPACONFIG_DISRX_AESMIC BIT(3)
BIT 805 dev/ic/rtwreg.h #define RTW8185_WPACONFIG_RXDECRYPT BIT(2)
BIT 806 dev/ic/rtwreg.h #define RTW8185_WPACONFIG_TXENCRYPT BIT(1)
BIT 807 dev/ic/rtwreg.h #define RTW8185_WPACONFIG_USEDEFAULTKEY BIT(0)
BIT 816 dev/ic/rtwreg.h #define RTW8185_CWCONFIG_PPRETRYLIMIT BIT(1) /* Per-Packet Retry Limit */
BIT 817 dev/ic/rtwreg.h #define RTW8185_CWCONFIG_PPCW BIT(1) /* Per-Packet Cont. Window */
BIT 824 dev/ic/rtwreg.h #define RTW8185_RATEFALLBACKCTL_ENABLE BIT(7)
BIT 828 dev/ic/rtwreg.h #define RTW_CONFIG5_TXFIFOOK BIT(7) /* Tx FIFO self-test pass, read-only */
BIT 829 dev/ic/rtwreg.h #define RTW_CONFIG5_RXFIFOOK BIT(6) /* Rx FIFO self-test pass, read-only */
BIT 830 dev/ic/rtwreg.h #define RTW_CONFIG5_CALON BIT(5) /* 1: start calibration cycle
BIT 834 dev/ic/rtwreg.h #define RTW_CONFIG5_EACPI BIT(2) /* Enable ACPI Wake up, default 0 */
BIT 835 dev/ic/rtwreg.h #define RTW_CONFIG5_LANWAKE BIT(1) /* Enable LAN Wake signal,
BIT 838 dev/ic/rtwreg.h #define RTW_CONFIG5_PMESTS BIT(0) /* 1: both software & PCI Reset
BIT 848 dev/ic/rtwreg.h #define RTW_TPPOLL_BQ BIT(7) /* RTL8180 clears to notify host of a beacon
BIT 851 dev/ic/rtwreg.h #define RTW_TPPOLL_HPQ BIT(6) /* Host writes 1 to notify RTL8180 of
BIT 855 dev/ic/rtwreg.h #define RTW_TPPOLL_NPQ BIT(5) /* If RTW_CONFIG2_DPS is set,
BIT 864 dev/ic/rtwreg.h #define RTW_TPPOLL_LPQ BIT(4) /* Host writes 1 to notify RTL8180 of
BIT 868 dev/ic/rtwreg.h #define RTW_TPPOLL_SBQ BIT(3) /* Host writes 1 to tell RTL8180 to
BIT 872 dev/ic/rtwreg.h #define RTW_TPPOLL_SHPQ BIT(2) /* Host writes 1 to tell RTL8180 to
BIT 875 dev/ic/rtwreg.h #define RTW_TPPOLL_SNPQ BIT(1) /* Host writes 1 to tell RTL8180 to
BIT 879 dev/ic/rtwreg.h #define RTW_TPPOLL_SLPQ BIT(0) /* Host writes 1 to tell RTL8180 to
BIT 909 dev/ic/rtwreg.h #define RTW_FER_INTR BIT(15) /* set when RTW_FFER_INTR is set */
BIT 910 dev/ic/rtwreg.h #define RTW_FER_GWAKE BIT(4) /* General Wakeup */
BIT 915 dev/ic/rtwreg.h #define RTW_FEMR_INTR BIT(15) /* set when RTW_FFER_INTR is set */
BIT 916 dev/ic/rtwreg.h #define RTW_FEMR_WKUP BIT(14) /* Wakeup Mask */
BIT 917 dev/ic/rtwreg.h #define RTW_FEMR_GWAKE BIT(4) /* General Wakeup */
BIT 923 dev/ic/rtwreg.h #define RTW_FPSR_INTR BIT(15) /* TBD */
BIT 924 dev/ic/rtwreg.h #define RTW_FPSR_GWAKE BIT(4) /* General Wakeup: TBD */
BIT 930 dev/ic/rtwreg.h #define RTW_FFER_INTR BIT(15) /* TBD */
BIT 931 dev/ic/rtwreg.h #define RTW_FFER_GWAKE BIT(4) /* General Wakeup: TBD */
BIT 971 dev/ic/rtwreg.h #define RTW_SR_RFPARM_DIGPHY BIT(0) /* 1: digital PHY */
BIT 972 dev/ic/rtwreg.h #define RTW_SR_RFPARM_DFLANTB BIT(1) /* 1: antenna B is default */
BIT 998 dev/ic/rtwreg.h #define RTW_TXCTL0_OWN BIT(31) /* 1: ready to Tx */
BIT 999 dev/ic/rtwreg.h #define RTW_TXCTL0_RSVD0 BIT(30) /* reserved */
BIT 1000 dev/ic/rtwreg.h #define RTW_TXCTL0_FS BIT(29) /* first segment */
BIT 1001 dev/ic/rtwreg.h #define RTW_TXCTL0_LS BIT(28) /* last segment */
BIT 1009 dev/ic/rtwreg.h #define RTW_TXCTL0_RTSEN BIT(23) /* RTS Enable */
BIT 1017 dev/ic/rtwreg.h #define RTW_TXCTL0_BEACON BIT(18) /* packet is a beacon */
BIT 1018 dev/ic/rtwreg.h #define RTW_TXCTL0_MOREFRAG BIT(17) /* another fragment follows */
BIT 1019 dev/ic/rtwreg.h #define RTW_TXCTL0_SPLCP BIT(16) /* add short PLCP preamble
BIT 1033 dev/ic/rtwreg.h #define RTW_TXSTAT_TOK BIT(15)
BIT 1037 dev/ic/rtwreg.h #define RTW_TXCTL1_LENGEXT BIT(31) /* supplements _LENGTH
BIT 1061 dev/ic/rtwreg.h #define RTW_RXCTL_OWN BIT(31) /* 1: owned by NIC */
BIT 1062 dev/ic/rtwreg.h #define RTW_RXCTL_EOR BIT(30) /* end of ring */
BIT 1063 dev/ic/rtwreg.h #define RTW_RXCTL_FS BIT(29) /* first segment */
BIT 1064 dev/ic/rtwreg.h #define RTW_RXCTL_LS BIT(28) /* last segment */
BIT 1072 dev/ic/rtwreg.h #define RTW_RXSTAT_DMAFAIL BIT(27) /* DMA failure on this pkt */
BIT 1073 dev/ic/rtwreg.h #define RTW_RXSTAT_BOVF BIT(26) /* buffer overflow XXX means
BIT 1076 dev/ic/rtwreg.h #define RTW_RXSTAT_SPLCP BIT(25) /* Rx'd with short preamble
BIT 1079 dev/ic/rtwreg.h #define RTW_RXSTAT_RSVD1 BIT(24) /* reserved */
BIT 1085 dev/ic/rtwreg.h #define RTW_RXSTAT_MIC BIT(19) /* XXX from reference driver */
BIT 1086 dev/ic/rtwreg.h #define RTW_RXSTAT_MAR BIT(18) /* is multicast */
BIT 1087 dev/ic/rtwreg.h #define RTW_RXSTAT_PAR BIT(17) /* matches RTL8180's MAC */
BIT 1088 dev/ic/rtwreg.h #define RTW_RXSTAT_BAR BIT(16) /* is broadcast */
BIT 1089 dev/ic/rtwreg.h #define RTW_RXSTAT_RES BIT(15) /* error summary. valid when
BIT 1094 dev/ic/rtwreg.h #define RTW_RXSTAT_PWRMGT BIT(14) /* 802.11 PWRMGMT bit is set */
BIT 1095 dev/ic/rtwreg.h #define RTW_RXSTAT_CRC16 BIT(14) /* XXX CRC16 error, from
BIT 1098 dev/ic/rtwreg.h #define RTW_RXSTAT_CRC32 BIT(13) /* CRC32 error */
BIT 1099 dev/ic/rtwreg.h #define RTW_RXSTAT_ICV BIT(12) /* ICV error */
BIT 1119 dev/ic/rtwreg.h #define RTW_RXRSSI_IMR_LNA BIT(8) /* 1: LNA activated */
BIT 42 dev/ic/sa2400reg.h #define SA2400_TWI_WREN BIT(7) /* enable write */
BIT 49 dev/ic/sa2400reg.h #define SA2400_SYNA_FM BIT(21) /* fractional modulus select,
BIT 70 dev/ic/sa2400reg.h #define SA2400_SYNB_ON BIT(9) /* power on/off,
BIT 75 dev/ic/sa2400reg.h #define SA2400_SYNB_ONE BIT(8) /* always 1 */
BIT 94 dev/ic/sa2400reg.h #define SA2400_SYNC_ZERO BIT(2) /* always 0 */
BIT 98 dev/ic/sa2400reg.h #define SA2400_SYND_TPHPSU BIT(16) /* T[phpsu], 1: disable
BIT 102 dev/ic/sa2400reg.h #define SA2400_SYND_TPSU BIT(15) /* T[spu], 1: speedup on,
BIT 110 dev/ic/sa2400reg.h #define SA2400_OPMODE_ADC BIT(19) /* 1: in Rx mode, RSSI-ADC always on
BIT 113 dev/ic/sa2400reg.h #define SA2400_OPMODE_FTERR BIT(18) /* read-only filter tuner error:
BIT 121 dev/ic/sa2400reg.h #define SA2400_OPMODE_V2P5 BIT(14) /* external reference voltage
BIT 124 dev/ic/sa2400reg.h #define SA2400_OPMODE_I1M BIT(13) /* external reference current ... */
BIT 125 dev/ic/sa2400reg.h #define SA2400_OPMODE_I0P3 BIT(12) /* external reference current ... */
BIT 126 dev/ic/sa2400reg.h #define SA2400_OPMODE_IN22 BIT(10) /* xtal input frequency,
BIT 130 dev/ic/sa2400reg.h #define SA2400_OPMODE_CLK BIT(9) /* reference clock output on */
BIT 131 dev/ic/sa2400reg.h #define SA2400_OPMODE_XO BIT(8) /* xtal oscillator on */
BIT 132 dev/ic/sa2400reg.h #define SA2400_OPMODE_DIGIN BIT(7) /* use digital Tx inputs (FIRDAC) */
BIT 133 dev/ic/sa2400reg.h #define SA2400_OPMODE_RXLV BIT(6) /* Rx output common mode voltage,
BIT 137 dev/ic/sa2400reg.h #define SA2400_OPMODE_VEO BIT(5) /* make internal vco
BIT 140 dev/ic/sa2400reg.h #define SA2400_OPMODE_VEI BIT(4) /* use external vco input (vcoextin) */
BIT 158 dev/ic/sa2400reg.h #define SA2400_AGC_TARGETSIGN BIT(23) /* fine-tune AGC target:
BIT 186 dev/ic/sa2400reg.h #define SA2400_MANRX_AHSN BIT(23) /* 1: AGC w/ high S/N---switch LNA at
BIT 197 dev/ic/sa2400reg.h #define SA2400_MANRX_RXOSQON BIT(22) /* Rx Q-channel correction. */
BIT 198 dev/ic/sa2400reg.h #define SA2400_MANRX_RXOSQSIGN BIT(21)
BIT 201 dev/ic/sa2400reg.h #define SA2400_MANRX_RXOSION BIT(17) /* Rx I-channel correction. */
BIT 202 dev/ic/sa2400reg.h #define SA2400_MANRX_RXOSISIGN BIT(16)
BIT 204 dev/ic/sa2400reg.h #define SA2400_MANRX_TEN BIT(12) /* use 10MHz offset cancellation
BIT 226 dev/ic/sa2400reg.h #define SA2400_TX_TXOSQON BIT(19)
BIT 227 dev/ic/sa2400reg.h #define SA2400_TX_TXOSQSIGN BIT(18)
BIT 229 dev/ic/sa2400reg.h #define SA2400_TX_TXOSION BIT(14)
BIT 230 dev/ic/sa2400reg.h #define SA2400_TX_TXOSISIGN BIT(13)
BIT 250 dev/ic/sa2400reg.h #define SA2400_VCO_VCERR BIT(4) /* VCO calibration error flag---no
BIT 60 dev/ic/si4136reg.h #define SI4126_MAIN_XINDIV2 BIT(6) /* 1: divide crystal input (XIN) by 2 */
BIT 61 dev/ic/si4136reg.h #define SI4126_MAIN_LPWR BIT(5) /* 1: low-power mode */
BIT 62 dev/ic/si4136reg.h #define SI4126_MAIN_AUTOPDB BIT(3) /* 1: equivalent to
BIT 77 dev/ic/si4136reg.h #define SI4126_POWER_PDIB BIT(1) /* 1: IF synthesizer on */
BIT 78 dev/ic/si4136reg.h #define SI4126_POWER_PDRB BIT(0) /* 1: RF synthesizer on */
BIT 793 dev/usb/uaudio.c if (BIT(bno))
BIT 804 dev/usb/uaudio.c if (BIT(bno))