reg0 1321 dev/ic/aic6915.c uint32_t reg0, reg1, reg2;
reg0 1323 dev/ic/aic6915.c reg0 = enaddr[5] | (enaddr[4] << 8);
reg0 1327 dev/ic/aic6915.c sf_genreg_write(sc, SF_PERFECT_BASE + (slot * 0x10) + 0, reg0);
reg0 4891 dev/ic/rtw.c u_int16_t reg0, reg1, reg2;
reg0 4899 dev/ic/rtw.c reg0 = RTW_READ16(regs, RTW8185_RFPINSOUTPUT) &
reg0 4903 dev/ic/rtw.c RTW8185_RFPINSENABLE_ENABLE | reg0);
reg0 4909 dev/ic/rtw.c RTW_WRITE16(regs, RTW8185_RFPINSOUTPUT, reg0);
reg0 5175 dev/ic/rtw.c rtw_barrier(void *arg, u_int32_t reg0, u_int32_t reg1, int flags)
reg0 5178 dev/ic/rtw.c bus_space_barrier(regs->r_bt, regs->r_bh, MIN(reg0, reg1),
reg0 5179 dev/ic/rtw.c MAX(reg0, reg1) - MIN(reg0, reg1) + 4, flags);
reg0 1174 dev/ic/rtwreg.h #define RTW_BARRIER(regs, reg0, reg1, flags) \
reg0 1175 dev/ic/rtwreg.h ((*(regs)->r_barrier)(regs, reg0, reg1, flags))
reg0 1181 dev/ic/rtwreg.h #define RTW_SYNC(regs, reg0, reg1) \
reg0 1182 dev/ic/rtwreg.h RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_SYNC)
reg0 1185 dev/ic/rtwreg.h #define RTW_WBW(regs, reg0, reg1) \
reg0 1186 dev/ic/rtwreg.h RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE)
reg0 1189 dev/ic/rtwreg.h #define RTW_WBR(regs, reg0, reg1) \
reg0 1190 dev/ic/rtwreg.h RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_READ)
reg0 1193 dev/ic/rtwreg.h #define RTW_RBR(regs, reg0, reg1) \
reg0 1194 dev/ic/rtwreg.h RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_READ)
reg0 1197 dev/ic/rtwreg.h #define RTW_RBW(regs, reg0, reg1) \
reg0 1198 dev/ic/rtwreg.h RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_WRITE)
reg0 1200 dev/ic/rtwreg.h #define RTW_WBRW(regs, reg0, reg1) \
reg0 1201 dev/ic/rtwreg.h RTW_BARRIER(regs, reg0, reg1, \
reg0 967 dev/ic/smc83c170.c u_int32_t genctl, reg0;
reg0 1000 dev/ic/smc83c170.c reg0 = bus_space_read_4(st, sh, EPIC_NVCTL);
reg0 1001 dev/ic/smc83c170.c bus_space_write_4(st, sh, EPIC_NVCTL, reg0 | NVCTL_GPIO1 | NVCTL_GPOE1);
reg0 1007 dev/ic/smc83c170.c bus_space_write_4(st, sh, EPIC_NVCTL, reg0);
reg0 1012 dev/ic/smc83c170.c reg0 = sc->sc_arpcom.ac_enaddr[1] << 8 | sc->sc_arpcom.ac_enaddr[0];
reg0 1013 dev/ic/smc83c170.c bus_space_write_4(st, sh, EPIC_LAN0, reg0);
reg0 1014 dev/ic/smc83c170.c reg0 = sc->sc_arpcom.ac_enaddr[3] << 8 | sc->sc_arpcom.ac_enaddr[2];
reg0 1015 dev/ic/smc83c170.c bus_space_write_4(st, sh, EPIC_LAN1, reg0);
reg0 1016 dev/ic/smc83c170.c reg0 = sc->sc_arpcom.ac_enaddr[5] << 8 | sc->sc_arpcom.ac_enaddr[4];
reg0 1017 dev/ic/smc83c170.c bus_space_write_4(st, sh, EPIC_LAN2, reg0);
reg0 1023 dev/ic/smc83c170.c reg0 = bus_space_read_4(st, sh, EPIC_RXCON) &
reg0 1025 dev/ic/smc83c170.c reg0 |= (RXCON_RXMULTICAST | RXCON_RXBROADCAST);
reg0 1027 dev/ic/smc83c170.c reg0 |= RXCON_PROMISCMODE;
reg0 1028 dev/ic/smc83c170.c bus_space_write_4(st, sh, EPIC_RXCON, reg0);
reg0 202 dev/isa/viasio.c u_int8_t reg0, reg1;
reg0 215 dev/isa/viasio.c reg0 = viasio_conf_read(sc->sc_iot, sc->sc_ioh, VT1211_HM_ACT);
reg0 216 dev/isa/viasio.c DPRINTF((": ACT 0x%02x", reg0));
reg0 217 dev/isa/viasio.c if ((reg0 & VT1211_HM_ACT_EN) == 0) {
reg0 220 dev/isa/viasio.c reg0 |= VT1211_HM_ACT_EN;
reg0 222 dev/isa/viasio.c VT1211_HM_ACT, reg0);
reg0 223 dev/isa/viasio.c reg0 = viasio_conf_read(sc->sc_iot, sc->sc_ioh,
reg0 225 dev/isa/viasio.c DPRINTF((", new ACT 0x%02x", reg0));
reg0 226 dev/isa/viasio.c if ((reg0 & VT1211_HM_ACT_EN) == 0) {
reg0 237 dev/isa/viasio.c reg0 = viasio_conf_read(sc->sc_iot, sc->sc_ioh, VT1211_HM_ADDR_LSB);
reg0 239 dev/isa/viasio.c iobase = (reg1 << 8) | reg0;
reg0 253 dev/isa/viasio.c reg0 = bus_space_read_1(sc->sc_iot, sc->sc_hm_ioh, VT1211_HM_CONF);
reg0 254 dev/isa/viasio.c DPRINTF((", CONF 0x%02x", reg0));
reg0 255 dev/isa/viasio.c if ((reg0 & VT1211_HM_CONF_START) == 0) {
reg0 258 dev/isa/viasio.c reg0 |= VT1211_HM_CONF_START;
reg0 260 dev/isa/viasio.c VT1211_HM_CONF, reg0);
reg0 261 dev/isa/viasio.c reg0 = bus_space_read_1(sc->sc_iot, sc->sc_hm_ioh,
reg0 263 dev/isa/viasio.c DPRINTF((", new CONF 0x%02x", reg0));
reg0 264 dev/isa/viasio.c if ((reg0 & VT1211_HM_CONF_START) == 0) {
reg0 275 dev/isa/viasio.c reg0 = bus_space_read_1(sc->sc_iot, sc->sc_hm_ioh, VT1211_HM_PWMCS);
reg0 276 dev/isa/viasio.c sc->sc_hm_clock = vt1211_hm_clock[reg0 & 0x07];
reg0 277 dev/isa/viasio.c DPRINTF((", PWMCS 0x%02x, %dHz", reg0, sc->sc_hm_clock));
reg0 283 dev/isa/viasio.c reg0 = bus_space_read_1(sc->sc_iot, sc->sc_hm_ioh, VT1211_HM_UCHCONF);
reg0 284 dev/isa/viasio.c DPRINTF((", UCHCONF 0x%02x", reg0));
reg0 287 dev/isa/viasio.c if (VT1211_HM_UCHCONF_ISTEMP(reg0, i)) {
reg0 322 dev/isa/viasio.c u_int8_t reg0, reg1;
reg0 327 dev/isa/viasio.c reg0 = bus_space_read_1(sc->sc_iot, sc->sc_hm_ioh, VT1211_HM_TEMP1);
reg0 330 dev/isa/viasio.c val = (reg0 << 2) | reg1;
reg0 347 dev/isa/viasio.c reg0 = bus_space_read_1(sc->sc_iot, sc->sc_hm_ioh,
reg0 358 dev/isa/viasio.c val = (reg0 << 2) | reg1;
reg0 374 dev/isa/viasio.c reg0 = bus_space_read_1(sc->sc_iot, sc->sc_hm_ioh,
reg0 376 dev/isa/viasio.c val = reg0;
reg0 387 dev/isa/viasio.c reg0 = bus_space_read_1(sc->sc_iot, sc->sc_hm_ioh, VT1211_HM_33V);
reg0 388 dev/isa/viasio.c val = reg0;
reg0 397 dev/isa/viasio.c reg0 = bus_space_read_1(sc->sc_iot, sc->sc_hm_ioh, VT1211_HM_FAN1);
reg0 400 dev/isa/viasio.c val = reg0 << reg1;
reg0 413 dev/isa/viasio.c reg0 = bus_space_read_1(sc->sc_iot, sc->sc_hm_ioh, VT1211_HM_FAN2);
reg0 416 dev/isa/viasio.c val = reg0 << reg1;
reg0 434 dev/isa/viasio.c u_int8_t reg0, reg1;
reg0 446 dev/isa/viasio.c reg0 = viasio_conf_read(sc->sc_iot, sc->sc_ioh, VT1211_WDG_ACT);
reg0 447 dev/isa/viasio.c DPRINTF((": ACT 0x%02x", reg0));
reg0 448 dev/isa/viasio.c if ((reg0 & VT1211_WDG_ACT_EN) == 0) {
reg0 451 dev/isa/viasio.c reg0 |= VT1211_WDG_ACT_EN;
reg0 453 dev/isa/viasio.c VT1211_WDG_ACT, reg0);
reg0 454 dev/isa/viasio.c reg0 = viasio_conf_read(sc->sc_iot, sc->sc_ioh,
reg0 456 dev/isa/viasio.c DPRINTF((", new ACT 0x%02x", reg0));
reg0 457 dev/isa/viasio.c if ((reg0 & VT1211_WDG_ACT_EN) == 0) {
reg0 468 dev/isa/viasio.c reg0 = viasio_conf_read(sc->sc_iot, sc->sc_ioh, VT1211_WDG_ADDR_LSB);
reg0 470 dev/isa/viasio.c iobase = (reg1 << 8) | reg0;