root/dev/ic/smc83c170.c

DEFINITIONS

1. epic_attach
2. epic_shutdown
3. epic_start
4. epic_watchdog
5. epic_ioctl
6. epic_intr
7. epic_tick
8. epic_fixup_clock_source
9. epic_reset
10. epic_init
11. epic_rxdrain
12. epic_stop
13. epic_read_eeprom
14. epic_add_rxbuf
15. epic_set_mchash
16. epic_mii_wait
17. epic_mii_read
18. epic_mii_write
19. epic_statchg
20. epic_mediastatus
21. epic_mediachange

    1 /*      $OpenBSD: smc83c170.c,v 1.8 2006/03/25 22:41:43 djm Exp $       */
    2 /*      $NetBSD: smc83c170.c,v 1.59 2005/02/27 00:27:02 perry Exp $     */
    4 /*-
    5  * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
    6  * All rights reserved.
    7  *
    8  * This code is derived from software contributed to The NetBSD Foundation
    9  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
   10  * NASA Ames Research Center.
   11  *
   12  * Redistribution and use in source and binary forms, with or without
   13  * modification, are permitted provided that the following conditions
   14  * are met:
   15  * 1. Redistributions of source code must retain the above copyright
   16  *    notice, this list of conditions and the following disclaimer.
   17  * 2. Redistributions in binary form must reproduce the above copyright
   18  *    notice, this list of conditions and the following disclaimer in the
   19  *    documentation and/or other materials provided with the distribution.
   20  * 3. All advertising materials mentioning features or use of this software
   21  *    must display the following acknowledgement:
   22  *      This product includes software developed by the NetBSD
   23  *      Foundation, Inc. and its contributors.
   24  * 4. Neither the name of The NetBSD Foundation nor the names of its
   25  *    contributors may be used to endorse or promote products derived
   26  *    from this software without specific prior written permission.
   27  *
   28  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   29  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   30  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   31  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   32  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   33  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   34  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   35  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   36  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   37  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   38  * POSSIBILITY OF SUCH DAMAGE.
   39  */
   41 /*
   42  * Device driver for the Standard Microsystems Corp. 83C170
   43  * Ethernet PCI Integrated Controller (EPIC/100).
   44  */
   46 #if 0
   47 #include <sys/cdefs.h>
   48 __KERNEL_RCSID(0, "$NetBSD: smc83c170.c,v 1.59 2005/02/27 00:27:02 perry Exp $");
   49 #endif
   51 #include "bpfilter.h"
   53 #include <sys/param.h>
   54 #include <sys/systm.h>
   55 #include <sys/timeout.h>
   56 #include <sys/mbuf.h>
   57 #include <sys/malloc.h>
   58 #include <sys/kernel.h>
   59 #include <sys/socket.h>
   60 #include <sys/ioctl.h>
   61 #include <sys/errno.h>
   62 #include <sys/device.h>
   64 #include <net/if.h>
   65 #include <net/if_dl.h>
   67 #ifdef INET
   68 #include <netinet/in.h>
   69 #include <netinet/in_systm.h>
   70 #include <netinet/in_var.h>
   71 #include <netinet/ip.h>
   72 #include <netinet/if_ether.h>
   73 #endif
   75 #include <net/if_media.h>
   77 #if NBPFILTER > 0
   78 #include <net/bpf.h>
   79 #endif
   81 #include <machine/bus.h>
   82 #include <machine/intr.h>
   84 #include <dev/mii/miivar.h>
   85 #include <dev/mii/lxtphyreg.h>
   87 #include <dev/ic/smc83c170reg.h>
   88 #include <dev/ic/smc83c170var.h>
   90 void    epic_start(struct ifnet *);
   91 void    epic_watchdog(struct ifnet *);
   92 int     epic_ioctl(struct ifnet *, u_long, caddr_t);
   93 int     epic_init(struct ifnet *);
   94 void    epic_stop(struct ifnet *, int);
   96 void    epic_shutdown(void *);
   98 void    epic_reset(struct epic_softc *);
   99 void    epic_rxdrain(struct epic_softc *);
  100 int     epic_add_rxbuf(struct epic_softc *, int);
  101 void    epic_read_eeprom(struct epic_softc *, int, int, u_int16_t *);
  102 void    epic_set_mchash(struct epic_softc *);
  103 void    epic_fixup_clock_source(struct epic_softc *);
  104 int     epic_mii_read(struct device *, int, int);
  105 void    epic_mii_write(struct device *, int, int, int);
  106 int     epic_mii_wait(struct epic_softc *, u_int32_t);
  107 void    epic_tick(void *);
  109 void    epic_statchg(struct device *);
  110 int     epic_mediachange(struct ifnet *);
  111 void    epic_mediastatus(struct ifnet *, struct ifmediareq *);
  113 struct cfdriver epic_cd = {
  114         0, "epic", DV_IFNET
  115 };
  117 #define INTMASK (INTSTAT_FATAL_INT | INTSTAT_TXU | \
INTSTAT_TXC | INTSTAT_RXE | INTSTAT_RQE | INTSTAT_RCC)
  120 int     epic_copy_small = 0;
  122 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
  124 /*
  125  * Attach an EPIC interface to the system.
  126  */
  127 void
epic_attach(struct epic_softc *sc, const char *intrstr)
  129 {
bus_space_tag_t st = sc->sc_st;
bus_space_handle_t sh = sc->sc_sh;
  132         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
  133         int rseg, error, miiflags;
u_int i;
bus_dma_segment_t seg;
u_int8_t enaddr[ETHER_ADDR_LEN], devname[12 + 1];
u_int16_t myea[ETHER_ADDR_LEN / 2], mydevname[6];
  138         char *nullbuf;
timeout_set(&sc->sc_mii_timeout, epic_tick, sc);
  142         /*
  143          * Allocate the control data structures, and create and load the
  144          * DMA map for it.
  145          */
  146         if ((error = bus_dmamem_alloc(sc->sc_dmat,
  147             sizeof(struct epic_control_data) + ETHER_PAD_LEN, PAGE_SIZE, 0,
  148             &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
printf(": unable to allocate control data, error = %d\n",
error);
  151                 goto fail_0;
  152         }
  154         if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
  155             sizeof(struct epic_control_data) + ETHER_PAD_LEN,
  156             (caddr_t *)&sc->sc_control_data,
BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
printf(": unable to map control data, error = %d\n", error);
  159                 goto fail_1;
  160         }
nullbuf =
  162             (char *)sc->sc_control_data + sizeof(struct epic_control_data);
memset(nullbuf, 0, ETHER_PAD_LEN);
  165         if ((error = bus_dmamap_create(sc->sc_dmat,
  166             sizeof(struct epic_control_data), 1,
  167             sizeof(struct epic_control_data), 0, BUS_DMA_NOWAIT,
  168             &sc->sc_cddmamap)) != 0) {
printf(": unable to create control data DMA map, error = %d\n",
error);
  171                 goto fail_2;
  172         }
  174         if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap,
sc->sc_control_data, sizeof(struct epic_control_data), NULL,
BUS_DMA_NOWAIT)) != 0) {
printf(": unable to load control data DMA map, error = %d\n",
error);
  179                 goto fail_3;
  180         }
  182         /*
  183          * Create the transmit buffer DMA maps.
  184          */
  185         for (i = 0; i < EPIC_NTXDESC; i++) {
  186                 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
EPIC_NFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT,
  188                     &EPIC_DSTX(sc, i)->ds_dmamap)) != 0) {
printf(": unable to create tx DMA map %d, error = %d\n",
i, error);
  191                         goto fail_4;
  192                 }
  193         }
  195         /*
  196          * Create the receive buffer DMA maps.
  197          */
  198         for (i = 0; i < EPIC_NRXDESC; i++) {
  199                 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
MCLBYTES, 0, BUS_DMA_NOWAIT,
  201                     &EPIC_DSRX(sc, i)->ds_dmamap)) != 0) {
printf(": unable to create rx DMA map %d, error = %d\n",
i, error);
  204                         goto fail_5;
  205                 }
EPIC_DSRX(sc, i)->ds_mbuf = NULL;
  207         }
  209         /*
  210          * create and map the pad buffer
  211          */
  212         if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_PAD_LEN, 1,
ETHER_PAD_LEN, 0, BUS_DMA_NOWAIT,&sc->sc_nulldmamap)) != 0) {
printf(": unable to create pad buffer DMA map, error = %d\n",
error);
  216                 goto fail_5;
  217         }
  219         if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_nulldmamap,
nullbuf, ETHER_PAD_LEN, NULL, BUS_DMA_NOWAIT)) != 0) {
printf(": unable to load pad buffer DMA map, error = %d\n",
error);
  223                 goto fail_6;
  224         }
bus_dmamap_sync(sc->sc_dmat, sc->sc_nulldmamap, 0, ETHER_PAD_LEN,
BUS_DMASYNC_PREWRITE);
  228         /*
  229          * Bring the chip out of low-power mode and reset it to a known state.
  230          */
bus_space_write_4(st, sh, EPIC_GENCTL, 0);
epic_reset(sc);
  234         /*
  235          * Read the Ethernet address from the EEPROM.
  236          */
epic_read_eeprom(sc, 0, (sizeof(myea) / sizeof(myea[0])), myea);
  238         for (i = 0; i < sizeof(myea)/ sizeof(myea[0]); i++) {
enaddr[i * 2]     = myea[i] & 0xff;
enaddr[i * 2 + 1] = myea[i] >> 8;
  241         }
  243         /*
  244          * ...and the device name.
  245          */
epic_read_eeprom(sc, 0x2c, (sizeof(mydevname) / sizeof(mydevname[0])),
mydevname);
  248         for (i = 0; i < sizeof(mydevname) / sizeof(mydevname[0]); i++) {
devname[i * 2]     = mydevname[i] & 0xff;
devname[i * 2 + 1] = mydevname[i] >> 8;
  251         }
devname[sizeof(devname) - 1] = ' ';
  254         for (i = sizeof(devname) - 1; devname[i] == ' '; i--) {
devname[i] = '\0';
  256                 if (i == 0)
  257                         break;
  258         }
printf(", %s : %s, address %s\n", devname, intrstr,
ether_sprintf(enaddr));
miiflags = 0;
  264         if (sc->sc_hwflags & EPIC_HAS_MII_FIBER)
miiflags |= MIIF_HAVEFIBER;
  267         /*
  268          * Initialize our media structures and probe the MII.
  269          */
sc->sc_mii.mii_ifp = ifp;
sc->sc_mii.mii_readreg = epic_mii_read;
sc->sc_mii.mii_writereg = epic_mii_write;
sc->sc_mii.mii_statchg = epic_statchg;
ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, epic_mediachange,
epic_mediastatus);
mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
MII_OFFSET_ANY, miiflags);
  278         if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
  281         } else
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
  284         if (sc->sc_hwflags & EPIC_HAS_BNC) {
  285                 /* use the next free media instance */
sc->sc_serinst = sc->sc_mii.mii_instance++;
ifmedia_add(&sc->sc_mii.mii_media,
IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0,
sc->sc_serinst),
  290                             0, NULL);
  291         } else
sc->sc_serinst = -1;
bcopy(enaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN);
bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
ifp->if_softc = sc;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_ioctl = epic_ioctl;
ifp->if_start = epic_start;
ifp->if_watchdog = epic_watchdog;
IFQ_SET_MAXLEN(&ifp->if_snd, EPIC_NTXDESC - 1);
IFQ_SET_READY(&ifp->if_snd);
ifp->if_capabilities = IFCAP_VLAN_MTU;
  306         /*
  307          * Attach the interface.
  308          */
if_attach(ifp);
ether_ifattach(ifp);
  312         /*
  313          * Make sure the interface is shutdown during reboot.
  314          */
sc->sc_sdhook = shutdownhook_establish(epic_shutdown, sc);
  316         if (sc->sc_sdhook == NULL)
printf("%s: WARNING: unable to establish shutdown hook\n",
sc->sc_dev.dv_xname);
  319         return;
  321         /*
  322          * Free any resources we've allocated during the failed attach
  323          * attempt.  Do this in reverse order and fall through.
  324          */
fail_6:
bus_dmamap_destroy(sc->sc_dmat, sc->sc_nulldmamap);
fail_5:
  328         for (i = 0; i < EPIC_NRXDESC; i++) {
  329                 if (EPIC_DSRX(sc, i)->ds_dmamap != NULL)
bus_dmamap_destroy(sc->sc_dmat,
EPIC_DSRX(sc, i)->ds_dmamap);
  332         }
fail_4:
  334         for (i = 0; i < EPIC_NTXDESC; i++) {
  335                 if (EPIC_DSTX(sc, i)->ds_dmamap != NULL)
bus_dmamap_destroy(sc->sc_dmat,
EPIC_DSTX(sc, i)->ds_dmamap);
  338         }
bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
fail_3:
bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
fail_2:
bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data,
  344             sizeof(struct epic_control_data));
fail_1:
bus_dmamem_free(sc->sc_dmat, &seg, rseg);
fail_0:
  348         return;
  349 }
  351 /*
  352  * Shutdown hook.  Make sure the interface is stopped at reboot.
  353  */
  354 void
epic_shutdown(void *arg)
  356 {
  357         struct epic_softc *sc = arg;
epic_stop(&sc->sc_arpcom.ac_if, 1);
  360 }
  362 /*
  363  * Start packet transmission on the interface.
  364  * [ifnet interface function]
  365  */
  366 void
epic_start(struct ifnet *ifp)
  368 {
  369         struct epic_softc *sc = ifp->if_softc;
  370         struct mbuf *m0, *m;
  371         struct epic_txdesc *txd;
  372         struct epic_descsoft *ds;
  373         struct epic_fraglist *fr;
bus_dmamap_t dmamap;
  375         int error, firsttx, nexttx, opending, seg;
u_int len;
  378         /*
  379          * Remember the previous txpending and the first transmit
  380          * descriptor we use.
  381          */
opending = sc->sc_txpending;
firsttx = EPIC_NEXTTX(sc->sc_txlast);
  385         /*
  386          * Loop through the send queue, setting up transmit descriptors
  387          * until we drain the queue, or use up all available transmit
  388          * descriptors.
  389          */
  390         while (sc->sc_txpending < EPIC_NTXDESC) {
  391                 /*
  392                  * Grab a packet off the queue.
  393                  */
IFQ_POLL(&ifp->if_snd, m0);
  395                 if (m0 == NULL)
  396                         break;
m = NULL;
  399                 /*
  400                  * Get the last and next available transmit descriptor.
  401                  */
nexttx = EPIC_NEXTTX(sc->sc_txlast);
txd = EPIC_CDTX(sc, nexttx);
fr = EPIC_CDFL(sc, nexttx);
ds = EPIC_DSTX(sc, nexttx);
dmamap = ds->ds_dmamap;
  408                 /*
  409                  * Load the DMA map.  If this fails, the packet either
  410                  * didn't fit in the alloted number of frags, or we were
  411                  * short on resources.  In this case, we'll copy and try
  412                  * again.
  413                  */
  414                 if ((error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 ||
  416                     (m0->m_pkthdr.len < ETHER_PAD_LEN &&
dmamap-> dm_nsegs == EPIC_NFRAGS)) {
  418                         if (error == 0)
bus_dmamap_unload(sc->sc_dmat, dmamap);
MGETHDR(m, M_DONTWAIT, MT_DATA);
  422                         if (m == NULL)
  423                                 break;
  424                         if (m0->m_pkthdr.len > MHLEN) {
MCLGET(m, M_DONTWAIT);
  426                                 if ((m->m_flags & M_EXT) == 0) {
m_freem(m);
  428                                         break;
  429                                 }
  430                         }
m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t));
m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap,
m, BUS_DMA_WRITE|BUS_DMA_NOWAIT);
  435                         if (error)
  436                                 break;
  437                 }
IFQ_DEQUEUE(&ifp->if_snd, m0);
  439                 if (m != NULL) {
m_freem(m0);
m0 = m;
  442                 }
  444                 /* Initialize the fraglist. */
  445                 for (seg = 0; seg < dmamap->dm_nsegs; seg++) {
fr->ef_frags[seg].ef_addr =
dmamap->dm_segs[seg].ds_addr;
fr->ef_frags[seg].ef_length =
dmamap->dm_segs[seg].ds_len;
  450                 }
len = m0->m_pkthdr.len;
  452                 if (len < ETHER_PAD_LEN) {
fr->ef_frags[seg].ef_addr = sc->sc_nulldma;
fr->ef_frags[seg].ef_length = ETHER_PAD_LEN - len;
len = ETHER_PAD_LEN;
seg++;
  457                 }
fr->ef_nfrags = seg;
EPIC_CDFLSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE);
  462                 /* Sync the DMA map. */
bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
BUS_DMASYNC_PREWRITE);
  466                 /*
  467                  * Store a pointer to the packet so we can free it later.
  468                  */
ds->ds_mbuf = m0;
  471                 /*
  472                  * Fill in the transmit descriptor.
  473                  */
txd->et_control = ET_TXCTL_LASTDESC | ET_TXCTL_FRAGLIST;
  476                 /*
  477                  * If this is the first descriptor we're enqueueing,
  478                  * don't give it to the EPIC yet.  That could cause
  479                  * a race condition.  We'll do it below.
  480                  */
  481                 if (nexttx == firsttx)
txd->et_txstatus = TXSTAT_TXLENGTH(len);
  483                 else
txd->et_txstatus =
TXSTAT_TXLENGTH(len) | ET_TXSTAT_OWNER;
EPIC_CDTXSYNC(sc, nexttx,
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
  490                 /* Advance the tx pointer. */
sc->sc_txpending++;
sc->sc_txlast = nexttx;
  494 #if NBPFILTER > 0
  495                 /*
  496                  * Pass the packet to any BPF listeners.
  497                  */
  498                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_OUT);
  500 #endif
  501         }
  503         if (sc->sc_txpending == EPIC_NTXDESC) {
  504                 /* No more slots left; notify upper layer. */
ifp->if_flags |= IFF_OACTIVE;
  506         }
  508         if (sc->sc_txpending != opending) {
  509                 /*
  510                  * We enqueued packets.  If the transmitter was idle,
  511                  * reset the txdirty pointer.
  512                  */
  513                 if (opending == 0)
sc->sc_txdirty = firsttx;
  516                 /*
  517                  * Cause a transmit interrupt to happen on the
  518                  * last packet we enqueued.
  519                  */
EPIC_CDTX(sc, sc->sc_txlast)->et_control |= ET_TXCTL_IAF;
EPIC_CDTXSYNC(sc, sc->sc_txlast,
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
  524                 /*
  525                  * The entire packet chain is set up.  Give the
  526                  * first descriptor to the EPIC now.
  527                  */
EPIC_CDTX(sc, firsttx)->et_txstatus |= ET_TXSTAT_OWNER;
EPIC_CDTXSYNC(sc, firsttx,
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
  532                 /* Start the transmitter. */
bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND,
COMMAND_TXQUEUED);
  536                 /* Set a watchdog timer in case the chip flakes out. */
ifp->if_timer = 5;
  538         }
  539 }
  541 /*
  542  * Watchdog timer handler.
  543  * [ifnet interface function]
  544  */
  545 void
epic_watchdog(struct ifnet *ifp)
  547 {
  548         struct epic_softc *sc = ifp->if_softc;
printf("%s: device timeout\n", sc->sc_dev.dv_xname);
ifp->if_oerrors++;
  553         (void) epic_init(ifp);
  554 }
  556 /*
  557  * Handle control requests from the operator.
  558  * [ifnet interface function]
  559  */
  560 int
epic_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
  562 {
  563         struct epic_softc *sc = ifp->if_softc;
  564         struct ifreq *ifr = (struct ifreq *)data;
  565         struct ifaddr *ifa = (struct ifaddr *)data;
  566         int s, error;
s = splnet();
  570         if ((error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data)) > 0) {
splx(s);
  572                 return (error);
  573         }
  575         switch (cmd) {
  576         case SIOCSIFADDR:
ifp->if_flags |= IFF_UP;
  579                 switch (ifa->ifa_addr->sa_family) {
  580 #ifdef INET
  581                 case AF_INET:
epic_init(ifp);
arp_ifinit(&sc->sc_arpcom, ifa);
  584                         break;
  585 #endif
  586                 default:
epic_init(ifp);
  588                         break;
  589                 }
  590                 break;
  592         case SIOCSIFMTU:
  593                 if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN)
error = EINVAL;
  595                 else if (ifp->if_mtu != ifr->ifr_mtu)
ifp->if_mtu = ifr->ifr_mtu;
  597                 break;
  599         case SIOCSIFFLAGS:
  600                 /*
  601                  * If interface is marked up and not running, then start it.
  602                  * If it is marked down and running, stop it.
  603                  * XXX If it's up then re-initialize it. This is so flags
  604                  * such as IFF_PROMISC are handled.
  605                  */
  606                 if (ifp->if_flags & IFF_UP)
epic_init(ifp);
  608                 else if (ifp->if_flags & IFF_RUNNING)
epic_stop(ifp, 1);
  610                 break;
  612         case SIOCADDMULTI:
  613         case SIOCDELMULTI:
error = (cmd == SIOCADDMULTI) ?
ether_addmulti(ifr, &sc->sc_arpcom) :
ether_delmulti(ifr, &sc->sc_arpcom);
  618                 if (error == ENETRESET) {
  619                         /*
  620                          * Multicast list has changed; set the hardware
  621                          * filter accordingly.
  622                          */
  623                         if (ifp->if_flags & IFF_RUNNING) {
mii_pollstat(&sc->sc_mii);
epic_set_mchash(sc);
  626                         }
error = 0;
  628                 }
  629                 break;
  631         case SIOCSIFMEDIA:
  632         case SIOCGIFMEDIA:
error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
  634                 break;
  636         default:
error = EINVAL;
  638         }
splx(s);
  640         return (error);
  641 }
  643 /*
  644  * Interrupt handler.
  645  */
  646 int
epic_intr(void *arg)
  648 {
  649         struct epic_softc *sc = arg;
  650         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
  651         struct epic_rxdesc *rxd;
  652         struct epic_txdesc *txd;
  653         struct epic_descsoft *ds;
  654         struct mbuf *m;
u_int32_t intstat, rxstatus, txstatus;
  656         int i, claimed = 0;
u_int len;
top:
  660         /*
  661          * Get the interrupt status from the EPIC.
  662          */
intstat = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT);
  664         if ((intstat & INTSTAT_INT_ACTV) == 0)
  665                 return (claimed);
claimed = 1;
  669         /*
  670          * Acknowledge the interrupt.
  671          */
bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT,
intstat & INTMASK);
  675         /*
  676          * Check for receive interrupts.
  677          */
  678         if (intstat & (INTSTAT_RCC | INTSTAT_RXE | INTSTAT_RQE)) {
  679                 for (i = sc->sc_rxptr;; i = EPIC_NEXTRX(i)) {
rxd = EPIC_CDRX(sc, i);
ds = EPIC_DSRX(sc, i);
EPIC_CDRXSYNC(sc, i,
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
rxstatus = rxd->er_rxstatus;
  687                         if (rxstatus & ER_RXSTAT_OWNER) {
  688                                 /*
  689                                  * We have processed all of the
  690                                  * receive buffers.
  691                                  */
  692                                 break;
  693                         }
  695                         /*
  696                          * Make sure the packet arrived intact.  If an error
  697                          * occurred, update stats and reset the descriptor.
  698                          * The buffer will be reused the next time the
  699                          * descriptor comes up in the ring.
  700                          */
  701                         if ((rxstatus & ER_RXSTAT_PKTINTACT) == 0) {
  702                                 if (rxstatus & ER_RXSTAT_CRCERROR)
printf("%s: CRC error\n",
sc->sc_dev.dv_xname);
  705                                 if (rxstatus & ER_RXSTAT_ALIGNERROR)
printf("%s: alignment error\n",
sc->sc_dev.dv_xname);
ifp->if_ierrors++;
EPIC_INIT_RXDESC(sc, i);
  710                                 continue;
  711                         }
bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
  716                         /*
  717                          * The EPIC includes the CRC with every packet;
  718                          * trim it.
  719                          */
len = RXSTAT_RXLENGTH(rxstatus) - ETHER_CRC_LEN;
  722                         if (len < sizeof(struct ether_header)) {
  723                                 /*
  724                                  * Runt packet; drop it now.
  725                                  */
ifp->if_ierrors++;
EPIC_INIT_RXDESC(sc, i);
bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
ds->ds_dmamap->dm_mapsize,
BUS_DMASYNC_PREREAD);
  731                                 continue;
  732                         }
  734                         /*
  735                          * If the packet is small enough to fit in a
  736                          * single header mbuf, allocate one and copy
  737                          * the data into it.  This greatly reduces
  738                          * memory consumption when we receive lots
  739                          * of small packets.
  740                          *
  741                          * Otherwise, we add a new buffer to the receive
  742                          * chain.  If this fails, we drop the packet and
  743                          * recycle the old buffer.
  744                          */
  745                         if (epic_copy_small != 0 && len <= MHLEN) {
MGETHDR(m, M_DONTWAIT, MT_DATA);
  747                                 if (m == NULL)
  748                                         goto dropit;
memcpy(mtod(m, caddr_t),
mtod(ds->ds_mbuf, caddr_t), len);
EPIC_INIT_RXDESC(sc, i);
bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
ds->ds_dmamap->dm_mapsize,
BUS_DMASYNC_PREREAD);
  755                         } else {
m = ds->ds_mbuf;
  757                                 if (epic_add_rxbuf(sc, i) != 0) {
dropit:
ifp->if_ierrors++;
EPIC_INIT_RXDESC(sc, i);
bus_dmamap_sync(sc->sc_dmat,
ds->ds_dmamap, 0,
ds->ds_dmamap->dm_mapsize,
BUS_DMASYNC_PREREAD);
  765                                         continue;
  766                                 }
  767                         }
m->m_pkthdr.rcvif = ifp;
m->m_pkthdr.len = m->m_len = len;
  772 #if NBPFILTER > 0
  773                         /*
  774                          * Pass this up to any BPF listeners, but only
  775                          * pass it up the stack if its for us.
  776                          */
  777                         if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN);
  779 #endif
  781                         /* Pass it on. */
ether_input_mbuf(ifp, m);
ifp->if_ipackets++;
  784                 }
  786                 /* Update the receive pointer. */
sc->sc_rxptr = i;
  789                 /*
  790                  * Check for receive queue underflow.
  791                  */
  792                 if (intstat & INTSTAT_RQE) {
printf("%s: receiver queue empty\n",
sc->sc_dev.dv_xname);
  795                         /*
  796                          * Ring is already built; just restart the
  797                          * receiver.
  798                          */
bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_PRCDAR,
EPIC_CDRXADDR(sc, sc->sc_rxptr));
bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND,
COMMAND_RXQUEUED | COMMAND_START_RX);
  803                 }
  804         }
  806         /*
  807          * Check for transmission complete interrupts.
  808          */
  809         if (intstat & (INTSTAT_TXC | INTSTAT_TXU)) {
ifp->if_flags &= ~IFF_OACTIVE;
  811                 for (i = sc->sc_txdirty; sc->sc_txpending != 0;
i = EPIC_NEXTTX(i), sc->sc_txpending--) {
txd = EPIC_CDTX(sc, i);
ds = EPIC_DSTX(sc, i);
EPIC_CDTXSYNC(sc, i,
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
txstatus = txd->et_txstatus;
  820                         if (txstatus & ET_TXSTAT_OWNER)
  821                                 break;
EPIC_CDFLSYNC(sc, i, BUS_DMASYNC_POSTWRITE);
bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap,
  826                             0, ds->ds_dmamap->dm_mapsize,
BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
m_freem(ds->ds_mbuf);
ds->ds_mbuf = NULL;
  832                         /*
  833                          * Check for errors and collisions.
  834                          */
  835                         if ((txstatus & ET_TXSTAT_PACKETTX) == 0)
ifp->if_oerrors++;
  837                         else
ifp->if_opackets++;
ifp->if_collisions +=
TXSTAT_COLLISIONS(txstatus);
  841                         if (txstatus & ET_TXSTAT_CARSENSELOST)
printf("%s: lost carrier\n",
sc->sc_dev.dv_xname);
  844                 }
  846                 /* Update the dirty transmit buffer pointer. */
sc->sc_txdirty = i;
  849                 /*
  850                  * Cancel the watchdog timer if there are no pending
  851                  * transmissions.
  852                  */
  853                 if (sc->sc_txpending == 0)
ifp->if_timer = 0;
  856                 /*
  857                  * Kick the transmitter after a DMA underrun.
  858                  */
  859                 if (intstat & INTSTAT_TXU) {
printf("%s: transmit underrun\n", sc->sc_dev.dv_xname);
bus_space_write_4(sc->sc_st, sc->sc_sh,
EPIC_COMMAND, COMMAND_TXUGO);
  863                         if (sc->sc_txpending)
bus_space_write_4(sc->sc_st, sc->sc_sh,
EPIC_COMMAND, COMMAND_TXQUEUED);
  866                 }
  868                 /*
  869                  * Try to get more packets going.
  870                  */
epic_start(ifp);
  872         }
  874         /*
  875          * Check for fatal interrupts.
  876          */
  877         if (intstat & INTSTAT_FATAL_INT) {
  878                 if (intstat & INTSTAT_PTA)
printf("%s: PCI target abort error\n",
sc->sc_dev.dv_xname);
  881                 else if (intstat & INTSTAT_PMA)
printf("%s: PCI master abort error\n",
sc->sc_dev.dv_xname);
  884                 else if (intstat & INTSTAT_APE)
printf("%s: PCI address parity error\n",
sc->sc_dev.dv_xname);
  887                 else if (intstat & INTSTAT_DPE)
printf("%s: PCI data parity error\n",
sc->sc_dev.dv_xname);
  890                 else
printf("%s: unknown fatal error\n",
sc->sc_dev.dv_xname);
  893                 (void) epic_init(ifp);
  894         }
  896         /*
  897          * Check for more interrupts.
  898          */
  899         goto top;
  900 }
  902 /*
  903  * One second timer, used to tick the MII.
  904  */
  905 void
epic_tick(void *arg)
  907 {
  908         struct epic_softc *sc = arg;
  909         int s;
s = splnet();
mii_tick(&sc->sc_mii);
splx(s);
timeout_add(&sc->sc_mii_timeout, hz);
  916 }
  918 /*
  919  * Fixup the clock source on the EPIC.
  920  */
  921 void
epic_fixup_clock_source(struct epic_softc *sc)
  923 {
  924         int i;
  926         /*
  927          * According to SMC Application Note 7-15, the EPIC's clock
  928          * source is incorrect following a reset.  This manifests itself
  929          * as failure to recognize when host software has written to
  930          * a register on the EPIC.  The appnote recommends issuing at
  931          * least 16 consecutive writes to the CLOCK TEST bit to correctly
  932          * configure the clock source.
  933          */
  934         for (i = 0; i < 16; i++)
bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TEST,
TEST_CLOCKTEST);
  937 }
  939 /*
  940  * Perform a soft reset on the EPIC.
  941  */
  942 void
epic_reset(struct epic_softc *sc)
  944 {
epic_fixup_clock_source(sc);
bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, 0);
delay(100);
bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, GENCTL_SOFTRESET);
delay(100);
epic_fixup_clock_source(sc);
  954 }
  956 /*
  957  * Initialize the interface.  Must be called at splnet().
  958  */
  959 int
epic_init(struct ifnet *ifp)
  961 {
  962         struct epic_softc *sc = ifp->if_softc;
bus_space_tag_t st = sc->sc_st;
bus_space_handle_t sh = sc->sc_sh;
  965         struct epic_txdesc *txd;
  966         struct epic_descsoft *ds;
u_int32_t genctl, reg0;
  968         int i, error = 0;
  970         /*
  971          * Cancel any pending I/O.
  972          */
epic_stop(ifp, 0);
  975         /*
  976          * Reset the EPIC to a known state.
  977          */
epic_reset(sc);
  980         /*
  981          * Magical mystery initialization.
  982          */
bus_space_write_4(st, sh, EPIC_TXTEST, 0);
  985         /*
  986          * Initialize the EPIC genctl register:
  987          *
  988          *      - 64 byte receive FIFO threshold
  989          *      - automatic advance to next receive frame
  990          */
genctl = GENCTL_RX_FIFO_THRESH0 | GENCTL_ONECOPY;
  992 #if BYTE_ORDER == BIG_ENDIAN
genctl |= GENCTL_BIG_ENDIAN;
  994 #endif
bus_space_write_4(st, sh, EPIC_GENCTL, genctl);
  997         /*
  998          * Reset the MII bus and PHY.
  999          */
reg0 = bus_space_read_4(st, sh, EPIC_NVCTL);
bus_space_write_4(st, sh, EPIC_NVCTL, reg0 | NVCTL_GPIO1 | NVCTL_GPOE1);
bus_space_write_4(st, sh, EPIC_MIICFG, MIICFG_ENASER);
bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_RESET_PHY);
delay(100);
bus_space_write_4(st, sh, EPIC_GENCTL, genctl);
delay(1000);
bus_space_write_4(st, sh, EPIC_NVCTL, reg0);
 1009         /*
 1010          * Initialize Ethernet address.
 1011          */
reg0 = sc->sc_arpcom.ac_enaddr[1] << 8 | sc->sc_arpcom.ac_enaddr[0];
bus_space_write_4(st, sh, EPIC_LAN0, reg0);
reg0 = sc->sc_arpcom.ac_enaddr[3] << 8 | sc->sc_arpcom.ac_enaddr[2];
bus_space_write_4(st, sh, EPIC_LAN1, reg0);
reg0 = sc->sc_arpcom.ac_enaddr[5] << 8 | sc->sc_arpcom.ac_enaddr[4];
bus_space_write_4(st, sh, EPIC_LAN2, reg0);
 1019         /*
 1020          * Initialize receive control.  Remember the external buffer
 1021          * size setting.
 1022          */
reg0 = bus_space_read_4(st, sh, EPIC_RXCON) &
 1024             (RXCON_EXTBUFSIZESEL1 | RXCON_EXTBUFSIZESEL0);
reg0 |= (RXCON_RXMULTICAST | RXCON_RXBROADCAST);
 1026         if (ifp->if_flags & IFF_PROMISC)
reg0 |= RXCON_PROMISCMODE;
bus_space_write_4(st, sh, EPIC_RXCON, reg0);
 1030         /* Set the current media. */
epic_mediachange(ifp);
 1033         /* Set up the multicast hash table. */
epic_set_mchash(sc);
 1036         /*
 1037          * Initialize the transmit descriptor ring.  txlast is initialized
 1038          * to the end of the list so that it will wrap around to the first
 1039          * descriptor when the first packet is transmitted.
 1040          */
 1041         for (i = 0; i < EPIC_NTXDESC; i++) {
txd = EPIC_CDTX(sc, i);
memset(txd, 0, sizeof(struct epic_txdesc));
txd->et_bufaddr = EPIC_CDFLADDR(sc, i);
txd->et_nextdesc = EPIC_CDTXADDR(sc, EPIC_NEXTTX(i));
EPIC_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 1047         }
sc->sc_txpending = 0;
sc->sc_txdirty = 0;
sc->sc_txlast = EPIC_NTXDESC - 1;
 1052         /*
 1053          * Initialize the receive descriptor ring.
 1054          */
 1055         for (i = 0; i < EPIC_NRXDESC; i++) {
ds = EPIC_DSRX(sc, i);
 1057                 if (ds->ds_mbuf == NULL) {
 1058                         if ((error = epic_add_rxbuf(sc, i)) != 0) {
printf("%s: unable to allocate or map rx "
 1060                                     "buffer %d error = %d\n",
sc->sc_dev.dv_xname, i, error);
 1062                                 /*
 1063                                  * XXX Should attempt to run with fewer receive
 1064                                  * XXX buffers instead of just failing.
 1065                                  */
epic_rxdrain(sc);
 1067                                 goto out;
 1068                         }
 1069                 } else
EPIC_INIT_RXDESC(sc, i);
 1071         }
sc->sc_rxptr = 0;
 1074         /*
 1075          * Initialize the interrupt mask and enable interrupts.
 1076          */
bus_space_write_4(st, sh, EPIC_INTMASK, INTMASK);
bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_INTENA);
 1080         /*
 1081          * Give the transmit and receive rings to the EPIC.
 1082          */
bus_space_write_4(st, sh, EPIC_PTCDAR,
EPIC_CDTXADDR(sc, EPIC_NEXTTX(sc->sc_txlast)));
bus_space_write_4(st, sh, EPIC_PRCDAR,
EPIC_CDRXADDR(sc, sc->sc_rxptr));
 1088         /*
 1089          * Set the EPIC in motion.
 1090          */
bus_space_write_4(st, sh, EPIC_COMMAND,
COMMAND_RXQUEUED | COMMAND_START_RX);
 1094         /*
 1095          * ...all done!
 1096          */
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
 1100         /*
 1101          * Start the one second clock.
 1102          */
timeout_add(&sc->sc_mii_timeout, hz);
 1105         /*
 1106          * Attempt to start output on the interface.
 1107          */
epic_start(ifp);
out:
 1111         if (error)
printf("%s: interface not running\n", sc->sc_dev.dv_xname);
 1113         return (error);
 1114 }
 1116 /*
 1117  * Drain the receive queue.
 1118  */
 1119 void
epic_rxdrain(struct epic_softc *sc)
 1121 {
 1122         struct epic_descsoft *ds;
 1123         int i;
 1125         for (i = 0; i < EPIC_NRXDESC; i++) {
ds = EPIC_DSRX(sc, i);
 1127                 if (ds->ds_mbuf != NULL) {
bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
m_freem(ds->ds_mbuf);
ds->ds_mbuf = NULL;
 1131                 }
 1132         }
 1133 }
 1135 /*
 1136  * Stop transmission on the interface.
 1137  */
 1138 void
epic_stop(struct ifnet *ifp, int disable)
 1140 {
 1141         struct epic_softc *sc = ifp->if_softc;
bus_space_tag_t st = sc->sc_st;
bus_space_handle_t sh = sc->sc_sh;
 1144         struct epic_descsoft *ds;
u_int32_t reg;
 1146         int i;
 1148         /*
 1149          * Stop the one second clock.
 1150          */
timeout_del(&sc->sc_mii_timeout);
 1153         /*
 1154          * Mark the interface down and cancel the watchdog timer.
 1155          */
ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
ifp->if_timer = 0;
 1159         /* Down the MII. */
mii_down(&sc->sc_mii);
 1162         /* Paranoia... */
epic_fixup_clock_source(sc);
 1165         /*
 1166          * Disable interrupts.
 1167          */
reg = bus_space_read_4(st, sh, EPIC_GENCTL);
bus_space_write_4(st, sh, EPIC_GENCTL, reg & ~GENCTL_INTENA);
bus_space_write_4(st, sh, EPIC_INTMASK, 0);
 1172         /*
 1173          * Stop the DMA engine and take the receiver off-line.
 1174          */
bus_space_write_4(st, sh, EPIC_COMMAND, COMMAND_STOP_RDMA |
COMMAND_STOP_TDMA | COMMAND_STOP_RX);
 1178         /*
 1179          * Release any queued transmit buffers.
 1180          */
 1181         for (i = 0; i < EPIC_NTXDESC; i++) {
ds = EPIC_DSTX(sc, i);
 1183                 if (ds->ds_mbuf != NULL) {
bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
m_freem(ds->ds_mbuf);
ds->ds_mbuf = NULL;
 1187                 }
 1188         }
 1190         if (disable)
epic_rxdrain(sc);
 1192 }
 1194 /*
 1195  * Read the EPIC Serial EEPROM.
 1196  */
 1197 void
epic_read_eeprom(struct epic_softc *sc, int word, int wordcnt, u_int16_t *data)
 1199 {
bus_space_tag_t st = sc->sc_st;
bus_space_handle_t sh = sc->sc_sh;
u_int16_t reg;
 1203         int i, x;
 1205 #define EEPROM_WAIT_READY(st, sh) \
 1206         while ((bus_space_read_4((st), (sh), EPIC_EECTL) & EECTL_EERDY) == 0) \
 1207                 /* nothing */
 1209         /*
 1210          * Enable the EEPROM.
 1211          */
bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE);
EEPROM_WAIT_READY(st, sh);
 1215         for (i = 0; i < wordcnt; i++) {
 1216                 /* Send CHIP SELECT for one clock tick. */
bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE|EECTL_EECS);
EEPROM_WAIT_READY(st, sh);
 1220                 /* Shift in the READ opcode. */
 1221                 for (x = 3; x > 0; x--) {
reg = EECTL_ENABLE|EECTL_EECS;
 1223                         if (EPIC_EEPROM_OPC_READ & (1 << (x - 1)))
reg |= EECTL_EEDI;
bus_space_write_4(st, sh, EPIC_EECTL, reg);
EEPROM_WAIT_READY(st, sh);
bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK);
EEPROM_WAIT_READY(st, sh);
bus_space_write_4(st, sh, EPIC_EECTL, reg);
EEPROM_WAIT_READY(st, sh);
 1231                 }
 1233                 /* Shift in address. */
 1234                 for (x = 6; x > 0; x--) {
reg = EECTL_ENABLE|EECTL_EECS;
 1236                         if ((word + i) & (1 << (x - 1)))
reg |= EECTL_EEDI;
bus_space_write_4(st, sh, EPIC_EECTL, reg);
EEPROM_WAIT_READY(st, sh);
bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK);
EEPROM_WAIT_READY(st, sh);
bus_space_write_4(st, sh, EPIC_EECTL, reg);
EEPROM_WAIT_READY(st, sh);
 1244                 }
 1246                 /* Shift out data. */
reg = EECTL_ENABLE|EECTL_EECS;
data[i] = 0;
 1249                 for (x = 16; x > 0; x--) {
bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK);
EEPROM_WAIT_READY(st, sh);
 1252                         if (bus_space_read_4(st, sh, EPIC_EECTL) & EECTL_EEDO)
data[i] |= (1 << (x - 1));
bus_space_write_4(st, sh, EPIC_EECTL, reg);
EEPROM_WAIT_READY(st, sh);
 1256                 }
 1258                 /* Clear CHIP SELECT. */
bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE);
EEPROM_WAIT_READY(st, sh);
 1261         }
 1263         /*
 1264          * Disable the EEPROM.
 1265          */
bus_space_write_4(st, sh, EPIC_EECTL, 0);
 1268 #undef EEPROM_WAIT_READY
 1269 }
 1271 /*
 1272  * Add a receive buffer to the indicated descriptor.
 1273  */
 1274 int
epic_add_rxbuf(struct epic_softc *sc, int idx)
 1276 {
 1277         struct epic_descsoft *ds = EPIC_DSRX(sc, idx);
 1278         struct mbuf *m;
 1279         int error;
MGETHDR(m, M_DONTWAIT, MT_DATA);
 1282         if (m == NULL)
 1283                 return (ENOBUFS);
MCLGET(m, M_DONTWAIT);
 1286         if ((m->m_flags & M_EXT) == 0) {
m_freem(m);
 1288                 return (ENOBUFS);
 1289         }
 1291         if (ds->ds_mbuf != NULL)
bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
ds->ds_mbuf = m;
error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap,
m->m_ext.ext_buf, m->m_ext.ext_size, NULL,
BUS_DMA_READ|BUS_DMA_NOWAIT);
 1299         if (error) {
printf("%s: can't load rx DMA map %d, error = %d\n",
sc->sc_dev.dv_xname, idx, error);
panic("epic_add_rxbuf");        /* XXX */
 1303         }
bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
EPIC_INIT_RXDESC(sc, idx);
 1310         return (0);
 1311 }
 1313 /*
 1314  * Set the EPIC multicast hash table.
 1315  *
 1316  * NOTE: We rely on a recently-updated mii_media_active here!
 1317  */
 1318 void
epic_set_mchash(struct epic_softc *sc)
 1320 {
 1321         struct arpcom *ac = &sc->sc_arpcom;
 1322         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
 1323         struct ether_multi *enm;
 1324         struct ether_multistep step;
u_int32_t hash, mchash[4];
 1327         /*
 1328          * Set up the multicast address filter by passing all multicast
 1329          * addresses through a CRC generator, and then using the low-order
 1330          * 6 bits as an index into the 64 bit multicast hash table (only
 1331          * the lower 16 bits of each 32 bit multicast hash register are
 1332          * valid).  The high order bits select the register, while the
 1333          * rest of the bits select the bit within the register.
 1334          */
 1336         if (ifp->if_flags & IFF_PROMISC)
 1337                 goto allmulti;
 1339         if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_10_T) {
 1340                 /* XXX hardware bug in 10Mbps mode. */
 1341                 goto allmulti;
 1342         }
mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0;
ETHER_FIRST_MULTI(step, ac, enm);
 1347         while (enm != NULL) {
 1348                 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN))
 1349                         goto allmulti;
hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN);
hash >>= 26;
 1354                 /* Set the corresponding bit in the hash table. */
mchash[hash >> 4] |= 1 << (hash & 0xf);
ETHER_NEXT_MULTI(step, enm);
 1358         }
ifp->if_flags &= ~IFF_ALLMULTI;
 1361         goto sethash;
allmulti:
ifp->if_flags |= IFF_ALLMULTI;
mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0xffff;
sethash:
bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC0, mchash[0]);
bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC1, mchash[1]);
bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC2, mchash[2]);
bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC3, mchash[3]);
 1372 }
 1374 /*
 1375  * Wait for the MII to become ready.
 1376  */
 1377 int
epic_mii_wait(struct epic_softc *sc, u_int32_t rw)
 1379 {
 1380         int i;
 1382         for (i = 0; i < 50; i++) {
 1383                 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL) & rw)
 1384                     == 0)
 1385                         break;
delay(2);
 1387         }
 1388         if (i == 50) {
printf("%s: MII timed out\n", sc->sc_dev.dv_xname);
 1390                 return (1);
 1391         }
 1393         return (0);
 1394 }
 1396 /*
 1397  * Read from the MII.
 1398  */
 1399 int
epic_mii_read(struct device *self, int phy, int reg)
 1401 {
 1402         struct epic_softc *sc = (struct epic_softc *)self;
 1404         if (epic_mii_wait(sc, MMCTL_WRITE))
 1405                 return (0);
bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL,
MMCTL_ARG(phy, reg, MMCTL_READ));
 1410         if (epic_mii_wait(sc, MMCTL_READ))
 1411                 return (0);
 1413         return (bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA) &
MMDATA_MASK);
 1415 }
 1417 /*
 1418  * Write to the MII.
 1419  */
 1420 void
epic_mii_write(struct device *self, int phy, int reg, int val)
 1422 {
 1423         struct epic_softc *sc = (struct epic_softc *)self;
 1425         if (epic_mii_wait(sc, MMCTL_WRITE))
 1426                 return;
bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA, val);
bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL,
MMCTL_ARG(phy, reg, MMCTL_WRITE));
 1431 }
 1433 /*
 1434  * Callback from PHY when media changes.
 1435  */
 1436 void
epic_statchg(struct device *self)
 1438 {
 1439         struct epic_softc *sc = (struct epic_softc *)self;
u_int32_t txcon, miicfg;
 1442         /*
 1443          * Update loopback bits in TXCON to reflect duplex mode.
 1444          */
txcon = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_TXCON);
 1446         if (sc->sc_mii.mii_media_active & IFM_FDX)
txcon |= (TXCON_LOOPBACK_D1|TXCON_LOOPBACK_D2);
 1448         else
txcon &= ~(TXCON_LOOPBACK_D1|TXCON_LOOPBACK_D2);
bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TXCON, txcon);
 1452         /* On some cards we need manualy set fullduplex led */
 1453         if (sc->sc_hwflags & EPIC_DUPLEXLED_ON_694) {
miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG);
 1455                 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX)
miicfg |= MIICFG_ENABLE;
 1457                 else
miicfg &= ~MIICFG_ENABLE;
bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg);
 1460         }
 1462         /*
 1463          * There is a multicast filter bug in 10Mbps mode.  Kick the
 1464          * multicast filter in case the speed changed.
 1465          */
epic_set_mchash(sc);
 1467 }
 1469 /*
 1470  * Callback from ifmedia to request current media status.
 1471  */
 1472 void
epic_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
 1474 {
 1475         struct epic_softc *sc = ifp->if_softc;
mii_pollstat(&sc->sc_mii);
ifmr->ifm_status = sc->sc_mii.mii_media_status;
ifmr->ifm_active = sc->sc_mii.mii_media_active;
 1480 }
 1482 /*
 1483  * Callback from ifmedia to request new media setting.
 1484  */
 1485 int
epic_mediachange(struct ifnet *ifp)
 1487 {
 1488         struct epic_softc *sc = ifp->if_softc;
 1489         struct mii_data *mii = &sc->sc_mii;
 1490         struct ifmedia *ifm = &mii->mii_media;
 1491         int media = ifm->ifm_cur->ifm_media;
u_int32_t miicfg;
 1493         struct mii_softc *miisc;
 1494         int cfg;
 1496         if (!(ifp->if_flags & IFF_UP))
 1497                 return (0);
 1499         if (IFM_INST(media) != sc->sc_serinst) {
 1500                 /* If we're not selecting serial interface, select MII mode */
 1501 #ifdef EPICMEDIADEBUG
printf("%s: parallel mode\n", ifp->if_xname);
 1503 #endif
miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG);
miicfg &= ~MIICFG_SERMODEENA;
bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg);
 1507         }
mii_mediachg(mii);
 1511         if (IFM_INST(media) == sc->sc_serinst) {
 1512                 /* select serial interface */
 1513 #ifdef EPICMEDIADEBUG
printf("%s: serial mode\n", ifp->if_xname);
 1515 #endif
miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG);
miicfg |= (MIICFG_SERMODEENA | MIICFG_ENABLE);
bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg);
 1520                 /* There is no driver to fill this */
mii->mii_media_active = media;
mii->mii_media_status = 0;
epic_statchg(&sc->sc_dev);
 1525                 return (0);
 1526         }
 1528         /* Lookup selected PHY */
 1529         for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
miisc = LIST_NEXT(miisc, mii_list)) {
 1531                 if (IFM_INST(media) == miisc->mii_inst)
 1532                         break;
 1533         }
 1534         if (!miisc) {
printf("epic_mediachange: can't happen\n"); /* ??? panic */
 1536                 return (0);
 1537         }
 1538 #ifdef EPICMEDIADEBUG
printf("%s: using phy %s\n", ifp->if_xname,
miisc->mii_dev.dv_xname);
 1541 #endif
 1543         if (miisc->mii_flags & MIIF_HAVEFIBER) {
 1544                 /* XXX XXX assume it's a Level1 - should check */
 1546                 /* We have to powerup fiber transceivers */
cfg = PHY_READ(miisc, MII_LXTPHY_CONFIG);
 1548                 if (IFM_SUBTYPE(media) == IFM_100_FX) {
 1549 #ifdef EPICMEDIADEBUG
printf("%s: power up fiber\n", ifp->if_xname);
 1551 #endif
cfg |= (CONFIG_LEDC1 | CONFIG_LEDC0);
 1553                 } else {
 1554 #ifdef EPICMEDIADEBUG
printf("%s: power down fiber\n", ifp->if_xname);
 1556 #endif
cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0);
 1558                 }
PHY_WRITE(miisc, MII_LXTPHY_CONFIG, cfg);
 1560         }
 1562         return (0);
 1563 }