txd 377 dev/ic/aic6915.c struct sf_txdesc0 *txd;
txd 411 dev/ic/aic6915.c txd = &sc->sc_txdescs[producer];
txd 459 dev/ic/aic6915.c txd->td_word0 =
txd 462 dev/ic/aic6915.c txd->td_word0 |= TD_W0_END;
txd 463 dev/ic/aic6915.c txd->td_word1 = htole32(dmamap->dm_nsegs);
txd 465 dev/ic/aic6915.c txd->td_frags[seg].fr_addr =
txd 467 dev/ic/aic6915.c txd->td_frags[seg].fr_len =
txd 3621 dev/ic/atw.c struct atw_txdesc *txd;
txd 3924 dev/ic/atw.c txd = &sc->sc_txdescs[nexttx];
txd 3925 dev/ic/atw.c txd->at_ctl = ctl |
txd 3928 dev/ic/atw.c txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr);
txd 3929 dev/ic/atw.c txd->at_flags =
txd 962 dev/ic/awi.c u_int32_t txd, frame, ntxd;
txd 967 dev/ic/awi.c txd = sc->sc_txnext;
txd 1017 dev/ic/awi.c awi_write_4(sc, txd + AWI_TXD_START, frame);
txd 1018 dev/ic/awi.c awi_write_4(sc, txd + AWI_TXD_NEXT, ntxd);
txd 1019 dev/ic/awi.c awi_write_4(sc, txd + AWI_TXD_LENGTH, len);
txd 1020 dev/ic/awi.c awi_write_1(sc, txd + AWI_TXD_RATE, rate);
txd 1021 dev/ic/awi.c awi_write_4(sc, txd + AWI_TXD_NDA, 0);
txd 1022 dev/ic/awi.c awi_write_4(sc, txd + AWI_TXD_NRA, 0);
txd 1023 dev/ic/awi.c awi_write_1(sc, txd + AWI_TXD_STATE, AWI_TXD_ST_OWN);
txd 2541 dev/ic/awi.c u_int32_t txd, ntxd, frame;
txd 2543 dev/ic/awi.c txd = sc->sc_txnext;
txd 2544 dev/ic/awi.c frame = txd + AWI_TXD_SIZE;
txd 2563 dev/ic/awi.c if (txd < ntxd) {
txd 2564 dev/ic/awi.c if (txd < sc->sc_txdone && ntxd + AWI_TXD_SIZE > sc->sc_txdone)
txd 2567 dev/ic/awi.c if (txd < sc->sc_txdone || ntxd + AWI_TXD_SIZE > sc->sc_txdone)
txd 1482 dev/ic/pdq.c pdq_txdesc_t *txd = &pdq->pdq_dbp->pdqdb_command_requests[idx];
txd 1484 dev/ic/pdq.c txd->txd_pa_lo = pdq->pdq_command_info.ci_pa_bufstart;
txd 1485 dev/ic/pdq.c txd->txd_eop = txd->txd_sop = 1;
txd 1486 dev/ic/pdq.c txd->txd_pa_hi = 0;
txd 371 dev/ic/smc83c170.c struct epic_txdesc *txd;
txd 403 dev/ic/smc83c170.c txd = EPIC_CDTX(sc, nexttx);
txd 474 dev/ic/smc83c170.c txd->et_control = ET_TXCTL_LASTDESC | ET_TXCTL_FRAGLIST;
txd 482 dev/ic/smc83c170.c txd->et_txstatus = TXSTAT_TXLENGTH(len);
txd 484 dev/ic/smc83c170.c txd->et_txstatus =
txd 652 dev/ic/smc83c170.c struct epic_txdesc *txd;
txd 813 dev/ic/smc83c170.c txd = EPIC_CDTX(sc, i);
txd 819 dev/ic/smc83c170.c txstatus = txd->et_txstatus;
txd 965 dev/ic/smc83c170.c struct epic_txdesc *txd;
txd 1042 dev/ic/smc83c170.c txd = EPIC_CDTX(sc, i);
txd 1043 dev/ic/smc83c170.c memset(txd, 0, sizeof(struct epic_txdesc));
txd 1044 dev/ic/smc83c170.c txd->et_bufaddr = EPIC_CDFLADDR(sc, i);
txd 1045 dev/ic/smc83c170.c txd->et_nextdesc = EPIC_CDTXADDR(sc, EPIC_NEXTTX(i));
txd 1253 dev/pci/if_nxe.c struct nxe_tx_desc *txd;
txd 1271 dev/pci/if_nxe.c txd = nxe_ring_cur(sc, nr);
txd 1272 dev/pci/if_nxe.c bzero(txd, sizeof(struct nxe_tx_desc));
txd 1302 dev/pci/if_nxe.c txd->tx_flags = htole16(NXE_TXD_F_OPCODE_TX);
txd 1303 dev/pci/if_nxe.c txd->tx_nbufs = dmap->dm_nsegs;
txd 1304 dev/pci/if_nxe.c txd->tx_length = htole16(dmap->dm_mapsize);
txd 1305 dev/pci/if_nxe.c txd->tx_id = pkt->pkt_id;
txd 1306 dev/pci/if_nxe.c txd->tx_port = sc->sc_port;
txd 1314 dev/pci/if_nxe.c txd->tx_addr_4 = htole64(segs[3].ds_addr);
txd 1315 dev/pci/if_nxe.c txd->tx_slen_4 = htole32(segs[3].ds_len);
txd 1317 dev/pci/if_nxe.c txd->tx_addr_3 = htole64(segs[2].ds_addr);
txd 1318 dev/pci/if_nxe.c txd->tx_slen_3 = htole32(segs[2].ds_len);
txd 1320 dev/pci/if_nxe.c txd->tx_addr_2 = htole64(segs[1].ds_addr);
txd 1321 dev/pci/if_nxe.c txd->tx_slen_2 = htole32(segs[1].ds_len);
txd 1323 dev/pci/if_nxe.c txd->tx_addr_1 = htole64(segs[0].ds_addr);
txd 1324 dev/pci/if_nxe.c txd->tx_slen_1 = htole32(segs[0].ds_len);
txd 1334 dev/pci/if_nxe.c txd = nxe_ring_next(sc, nr);
txd 1335 dev/pci/if_nxe.c bzero(txd, sizeof(struct nxe_tx_desc));
txd 855 dev/pci/if_txp.c struct txp_tx_desc *txd = r->r_desc + cons;
txd 868 dev/pci/if_txp.c if ((txd->tx_flags & TX_FLAGS_TYPE_M) ==
txd 876 dev/pci/if_txp.c txd->tx_addrlo = 0;
txd 877 dev/pci/if_txp.c txd->tx_addrhi = 0;
txd 884 dev/pci/if_txp.c txd = r->r_desc;
txd 888 dev/pci/if_txp.c txd++;
txd 1382 dev/pci/if_txp.c struct txp_tx_desc *txd;
txd 1435 dev/pci/if_txp.c txd = r->r_desc + prod;
txd 1437 dev/pci/if_txp.c txd->tx_flags = TX_FLAGS_TYPE_DATA;
txd 1438 dev/pci/if_txp.c txd->tx_numdesc = 0;
txd 1439 dev/pci/if_txp.c txd->tx_addrlo = 0;
txd 1440 dev/pci/if_txp.c txd->tx_addrhi = 0;
txd 1441 dev/pci/if_txp.c txd->tx_totlen = m->m_pkthdr.len;
txd 1442 dev/pci/if_txp.c txd->tx_pflags = 0;
txd 1443 dev/pci/if_txp.c txd->tx_numdesc = sd->sd_map->dm_nsegs;
txd 1455 dev/pci/if_txp.c txd->tx_pflags = TX_PFLAGS_VLAN |
txd 1461 dev/pci/if_txp.c txd->tx_pflags |= TX_PFLAGS_IPCKSUM;
txd 1464 dev/pci/if_txp.c txd->tx_pflags |= TX_PFLAGS_TCPCKSUM;
txd 1468 dev/pci/if_txp.c txd->tx_pflags |= TX_PFLAGS_UDPCKSUM;
txd 1522 dev/pci/if_txp.c txd->tx_flags |= TX_FLAGS_VALID;
txd 1533 dev/pci/if_txp.c txd->tx_flags, txd->tx_numdesc, txd->tx_totlen,
txd 1534 dev/pci/if_txp.c txd->tx_pflags);
txd 1898 dev/pci/if_txp.c struct txp_tx_desc *txd = d;
txd 1919 dev/pci/if_txp.c txd->tx_flags, txd->tx_numdesc, txd->tx_totlen,
txd 1920 dev/pci/if_txp.c txd->tx_addrlo, txd->tx_addrhi, txd->tx_pflags);
txd 802 dev/pci/if_vic.c struct vic_txdesc *txd;
txd 816 dev/pci/if_vic.c txd = &sc->sc_txq[idx];
txd 817 dev/pci/if_vic.c if (txd->tx_owner != VIC_OWNER_DRIVER)
txd 952 dev/pci/if_vic.c struct vic_txdesc *txd;
txd 989 dev/pci/if_vic.c txd = &sc->sc_txq[idx];
txd 1017 dev/pci/if_vic.c txd->tx_flags = VIC_TX_FLAGS_KEEP;
txd 1018 dev/pci/if_vic.c txd->tx_owner = VIC_OWNER_NIC;
txd 1019 dev/pci/if_vic.c txd->tx_sa.sa_addr_type = VIC_SG_ADDR_PHYS;
txd 1020 dev/pci/if_vic.c txd->tx_sa.sa_length = dmap->dm_nsegs;
txd 1022 dev/pci/if_vic.c sge = &txd->tx_sa.sa_sg[i];
txd 1028 dev/pci/if_vic.c txd->tx_flags |= VIC_TX_FLAGS_TXURN;
txd 196 dev/pci/if_xge.c struct txd *sc_txd[NTXDESCS]; /* transmit frags array */
txd 825 dev/pci/if_xge.c struct txd *txd;
txd 858 dev/pci/if_xge.c txd = sc->sc_txd[i];
txd 865 dev/pci/if_xge.c if (txd->txd_control1 & TXD_CTL1_OWN) {
txd 1103 dev/pci/if_xge.c struct txd *txd = NULL; /* XXX - gcc */
txd 1138 dev/pci/if_xge.c txd = sc->sc_txd[nexttx];
txd 1143 dev/pci/if_xge.c txd->txd_control1 = dmp->dm_segs[i].ds_len;
txd 1144 dev/pci/if_xge.c txd->txd_control2 = 0;
txd 1145 dev/pci/if_xge.c txd->txd_bufaddr = dmp->dm_segs[i].ds_addr;
txd 1146 dev/pci/if_xge.c txd++;
txd 1148 dev/pci/if_xge.c ntxd = txd - sc->sc_txd[nexttx] - 1;
txd 1149 dev/pci/if_xge.c txd = sc->sc_txd[nexttx];
txd 1150 dev/pci/if_xge.c txd->txd_control1 |= TXD_CTL1_OWN|TXD_CTL1_GCF;
txd 1151 dev/pci/if_xge.c txd->txd_control2 = TXD_CTL2_UTIL;
txd 1158 dev/pci/if_xge.c txd->txd_control2 |= TXD_CTL2_VLANE;
txd 1159 dev/pci/if_xge.c txd->txd_control2 |= TXD_CTL2_VLANT(ifv->ifv_tag);
txd 1164 dev/pci/if_xge.c txd->txd_control2 |= TXD_CTL2_CIPv4;
txd 1166 dev/pci/if_xge.c txd->txd_control2 |= TXD_CTL2_CTCP;
txd 1168 dev/pci/if_xge.c txd->txd_control2 |= TXD_CTL2_CUDP;
txd 1170 dev/pci/if_xge.c txd[ntxd].txd_control1 |= TXD_CTL1_GCL;
txd 1196 dev/pci/if_xge.c struct txd *txp;
txd 1202 dev/pci/if_xge.c #define TXMAPSZ (NTXDESCS*NTXFRAGS*sizeof(struct txd))
txd 1222 dev/pci/if_xge.c txp = (struct txd *)kva;
txd 1224 dev/pci/if_xge.c for (txp = (struct txd *)kva, i = 0; i < NTXDESCS; i++) {
txd 1228 dev/pci/if_xge.c txdp += (NTXFRAGS * sizeof(struct txd));
txd 220 dev/pci/if_xgereg.h struct txd {
txd 592 dev/sbus/be.c struct qec_xd *txd = sc->sc_rb.rb_txd;
txd 624 dev/sbus/be.c txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP |
txd 464 dev/sbus/qe.c struct qec_xd *txd = sc->sc_rb.rb_txd;
txd 498 dev/sbus/qe.c txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP |