root/dev/pci/if_xge.c

DEFINITIONS

1. pif_wcsr
2. pif_rcsr
3. txp_wcsr
4. pif_wkey
5. xge_match
6. xge_attach
7. xge_ifmedia_status
8. xge_xgmii_mediachange
9. xge_enable
10. xge_init
11. xge_stop
12. xge_shutdown
13. xge_intr
14. xge_ioctl
15. xge_setmulti
16. xge_setpromisc
17. xge_start
18. xge_alloc_txmem
19. xge_alloc_rxmem
20. xge_add_rxbuf
21. xge_setup_xgxs_xena
22. xge_setup_xgxs_herc

    1 /*      $OpenBSD: if_xge.c,v 1.42 2007/05/28 23:39:07 ckuethe Exp $     */
    2 /*      $NetBSD: if_xge.c,v 1.1 2005/09/09 10:30:27 ragge Exp $ */
    4 /*
    5  * Copyright (c) 2004, SUNET, Swedish University Computer Network.
    6  * All rights reserved.
    7  *
    8  * Written by Anders Magnusson for SUNET, Swedish University Computer Network.
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  * 3. All advertising materials mentioning features or use of this software
   19  *    must display the following acknowledgement:
   20  *      This product includes software developed for the NetBSD Project by
   21  *      SUNET, Swedish University Computer Network.
   22  * 4. The name of SUNET may not be used to endorse or promote products
   23  *    derived from this software without specific prior written permission.
   24  *
   25  * THIS SOFTWARE IS PROVIDED BY SUNET ``AS IS'' AND
   26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL SUNET
   29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   35  * POSSIBILITY OF SUCH DAMAGE.
   36  */
   38 /*
   39  * Driver for the Neterion Xframe Ten Gigabit Ethernet controller.
   40  */
   42 #include "bpfilter.h"
   43 #include "vlan.h"
   45 #include <sys/param.h>
   46 #include <sys/systm.h>
   47 #include <sys/sockio.h>
   48 #include <sys/mbuf.h>
   49 #include <sys/malloc.h>
   50 #include <sys/kernel.h>
   51 #include <sys/socket.h>
   52 #include <sys/device.h>
   54 #include <net/if.h>
   55 #include <net/if_dl.h>
   56 #include <net/if_media.h>
   58 #ifdef INET
   59 #include <netinet/in.h>
   60 #include <netinet/in_systm.h>
   61 #include <netinet/in_var.h>
   62 #include <netinet/ip.h>
   63 #include <netinet/if_ether.h>
   64 #include <netinet/tcp.h>
   65 #include <netinet/udp.h>
   66 #endif
   68 #if NVLAN > 0
   69 #include <net/if_types.h>
   70 #include <net/if_vlan_var.h>
   71 #endif
   73 #if NBPFILTER > 0
   74 #include <net/bpf.h>
   75 #endif
   77 #include <machine/bus.h>
   78 #include <machine/intr.h>
   79 #include <machine/endian.h>
   81 #include <dev/mii/mii.h>
   82 #include <dev/mii/miivar.h>
   84 #include <dev/pci/pcivar.h>
   85 #include <dev/pci/pcireg.h>
   86 #include <dev/pci/pcidevs.h>
   88 #include <sys/lock.h>
   89 #include <sys/proc.h>
   91 #include <dev/pci/if_xgereg.h>
   93 /* Xframe chipset revisions */
   94 #define XGE_TYPE_XENA           1       /* Xframe */
   95 #define XGE_TYPE_HERC           2       /* Xframe-II */
   97 #define XGE_PCISIZE_XENA        26
   98 #define XGE_PCISIZE_HERC        64
  100 /*
  101  * Some tunable constants, tune with care!
  102  */
  103 #define RX_MODE         RX_MODE_1  /* Receive mode (buffer usage, see below) */
  104 #define NRXDESCS        1016       /* # of receive descriptors (requested) */
  105 #define NTXDESCS        2048       /* Number of transmit descriptors */
  106 #define NTXFRAGS        100        /* Max fragments per packet */
  108 /*
  109  * Receive buffer modes; 1, 3 or 5 buffers.
  110  */
  111 #define RX_MODE_1 1
  112 #define RX_MODE_3 3
  113 #define RX_MODE_5 5
  115 /*
  116  * Use clever macros to avoid a bunch of #ifdef's.
  117  */
  118 #define XCONCAT3(x,y,z) x ## y ## z
  119 #define CONCAT3(x,y,z) XCONCAT3(x,y,z)
  120 #define NDESC_BUFMODE CONCAT3(NDESC_,RX_MODE,BUFMODE)
  121 #define rxd_4k CONCAT3(rxd,RX_MODE,_4k)
  122 /* XXX */
  123 #if 0
  124 #define rxdesc ___CONCAT(rxd,RX_MODE)
  125 #endif
  126 #define rxdesc rxd1
  128 #define NEXTTX(x)       (((x)+1) % NTXDESCS)
  129 #define NRXFRAGS        RX_MODE /* hardware imposed frags */
  130 #define NRXPAGES        ((NRXDESCS/NDESC_BUFMODE)+1)
  131 #define NRXREAL         (NRXPAGES*NDESC_BUFMODE)
  132 #define RXMAPSZ         (NRXPAGES*PAGE_SIZE)
  134 /*
  135  * Magic to fix a bug when the MAC address cannot be read correctly.
  136  * This came from the Linux driver.
  137  */
  138 static uint64_t fix_mac[] = {
  139         0x0060000000000000ULL, 0x0060600000000000ULL,
  140         0x0040600000000000ULL, 0x0000600000000000ULL,
  141         0x0020600000000000ULL, 0x0060600000000000ULL,
  142         0x0020600000000000ULL, 0x0060600000000000ULL,
  143         0x0020600000000000ULL, 0x0060600000000000ULL,
  144         0x0020600000000000ULL, 0x0060600000000000ULL,
  145         0x0020600000000000ULL, 0x0060600000000000ULL,
  146         0x0020600000000000ULL, 0x0060600000000000ULL,
  147         0x0020600000000000ULL, 0x0060600000000000ULL,
  148         0x0020600000000000ULL, 0x0060600000000000ULL,
  149         0x0020600000000000ULL, 0x0060600000000000ULL,
  150         0x0020600000000000ULL, 0x0060600000000000ULL,
  151         0x0020600000000000ULL, 0x0000600000000000ULL,
  152         0x0040600000000000ULL, 0x0060600000000000ULL,
  153 };
  155 /*
  156  * Constants to be programmed into Hercules's registers, to configure
  157  * the XGXS transciever.
  158  */
  159 #define END_SIGN 0x0
  160 static uint64_t herc_dtx_cfg[] = {
  161         0x8000051536750000ULL, 0x80000515367500E0ULL,
  162         0x8000051536750004ULL, 0x80000515367500E4ULL,
  164         0x80010515003F0000ULL, 0x80010515003F00E0ULL,
  165         0x80010515003F0004ULL, 0x80010515003F00E4ULL,
  167         0x801205150D440000ULL, 0x801205150D4400E0ULL,
  168         0x801205150D440004ULL, 0x801205150D4400E4ULL,
  170         0x80020515F2100000ULL, 0x80020515F21000E0ULL,
  171         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
END_SIGN
  174 };
  176 struct xge_softc {
  177         struct device           sc_dev;
  178         struct arpcom           sc_arpcom;
  179         struct ifmedia          xena_media;
  181         void                    *sc_ih;
  182         void                    *sc_shutdownhook;
bus_dma_tag_t           sc_dmat;
bus_space_tag_t         sc_st;
bus_space_handle_t      sc_sh;
bus_space_tag_t         sc_txt;
bus_space_handle_t      sc_txh;
pcireg_t                sc_pciregs[16];
  192         int                     xge_type; /* chip type */
  193         int                     xge_if_flags;
  195         /* Transmit structures */
  196         struct txd              *sc_txd[NTXDESCS]; /* transmit frags array */
bus_addr_t              sc_txdp[NTXDESCS]; /* dva of transmit frags */
bus_dmamap_t            sc_txm[NTXDESCS]; /* transmit frags map */
  199         struct mbuf             *sc_txb[NTXDESCS]; /* transmit mbuf pointer */
  200         int                     sc_nexttx, sc_lasttx;
bus_dmamap_t            sc_txmap; /* transmit descriptor map */
  203         /* Receive data */
bus_dmamap_t            sc_rxmap; /* receive descriptor map */
  205         struct rxd_4k           *sc_rxd_4k[NRXPAGES]; /* receive desc pages */
bus_dmamap_t            sc_rxm[NRXREAL]; /* receive buffer map */
  207         struct mbuf             *sc_rxb[NRXREAL]; /* mbufs on rx descriptors */
  208         int                     sc_nextrx; /* next descriptor to check */
  209 };
  211 #ifdef XGE_DEBUG
  212 #define DPRINTF(x)      do { if (xgedebug) printf x ; } while (0)
  213 #define DPRINTFN(n,x)   do { if (xgedebug >= (n)) printf x ; } while (0)
  214 int     xgedebug = 0;
  215 #else
  216 #define DPRINTF(x)
  217 #define DPRINTFN(n,x)
  218 #endif
  220 int xge_match(struct device *, void *, void *);
  221 void xge_attach(struct device *, struct device *, void *);
  222 int xge_alloc_txmem(struct xge_softc *);
  223 int xge_alloc_rxmem(struct xge_softc *);
  224 void xge_start(struct ifnet *);
  225 void xge_stop(struct ifnet *, int);
  226 void xge_shutdown(void *);
  227 int xge_add_rxbuf(struct xge_softc *, int);
  228 void xge_setmulti(struct xge_softc *);
  229 void xge_setpromisc(struct xge_softc *);
  230 int xge_setup_xgxs_xena(struct xge_softc *);
  231 int xge_setup_xgxs_herc(struct xge_softc *);
  232 int xge_ioctl(struct ifnet *, u_long, caddr_t);
  233 int xge_init(struct ifnet *);
  234 void xge_ifmedia_status(struct ifnet *, struct ifmediareq *);
  235 int xge_xgmii_mediachange(struct ifnet *);
  236 void xge_enable(struct xge_softc *);
  237 int xge_intr(void  *);
  239 /*
  240  * Helpers to address registers.
  241  */
  242 #define PIF_WCSR(csr, val)      pif_wcsr(sc, csr, val)
  243 #define PIF_RCSR(csr)           pif_rcsr(sc, csr)
  244 #define TXP_WCSR(csr, val)      txp_wcsr(sc, csr, val)
  245 #define PIF_WKEY(csr, val)      pif_wkey(sc, csr, val)
  247 static inline void
pif_wcsr(struct xge_softc *sc, bus_size_t csr, uint64_t val)
  249 {
uint32_t lval, hval;
lval = val&0xffffffff;
hval = val>>32;
bus_space_write_4(sc->sc_st, sc->sc_sh, csr, lval); 
bus_space_write_4(sc->sc_st, sc->sc_sh, csr+4, hval);
  257 }
  259 static inline uint64_t
pif_rcsr(struct xge_softc *sc, bus_size_t csr)
  261 {
uint64_t val, val2;
val = bus_space_read_4(sc->sc_st, sc->sc_sh, csr);
val2 = bus_space_read_4(sc->sc_st, sc->sc_sh, csr+4);
val |= (val2 << 32);
  267         return (val);
  268 }
  270 static inline void
txp_wcsr(struct xge_softc *sc, bus_size_t csr, uint64_t val)
  272 {
uint32_t lval, hval;
lval = val&0xffffffff;
hval = val>>32;
bus_space_write_4(sc->sc_txt, sc->sc_txh, csr, lval); 
bus_space_write_4(sc->sc_txt, sc->sc_txh, csr+4, hval);
  280 }
  283 static inline void
pif_wkey(struct xge_softc *sc, bus_size_t csr, uint64_t val)
  285 {
uint32_t lval, hval;
lval = val&0xffffffff;
hval = val>>32;
  291         if (sc->xge_type == XGE_TYPE_XENA)
PIF_WCSR(RMAC_CFG_KEY, RMAC_KEY_VALUE);
bus_space_write_4(sc->sc_st, sc->sc_sh, csr, lval);
  296         if (sc->xge_type == XGE_TYPE_XENA)
PIF_WCSR(RMAC_CFG_KEY, RMAC_KEY_VALUE);
bus_space_write_4(sc->sc_st, sc->sc_sh, csr+4, hval);
  300 }
  302 struct cfattach xge_ca = {
  303         sizeof(struct xge_softc), xge_match, xge_attach
  304 };
  306 struct cfdriver xge_cd = {
  307         0, "xge", DV_IFNET
  308 };
  310 #define XNAME sc->sc_dev.dv_xname
  312 #define XGE_RXSYNC(desc, what) \
bus_dmamap_sync(sc->sc_dmat, sc->sc_rxmap, \
  314         (desc/NDESC_BUFMODE) * XGE_PAGE + sizeof(struct rxdesc) * \
  315         (desc%NDESC_BUFMODE), sizeof(struct rxdesc), what)
  316 #define XGE_RXD(desc)   &sc->sc_rxd_4k[desc/NDESC_BUFMODE]-> \
r4_rxd[desc%NDESC_BUFMODE]
  319 /*
  320  * Non-tunable constants.
  321  */
  322 #define XGE_MAX_FRAMELEN        9622
  323 #define XGE_MAX_MTU             (XGE_MAX_FRAMELEN - ETHER_HDR_LEN - \
ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN)
  326 const struct pci_matchid xge_devices[] = {
  327         { PCI_VENDOR_NETERION, PCI_PRODUCT_NETERION_XFRAME },
  328         { PCI_VENDOR_NETERION, PCI_PRODUCT_NETERION_XFRAME_2 }
  329 };
  331 int
xge_match(struct device *parent, void *match, void *aux)
  333 {
  334         return (pci_matchbyid((struct pci_attach_args *)aux, xge_devices,
  335             sizeof(xge_devices)/sizeof(xge_devices[0])));
  336 }
  338 void
xge_attach(struct device *parent, struct device *self, void *aux)
  340 {
  341         struct pci_attach_args *pa = aux;
  342         struct xge_softc *sc;
  343         struct ifnet *ifp;
pcireg_t memtype;
pci_intr_handle_t ih;
  346         const char *intrstr = NULL;
pci_chipset_tag_t pc = pa->pa_pc;
uint8_t enaddr[ETHER_ADDR_LEN];
uint64_t val;
  350         int i;
sc = (struct xge_softc *)self;
sc->sc_dmat = pa->pa_dmat;
  356         if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NETERION_XFRAME)
sc->xge_type = XGE_TYPE_XENA;
  358         else
sc->xge_type = XGE_TYPE_HERC;
  361         /* Get BAR0 address */
memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, XGE_PIF_BAR);
  363         if (pci_mapreg_map(pa, XGE_PIF_BAR, memtype, 0,
  364             &sc->sc_st, &sc->sc_sh, 0, 0, 0)) {
printf(": unable to map PIF BAR registers\n");
  366                 return;
  367         }
memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, XGE_TXP_BAR);
  370         if (pci_mapreg_map(pa, XGE_TXP_BAR, memtype, 0,
  371             &sc->sc_txt, &sc->sc_txh, 0, 0, 0)) {
printf(": unable to map TXP BAR registers\n");
  373                 return;
  374         }
  376         if (sc->xge_type == XGE_TYPE_XENA) {
  377                 /* Save PCI config space */
  378                 for (i = 0; i < XGE_PCISIZE_XENA; i += 4)
sc->sc_pciregs[i/4] = pci_conf_read(pa->pa_pc, pa->pa_tag, i);
  380         }
  382 #if BYTE_ORDER == LITTLE_ENDIAN
val = (uint64_t)0xFFFFFFFFFFFFFFFFULL;
val &= ~(TxF_R_SE|RxF_W_SE);
PIF_WCSR(SWAPPER_CTRL, val);
PIF_WCSR(SWAPPER_CTRL, val);
  387 #endif
  389         if ((val = PIF_RCSR(PIF_RD_SWAPPER_Fb)) != SWAPPER_MAGIC) {
printf(": failed configuring endian, %llx != %llx!\n",
  391                     (unsigned long long)val, SWAPPER_MAGIC);
  392                 return;
  393         }
  395         /*
  396          * Fix for all "FFs" MAC address problems observed on
  397          * Alpha platforms. Not needed for Herc.
  398          */ 
  399         if (sc->xge_type == XGE_TYPE_XENA) {
  400                 /*
  401                  * The MAC addr may be all FF's, which is not good.
  402                  * Resolve it by writing some magics to GPIO_CONTROL and 
  403                  * force a chip reset to read in the serial eeprom again.
  404                  */
  405                 for (i = 0; i < sizeof(fix_mac)/sizeof(fix_mac[0]); i++) {
PIF_WCSR(GPIO_CONTROL, fix_mac[i]);
PIF_RCSR(GPIO_CONTROL);
  408                 }
  410                 /*
  411                  * Reset the chip and restore the PCI registers.
  412                  */
PIF_WCSR(SW_RESET, 0xa5a5a50000000000ULL);
DELAY(500000);
  415                 for (i = 0; i < XGE_PCISIZE_XENA; i += 4)
pci_conf_write(pa->pa_pc, pa->pa_tag, i, sc->sc_pciregs[i/4]);
  418                 /*
  419                  * Restore the byte order registers.
  420                  */
  421 #if BYTE_ORDER == LITTLE_ENDIAN
val = (uint64_t)0xFFFFFFFFFFFFFFFFULL;
val &= ~(TxF_R_SE|RxF_W_SE);
PIF_WCSR(SWAPPER_CTRL, val);
PIF_WCSR(SWAPPER_CTRL, val);
  426 #endif
  428                 if ((val = PIF_RCSR(PIF_RD_SWAPPER_Fb)) != SWAPPER_MAGIC) {
printf(": failed configuring endian2, %llx != %llx!\n",
  430                             (unsigned long long)val, SWAPPER_MAGIC);
  431                         return;
  432                 }
  433         }
  435         /*
  436          * XGXS initialization.
  437          */
  439         /*
  440          * For Herc, bring EOI out of reset before XGXS.
  441          */
  442         if (sc->xge_type == XGE_TYPE_HERC) {
val = PIF_RCSR(SW_RESET);
val &= 0xffff00ffffffffffULL;
PIF_WCSR(SW_RESET,val);
delay(1000*1000);       /* wait for 1 sec */
  447         }
  449         /* 29, Bring adapter out of reset */
val = PIF_RCSR(SW_RESET);
val &= 0xffffff00ffffffffULL;
PIF_WCSR(SW_RESET, val);
DELAY(500000);
  455         /* Ensure that it's safe to access registers by checking
  456          * RIC_RUNNING bit is reset. Check is valid only for XframeII.
  457          */
  458         if (sc->xge_type == XGE_TYPE_HERC){
  459                 for (i = 0; i < 50; i++) {
val = PIF_RCSR(ADAPTER_STATUS);
  461                         if (!(val & RIC_RUNNING))
  462                                 break;
delay(20*1000);
  464                 }
  466                 if (i == 50) {
printf(": not safe to access registers\n");
  468                         return;
  469                 }
  470         }
  472         /* 30, configure XGXS transceiver */
  473         if (sc->xge_type == XGE_TYPE_XENA)
xge_setup_xgxs_xena(sc);
  475         else if(sc->xge_type == XGE_TYPE_HERC)
xge_setup_xgxs_herc(sc);
  478         /* 33, program MAC address (not needed here) */
  479         /* Get ethernet address */
PIF_WCSR(RMAC_ADDR_CMD_MEM,
RMAC_ADDR_CMD_MEM_STR|RMAC_ADDR_CMD_MEM_OFF(0));
  482         while (PIF_RCSR(RMAC_ADDR_CMD_MEM) & RMAC_ADDR_CMD_MEM_STR)
  483                 ;
val = PIF_RCSR(RMAC_ADDR_DATA0_MEM);
  485         for (i = 0; i < ETHER_ADDR_LEN; i++)
enaddr[i] = (uint8_t)(val >> (56 - (8*i)));
  488         /*
  489          * Get memory for transmit descriptor lists.
  490          */
  491         if (xge_alloc_txmem(sc)) {
printf(": failed allocating txmem.\n");
  493                 return;
  494         }
  496         /* 9 and 10 - set FIFO number/prio */
PIF_WCSR(TX_FIFO_P0, TX_FIFO_LEN0(NTXDESCS));
PIF_WCSR(TX_FIFO_P1, 0ULL);
PIF_WCSR(TX_FIFO_P2, 0ULL);
PIF_WCSR(TX_FIFO_P3, 0ULL);
  502         /* 11, XXX set round-robin prio? */
  504         /* 12, enable transmit FIFO */
val = PIF_RCSR(TX_FIFO_P0);
val |= TX_FIFO_ENABLE;
PIF_WCSR(TX_FIFO_P0, val);
  509         /* 13, disable some error checks */
PIF_WCSR(TX_PA_CFG,
TX_PA_CFG_IFR|TX_PA_CFG_ISO|TX_PA_CFG_ILC|TX_PA_CFG_ILE);
  513         /* Create transmit DMA maps */
  514         for (i = 0; i < NTXDESCS; i++) {
  515                 if (bus_dmamap_create(sc->sc_dmat, XGE_MAX_FRAMELEN,
NTXFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, &sc->sc_txm[i])) {
printf(": cannot create TX DMA maps\n");
  518                         return;
  519                 }
  520         }
sc->sc_lasttx = NTXDESCS-1;
  524         /*
  525          * RxDMA initialization.
  526          * Only use one out of 8 possible receive queues.
  527          */
  528         /* allocate rx descriptor memory */
  529         if (xge_alloc_rxmem(sc)) {
printf(": failed allocating rxmem\n");
  531                 return;
  532         }
  534         /* Create receive buffer DMA maps */
  535         for (i = 0; i < NRXREAL; i++) {
  536                 if (bus_dmamap_create(sc->sc_dmat, XGE_MAX_FRAMELEN,
NRXFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, &sc->sc_rxm[i])) {
printf(": cannot create RX DMA maps\n");
  539                         return;
  540                 }
  541         }
  543         /* allocate mbufs to receive descriptors */
  544         for (i = 0; i < NRXREAL; i++)
  545                 if (xge_add_rxbuf(sc, i))
panic("out of mbufs too early");
  548         /* 14, setup receive ring priority */
PIF_WCSR(RX_QUEUE_PRIORITY, 0ULL); /* only use one ring */
  551         /* 15, setup receive ring round-robin calendar */
PIF_WCSR(RX_W_ROUND_ROBIN_0, 0ULL); /* only use one ring */
PIF_WCSR(RX_W_ROUND_ROBIN_1, 0ULL);
PIF_WCSR(RX_W_ROUND_ROBIN_2, 0ULL);
PIF_WCSR(RX_W_ROUND_ROBIN_3, 0ULL);
PIF_WCSR(RX_W_ROUND_ROBIN_4, 0ULL);
  558         /* 16, write receive ring start address */
PIF_WCSR(PRC_RXD0_0, (uint64_t)sc->sc_rxmap->dm_segs[0].ds_addr);
  560         /* PRC_RXD0_[1-7] are not used */
  562         /* 17, Setup alarm registers */
PIF_WCSR(PRC_ALARM_ACTION, 0ULL); /* Default everything to retry */
  565         /* 18, init receive ring controller */
  566 #if RX_MODE == RX_MODE_1
val = RING_MODE_1;
  568 #elif RX_MODE == RX_MODE_3
val = RING_MODE_3;
  570 #else /* RX_MODE == RX_MODE_5 */
val = RING_MODE_5;
  572 #endif
PIF_WCSR(PRC_CTRL_0, RC_IN_SVC|val);
  574         /* leave 1-7 disabled */
  575         /* XXXX snoop configuration? */
  577         /* 19, set chip memory assigned to the queue */
  578         if (sc->xge_type == XGE_TYPE_XENA) {
  579                 /* all 64M to queue 0 */
PIF_WCSR(RX_QUEUE_CFG, MC_QUEUE(0, 64));
  581         } else {
  582                 /* all 32M to queue 0 */
PIF_WCSR(RX_QUEUE_CFG, MC_QUEUE(0, 32));
  584         }
  586         /* 20, setup RLDRAM parameters */
  587         /* do not touch it for now */
  589         /* 21, setup pause frame thresholds */
  590         /* so not touch the defaults */
  591         /* XXX - must 0xff be written as stated in the manual? */
  593         /* 22, configure RED */
  594         /* we do not want to drop packets, so ignore */
  596         /* 23, initiate RLDRAM */
val = PIF_RCSR(MC_RLDRAM_MRS);
val |= MC_QUEUE_SIZE_ENABLE|MC_RLDRAM_MRS_ENABLE;
PIF_WCSR(MC_RLDRAM_MRS, val);
DELAY(1000);
  602         /*
  603          * Setup interrupt policies.
  604          */
  605         /* 40, Transmit interrupts */
PIF_WCSR(TTI_DATA1_MEM, TX_TIMER_VAL(0x1ff) | TX_TIMER_AC |
TX_URNG_A(5) | TX_URNG_B(20) | TX_URNG_C(48));
PIF_WCSR(TTI_DATA2_MEM,
TX_UFC_A(25) | TX_UFC_B(64) | TX_UFC_C(128) | TX_UFC_D(512));
PIF_WCSR(TTI_COMMAND_MEM, TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE);
  611         while (PIF_RCSR(TTI_COMMAND_MEM) & TTI_CMD_MEM_STROBE)
  612                 ;
  614         /* 41, Receive interrupts */
PIF_WCSR(RTI_DATA1_MEM, RX_TIMER_VAL(0x800) | RX_TIMER_AC |
RX_URNG_A(5) | RX_URNG_B(20) | RX_URNG_C(50));
PIF_WCSR(RTI_DATA2_MEM,
RX_UFC_A(64) | RX_UFC_B(128) | RX_UFC_C(256) | RX_UFC_D(512));
PIF_WCSR(RTI_COMMAND_MEM, RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE);
  620         while (PIF_RCSR(RTI_COMMAND_MEM) & RTI_CMD_MEM_STROBE)
  621                 ;
  623         /*
  624          * Setup media stuff.
  625          */
ifmedia_init(&sc->xena_media, IFM_IMASK, xge_xgmii_mediachange,
xge_ifmedia_status);
ifmedia_add(&sc->xena_media, IFM_ETHER|IFM_10G_SR, 0, NULL);
ifmedia_set(&sc->xena_media, IFM_ETHER|IFM_10G_SR);
ifp = &sc->sc_arpcom.ac_if;
strlcpy(ifp->if_xname, XNAME, IFNAMSIZ);
memcpy(sc->sc_arpcom.ac_enaddr, enaddr, ETHER_ADDR_LEN);
ifp->if_baudrate = 1000000000;
ifp->if_softc = sc;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_ioctl = xge_ioctl;
ifp->if_start = xge_start;
  639 #ifdef XGE_JUMBO
ifp->if_hardmtu = XGE_MAX_MTU;
  641 #endif
IFQ_SET_MAXLEN(&ifp->if_snd, NTXDESCS - 1);
IFQ_SET_READY(&ifp->if_snd);
ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_CSUM_IPv4 |
IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4;
  648 #if NVLAN > 0
ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
  650 #endif
  652         /*
  653          * Attach the interface.
  654          */
if_attach(ifp);
ether_ifattach(ifp);
sc->sc_shutdownhook = shutdownhook_establish(xge_shutdown, sc);
  660         /*
  661          * Setup interrupt vector before initializing.
  662          */
  663         if (pci_intr_map(pa, &ih)) {
printf(": unable to map interrupt\n");
  665                 return;
  666         }
intrstr = pci_intr_string(pc, ih);
  668         if ((sc->sc_ih =
pci_intr_establish(pc, ih, IPL_NET, xge_intr, sc, XNAME)) == NULL) {
printf(": unable to establish interrupt at %s\n",
intrstr ? intrstr : "<unknown>");
  672                 return;
  673             }
printf(": %s, address %s\n", intrstr, ether_sprintf(enaddr));
  675 }
  677 void
xge_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr)
  679 {
  680         struct xge_softc *sc = ifp->if_softc;
uint64_t reg;
ifmr->ifm_status = IFM_AVALID;
ifmr->ifm_active = IFM_ETHER|IFM_10G_SR;
reg = PIF_RCSR(ADAPTER_STATUS);
  687         if ((reg & (RMAC_REMOTE_FAULT|RMAC_LOCAL_FAULT)) == 0)  
ifmr->ifm_status |= IFM_ACTIVE;
  689 }
  691 int
xge_xgmii_mediachange(struct ifnet *ifp)
  693 {
  694         return (0);
  695 }
  697 void
xge_enable(struct xge_softc *sc)
  699 {
uint64_t val;
  702         /* 2, enable adapter */
val = PIF_RCSR(ADAPTER_CONTROL);
val |= ADAPTER_EN;
PIF_WCSR(ADAPTER_CONTROL, val);
  707         /* 3, light the card enable led */
val = PIF_RCSR(ADAPTER_CONTROL);
val |= LED_ON;
PIF_WCSR(ADAPTER_CONTROL, val);
  711 #ifdef XGE_DEBUG
printf("%s: link up\n", XNAME);
  713 #endif
  714 }
  716 int 
xge_init(struct ifnet *ifp)
  718 {
  719         struct xge_softc *sc = ifp->if_softc;
uint64_t val;
  721         int s;
s = splnet();
  725         /*
  726          * Cancel any pending I/O
  727          */
xge_stop(ifp, 0);
  730         /* 31+32, setup MAC config */
PIF_WKEY(MAC_CFG, TMAC_EN|RMAC_EN|TMAC_APPEND_PAD|RMAC_STRIP_FCS|
RMAC_BCAST_EN|RMAC_DISCARD_PFRM);
DELAY(1000);
  736         /* 54, ensure that the adapter is 'quiescent' */
val = PIF_RCSR(ADAPTER_STATUS);
  738         if ((val & QUIESCENT) != QUIESCENT) {
  739 #if 0
  740                 char buf[200];
  741 #endif
printf("%s: adapter not quiescent, aborting\n", XNAME);
val = (val & QUIESCENT) ^ QUIESCENT;
  744 #if 0
bitmask_snprintf(val, QUIESCENT_BMSK, buf, sizeof buf);
printf("%s: ADAPTER_STATUS missing bits %s\n", XNAME, buf);
  747 #endif
splx(s);
  749                 return (1);
  750         }
  752         /* disable VLAN tag stripping */
val = PIF_RCSR(RX_PA_CFG);
val &= ~STRIP_VLAN_TAG;
PIF_WCSR(RX_PA_CFG, val);
  757         /* set MRU */
  758 #ifdef XGE_JUMBO
PIF_WCSR(RMAC_MAX_PYLD_LEN, RMAC_PYLD_LEN(XGE_MAX_FRAMELEN));
  760 #else
PIF_WCSR(RMAC_MAX_PYLD_LEN, RMAC_PYLD_LEN(ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN));
  762 #endif
  764         /* 56, enable the transmit laser */
val = PIF_RCSR(ADAPTER_CONTROL);
val |= EOI_TX_ON;
PIF_WCSR(ADAPTER_CONTROL, val);
xge_enable(sc);
  771         /*
  772          * Enable all interrupts
  773          */
PIF_WCSR(TX_TRAFFIC_MASK, 0);
PIF_WCSR(RX_TRAFFIC_MASK, 0);
PIF_WCSR(GENERAL_INT_MASK, 0);
PIF_WCSR(TXPIC_INT_MASK, 0);
PIF_WCSR(RXPIC_INT_MASK, 0);
PIF_WCSR(MAC_INT_MASK, MAC_TMAC_INT); /* only from RMAC */
PIF_WCSR(MAC_RMAC_ERR_MASK, ~RMAC_LINK_STATE_CHANGE_INT);
xge_setpromisc(sc);
xge_setmulti(sc);
  787         /* Done... */
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
splx(s);
  793         return (0);
  794 }
  796 void
xge_stop(struct ifnet *ifp, int disable)
  798 {
  799         struct xge_softc *sc = ifp->if_softc;
uint64_t val;
ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
val = PIF_RCSR(ADAPTER_CONTROL);
val &= ~ADAPTER_EN;
PIF_WCSR(ADAPTER_CONTROL, val);
  808         while ((PIF_RCSR(ADAPTER_STATUS) & QUIESCENT) != QUIESCENT)
  809                 ;
  810 }
  812 void
xge_shutdown(void *pv)
  814 {
  815         struct xge_softc *sc = (struct xge_softc *)pv;
  816         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
xge_stop(ifp, 1);
  819 }
  821 int
xge_intr(void *pv)
  823 {
  824         struct xge_softc *sc = pv;
  825         struct txd *txd;
  826         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
bus_dmamap_t dmp;
uint64_t val;
  829         int i, lasttx, plen;
val = PIF_RCSR(GENERAL_INT_STATUS);
  832         if (val == 0)
  833                 return (0); /* no interrupt here */
PIF_WCSR(GENERAL_INT_STATUS, val);
  837         if ((val = PIF_RCSR(MAC_RMAC_ERR_REG)) & RMAC_LINK_STATE_CHANGE_INT) {
  838                 /* Wait for quiescence */
  839 #ifdef XGE_DEBUG
printf("%s: link down\n", XNAME);
  841 #endif
  842                 while ((PIF_RCSR(ADAPTER_STATUS) & QUIESCENT) != QUIESCENT)
  843                         ;
PIF_WCSR(MAC_RMAC_ERR_REG, RMAC_LINK_STATE_CHANGE_INT);
val = PIF_RCSR(ADAPTER_STATUS);
  847                 if ((val & (RMAC_REMOTE_FAULT|RMAC_LOCAL_FAULT)) == 0)
xge_enable(sc); /* Only if link restored */
  849         }
  851         if ((val = PIF_RCSR(TX_TRAFFIC_INT)))
PIF_WCSR(TX_TRAFFIC_INT, val); /* clear interrupt bits */
  853         /*
  854          * Collect sent packets.
  855          */
lasttx = sc->sc_lasttx;
  857         while ((i = NEXTTX(sc->sc_lasttx)) != sc->sc_nexttx) {
txd = sc->sc_txd[i];
dmp = sc->sc_txm[i];
bus_dmamap_sync(sc->sc_dmat, dmp, 0,
dmp->dm_mapsize,
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
  865                 if (txd->txd_control1 & TXD_CTL1_OWN) {
bus_dmamap_sync(sc->sc_dmat, dmp, 0,
dmp->dm_mapsize, BUS_DMASYNC_PREREAD);
  868                         break;
  869                 }
bus_dmamap_unload(sc->sc_dmat, dmp);
m_freem(sc->sc_txb[i]);
ifp->if_opackets++;
sc->sc_lasttx = i;
  874         }
  876         if (sc->sc_lasttx != lasttx)
ifp->if_flags &= ~IFF_OACTIVE;
  879         /* Try to get more packets on the wire */
xge_start(ifp);
  882         /* clear interrupt bits */
  883         if ((val = PIF_RCSR(RX_TRAFFIC_INT)))
PIF_WCSR(RX_TRAFFIC_INT, val);
  886         for (;;) {
  887                 struct rxdesc *rxd;
  888                 struct mbuf *m;
XGE_RXSYNC(sc->sc_nextrx,
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
rxd = XGE_RXD(sc->sc_nextrx);
  894                 if (rxd->rxd_control1 & RXD_CTL1_OWN) {
XGE_RXSYNC(sc->sc_nextrx, BUS_DMASYNC_PREREAD);
  896                         break;
  897                 }
  899                 /* got a packet */
m = sc->sc_rxb[sc->sc_nextrx];
  901 #if RX_MODE == RX_MODE_1
plen = m->m_len = RXD_CTL2_BUF0SIZ(rxd->rxd_control2);
  903 #elif RX_MODE == RX_MODE_3
  904 #error Fix rxmodes in xge_intr
  905 #elif RX_MODE == RX_MODE_5
plen = m->m_len = RXD_CTL2_BUF0SIZ(rxd->rxd_control2);
plen += m->m_next->m_len = RXD_CTL2_BUF1SIZ(rxd->rxd_control2);
plen += m->m_next->m_next->m_len =
RXD_CTL2_BUF2SIZ(rxd->rxd_control2);
plen += m->m_next->m_next->m_next->m_len =
RXD_CTL3_BUF3SIZ(rxd->rxd_control3);
plen += m->m_next->m_next->m_next->m_next->m_len =
RXD_CTL3_BUF4SIZ(rxd->rxd_control3);
  914 #endif
m->m_pkthdr.rcvif = ifp;
m->m_pkthdr.len = plen;
val = rxd->rxd_control1;
  920                 if (xge_add_rxbuf(sc, sc->sc_nextrx)) {
  921                         /* Failed, recycle this mbuf */
  922 #if RX_MODE == RX_MODE_1
rxd->rxd_control2 = RXD_MKCTL2(MCLBYTES, 0, 0);
rxd->rxd_control1 = RXD_CTL1_OWN;
  925 #elif RX_MODE == RX_MODE_3
  926 #elif RX_MODE == RX_MODE_5
  927 #endif
XGE_RXSYNC(sc->sc_nextrx,
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
ifp->if_ierrors++;
  931                         break;
  932                 }
ifp->if_ipackets++;
  936                 if (RXD_CTL1_PROTOS(val) & RXD_CTL1_P_IPv4)
m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK;
  938                 if (RXD_CTL1_PROTOS(val) & RXD_CTL1_P_TCP)
m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK;
  940                 if (RXD_CTL1_PROTOS(val) & RXD_CTL1_P_UDP)
m->m_pkthdr.csum_flags |= M_UDP_CSUM_IN_OK;
  943 #if NBPFILTER > 0
  944                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN);
  946 #endif /* NBPFILTER > 0 */
ether_input_mbuf(ifp, m);
  950                 if (++sc->sc_nextrx == NRXREAL)
sc->sc_nextrx = 0;
  952         }
  954         return (1);
  955 }
  957 int 
xge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
  959 {
  960         struct xge_softc *sc = ifp->if_softc;
  961         struct ifreq *ifr = (struct ifreq *) data;
  962         struct ifaddr *ifa = (struct ifaddr *)data;
  963         int s, error = 0;
s = splnet();
  967         if ((error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data)) > 0) {
splx(s);
  969                 return (error);
  970         }
  972         switch (cmd) {
  973         case SIOCSIFADDR:
ifp->if_flags |= IFF_UP;
  975                 if (!(ifp->if_flags & IFF_RUNNING))
xge_init(ifp);
  977 #ifdef INET
  978                 if (ifa->ifa_addr->sa_family == AF_INET)
arp_ifinit(&sc->sc_arpcom, ifa);
  980 #endif /* INET */
  981                 break;
  982         case SIOCSIFMTU:
  983                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ifp->if_hardmtu)
error = EINVAL;
  985                 else if (ifp->if_mtu != ifr->ifr_mtu)
ifp->if_mtu = ifr->ifr_mtu;
  987                 break;
  988         case SIOCSIFFLAGS:
  989                 if (ifp->if_flags & IFF_UP) {
  990                         if (ifp->if_flags & IFF_RUNNING &&
  991                             (ifp->if_flags ^ sc->xge_if_flags) &
IFF_PROMISC) {
xge_setpromisc(sc);
  994                         } else {
  995                                 if (!(ifp->if_flags & IFF_RUNNING))
xge_init(ifp);
  997                         }
  998                 } else {
  999                         if (ifp->if_flags & IFF_RUNNING)
xge_stop(ifp, 1);
 1001                 }
sc->xge_if_flags = ifp->if_flags;
 1003                 break;
 1004         case SIOCADDMULTI:
 1005         case SIOCDELMULTI:
error = (cmd == SIOCADDMULTI)
 1007                         ? ether_addmulti(ifr, &sc->sc_arpcom)
 1008                         : ether_delmulti(ifr, &sc->sc_arpcom);
 1010                 if (error == ENETRESET) {
 1011                         if (ifp->if_flags & IFF_RUNNING)
xge_setmulti(sc);
error = 0;
 1014                 }
 1015                 break;
 1016         case SIOCGIFMEDIA:
 1017         case SIOCSIFMEDIA:
error = ifmedia_ioctl(ifp, ifr, &sc->xena_media, cmd);
 1019                 break;
 1020         default:
error = ENOTTY;
 1022         }
splx(s);
 1026         return (error);
 1027 }
 1029 void
xge_setmulti(struct xge_softc *sc)
 1031 {
 1032         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
 1033         struct arpcom *ac = &sc->sc_arpcom;
 1034         struct ether_multi *enm;
 1035         struct ether_multistep step;
 1036         int i, numaddr = 1; /* first slot used for card unicast address */
uint64_t val;
ETHER_FIRST_MULTI(step, ac, enm);
 1040         while (enm != NULL) {
 1041                 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
 1042                         /* Skip ranges */
 1043                         goto allmulti;
 1044                 }
 1045                 if (numaddr == MAX_MCAST_ADDR)
 1046                         goto allmulti;
 1047                 for (val = 0, i = 0; i < ETHER_ADDR_LEN; i++) {
val <<= 8;
val |= enm->enm_addrlo[i];
 1050                 }
PIF_WCSR(RMAC_ADDR_DATA0_MEM, val << 16);
PIF_WCSR(RMAC_ADDR_DATA1_MEM, 0xFFFFFFFFFFFFFFFFULL);
PIF_WCSR(RMAC_ADDR_CMD_MEM, RMAC_ADDR_CMD_MEM_WE|
RMAC_ADDR_CMD_MEM_STR|RMAC_ADDR_CMD_MEM_OFF(numaddr));
 1055                 while (PIF_RCSR(RMAC_ADDR_CMD_MEM) & RMAC_ADDR_CMD_MEM_STR)
 1056                         ;
numaddr++;
ETHER_NEXT_MULTI(step, enm);
 1059         }
 1060         /* set the remaining entries to the broadcast address */
 1061         for (i = numaddr; i < MAX_MCAST_ADDR; i++) {
PIF_WCSR(RMAC_ADDR_DATA0_MEM, 0xffffffffffff0000ULL);
PIF_WCSR(RMAC_ADDR_DATA1_MEM, 0xFFFFFFFFFFFFFFFFULL);
PIF_WCSR(RMAC_ADDR_CMD_MEM, RMAC_ADDR_CMD_MEM_WE|
RMAC_ADDR_CMD_MEM_STR|RMAC_ADDR_CMD_MEM_OFF(i));
 1066                 while (PIF_RCSR(RMAC_ADDR_CMD_MEM) & RMAC_ADDR_CMD_MEM_STR)
 1067                         ;
 1068         }
ifp->if_flags &= ~IFF_ALLMULTI;
 1070         return;
allmulti:
 1073         /* Just receive everything with the multicast bit set */
ifp->if_flags |= IFF_ALLMULTI;
PIF_WCSR(RMAC_ADDR_DATA0_MEM, 0x8000000000000000ULL);
PIF_WCSR(RMAC_ADDR_DATA1_MEM, 0xF000000000000000ULL);
PIF_WCSR(RMAC_ADDR_CMD_MEM, RMAC_ADDR_CMD_MEM_WE|
RMAC_ADDR_CMD_MEM_STR|RMAC_ADDR_CMD_MEM_OFF(1));
 1079         while (PIF_RCSR(RMAC_ADDR_CMD_MEM) & RMAC_ADDR_CMD_MEM_STR)
 1080                 ;
 1081 }
 1083 void
xge_setpromisc(struct xge_softc *sc)
 1085 {
 1086         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
uint64_t val;
val = PIF_RCSR(MAC_CFG);
 1091         if (ifp->if_flags & IFF_PROMISC)
val |= RMAC_PROM_EN;
 1093         else
val &= ~RMAC_PROM_EN;
PIF_WCSR(MAC_CFG, val);
 1097 }
 1099 void 
xge_start(struct ifnet *ifp)
 1101 {
 1102         struct xge_softc *sc = ifp->if_softc;
 1103         struct txd *txd = NULL; /* XXX - gcc */
bus_dmamap_t dmp;
 1105         struct  mbuf *m;
uint64_t par, lcr;
 1107         int nexttx = 0, ntxd, error, i;
 1108 #if NVLAN > 0
 1109         struct ifvlan *ifv = NULL;
 1110 #endif
 1112         if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
 1113                 return;
par = lcr = 0;
 1116         for (;;) {
IFQ_POLL(&ifp->if_snd, m);
 1118                 if (m == NULL)
 1119                         break;  /* out of packets */
 1121                 if (sc->sc_nexttx == sc->sc_lasttx)
 1122                         break;  /* No more space */
nexttx = sc->sc_nexttx;
dmp = sc->sc_txm[nexttx];
 1127                 if ((error = bus_dmamap_load_mbuf(sc->sc_dmat, dmp, m,
BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0) {
printf("%s: bus_dmamap_load_mbuf error %d\n",
XNAME, error);
 1131                         break;
 1132                 }
IFQ_DEQUEUE(&ifp->if_snd, m);
bus_dmamap_sync(sc->sc_dmat, dmp, 0, dmp->dm_mapsize,
BUS_DMASYNC_PREWRITE);
txd = sc->sc_txd[nexttx];
sc->sc_txb[nexttx] = m;
 1140                 for (i = 0; i < dmp->dm_nsegs; i++) {
 1141                         if (dmp->dm_segs[i].ds_len == 0)
 1142                                 continue;
txd->txd_control1 = dmp->dm_segs[i].ds_len;
txd->txd_control2 = 0;
txd->txd_bufaddr = dmp->dm_segs[i].ds_addr;
txd++;
 1147                 }
ntxd = txd - sc->sc_txd[nexttx] - 1;
txd = sc->sc_txd[nexttx];
txd->txd_control1 |= TXD_CTL1_OWN|TXD_CTL1_GCF;
txd->txd_control2 = TXD_CTL2_UTIL;
 1153 #if NVLAN > 0
 1154                 if ((m->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
m->m_pkthdr.rcvif != NULL) {
ifv = m->m_pkthdr.rcvif->if_softc;
txd->txd_control2 |= TXD_CTL2_VLANE;
txd->txd_control2 |= TXD_CTL2_VLANT(ifv->ifv_tag);
 1160                 }
 1161 #endif
 1163                 if (m->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT)
txd->txd_control2 |= TXD_CTL2_CIPv4;
 1165                 if (m->m_pkthdr.csum_flags & M_TCPV4_CSUM_OUT)
txd->txd_control2 |= TXD_CTL2_CTCP;
 1167                 if (m->m_pkthdr.csum_flags & M_UDPV4_CSUM_OUT)
txd->txd_control2 |= TXD_CTL2_CUDP;
txd[ntxd].txd_control1 |= TXD_CTL1_GCL;
bus_dmamap_sync(sc->sc_dmat, dmp, 0, dmp->dm_mapsize,
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
par = sc->sc_txdp[nexttx];
lcr = TXDL_NUMTXD(ntxd) | TXDL_LGC_FIRST | TXDL_LGC_LAST;
TXP_WCSR(TXDL_PAR, par);
TXP_WCSR(TXDL_LCR, lcr);
 1180 #if NBPFILTER > 0
 1181                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT);
 1183 #endif /* NBPFILTER > 0 */
sc->sc_nexttx = NEXTTX(nexttx);
 1186         }
 1187 }
 1189 /*
 1190  * Allocate DMA memory for transmit descriptor fragments.
 1191  * Only one map is used for all descriptors.
 1192  */
 1193 int
xge_alloc_txmem(struct xge_softc *sc)
 1195 {
 1196         struct txd *txp;
bus_dma_segment_t seg;
bus_addr_t txdp;
caddr_t kva;
 1200         int i, rseg, state;
 1202 #define TXMAPSZ (NTXDESCS*NTXFRAGS*sizeof(struct txd))
state = 0;
 1204         if (bus_dmamem_alloc(sc->sc_dmat, TXMAPSZ, PAGE_SIZE, 0,
 1205             &seg, 1, &rseg, BUS_DMA_NOWAIT))
 1206                 goto err;
state++;
 1208         if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, TXMAPSZ, &kva,
BUS_DMA_NOWAIT))
 1210                 goto err;
state++;
 1213         if (bus_dmamap_create(sc->sc_dmat, TXMAPSZ, 1, TXMAPSZ, 0,
BUS_DMA_NOWAIT, &sc->sc_txmap))
 1215                 goto err;
state++;
 1217         if (bus_dmamap_load(sc->sc_dmat, sc->sc_txmap,
kva, TXMAPSZ, NULL, BUS_DMA_NOWAIT))
 1219                 goto err;
 1221         /* setup transmit array pointers */
txp = (struct txd *)kva;
txdp = seg.ds_addr;
 1224         for (txp = (struct txd *)kva, i = 0; i < NTXDESCS; i++) {
sc->sc_txd[i] = txp;
sc->sc_txdp[i] = txdp;
txp += NTXFRAGS;
txdp += (NTXFRAGS * sizeof(struct txd));
 1229         }
 1231         return (0);
err:
 1234         if (state > 2)
bus_dmamap_destroy(sc->sc_dmat, sc->sc_txmap);
 1236         if (state > 1)
bus_dmamem_unmap(sc->sc_dmat, kva, TXMAPSZ);
 1238         if (state > 0)
bus_dmamem_free(sc->sc_dmat, &seg, rseg);
 1240         return (ENOBUFS);
 1241 }
 1243 /*
 1244  * Allocate DMA memory for receive descriptor,
 1245  * only one map is used for all descriptors.
 1246  * link receive descriptor pages together.
 1247  */
 1248 int
xge_alloc_rxmem(struct xge_softc *sc)
 1250 {
 1251         struct rxd_4k *rxpp;
bus_dma_segment_t seg;
caddr_t kva;
 1254         int i, rseg, state;
 1256         /* sanity check */
 1257         if (sizeof(struct rxd_4k) != XGE_PAGE) {
printf("bad compiler struct alignment, %d != %d\n",
 1259                     (int)sizeof(struct rxd_4k), XGE_PAGE);
 1260                 return (EINVAL);
 1261         }
state = 0;
 1264         if (bus_dmamem_alloc(sc->sc_dmat, RXMAPSZ, PAGE_SIZE, 0,
 1265             &seg, 1, &rseg, BUS_DMA_NOWAIT))
 1266                 goto err;
state++;
 1268         if (bus_dmamem_map(sc->sc_dmat, &seg, rseg, RXMAPSZ, &kva,
BUS_DMA_NOWAIT))
 1270                 goto err;
state++;
 1273         if (bus_dmamap_create(sc->sc_dmat, RXMAPSZ, 1, RXMAPSZ, 0,
BUS_DMA_NOWAIT, &sc->sc_rxmap))
 1275                 goto err;
state++;
 1277         if (bus_dmamap_load(sc->sc_dmat, sc->sc_rxmap,
kva, RXMAPSZ, NULL, BUS_DMA_NOWAIT))
 1279                 goto err;
 1281         /* setup receive page link pointers */
 1282         for (rxpp = (struct rxd_4k *)kva, i = 0; i < NRXPAGES; i++, rxpp++) {
sc->sc_rxd_4k[i] = rxpp;
rxpp->r4_next = (uint64_t)sc->sc_rxmap->dm_segs[0].ds_addr +
 1285                     (i*sizeof(struct rxd_4k)) + sizeof(struct rxd_4k);
 1286         }
sc->sc_rxd_4k[NRXPAGES-1]->r4_next = 
 1288             (uint64_t)sc->sc_rxmap->dm_segs[0].ds_addr;
 1290         return (0);
err:
 1293         if (state > 2)
bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxmap);
 1295         if (state > 1)
bus_dmamem_unmap(sc->sc_dmat, kva, RXMAPSZ);
 1297         if (state > 0)
bus_dmamem_free(sc->sc_dmat, &seg, rseg);
 1299         return (ENOBUFS);
 1300 }
 1303 /*
 1304  * Add a new mbuf chain to descriptor id.
 1305  */
 1306 int
xge_add_rxbuf(struct xge_softc *sc, int id)
 1308 {
 1309         struct rxdesc *rxd;
 1310         struct mbuf *m[5];
 1311         int page, desc, error;
 1312 #if RX_MODE == RX_MODE_5
 1313         int i;
 1314 #endif
page = id/NDESC_BUFMODE;
desc = id%NDESC_BUFMODE;
rxd = &sc->sc_rxd_4k[page]->r4_rxd[desc];
 1321         /*
 1322          * Allocate mbufs.
 1323          * Currently five mbufs and two clusters are used,
 1324          * the hardware will put (ethernet, ip, tcp/udp) headers in
 1325          * their own buffer and the clusters are only used for data.
 1326          */
 1327 #if RX_MODE == RX_MODE_1
MGETHDR(m[0], M_DONTWAIT, MT_DATA);
 1329         if (m[0] == NULL)
 1330                 return (ENOBUFS);
MCLGET(m[0], M_DONTWAIT);
 1332         if ((m[0]->m_flags & M_EXT) == 0) {
m_freem(m[0]);
 1334                 return (ENOBUFS);
 1335         }
m[0]->m_len = m[0]->m_pkthdr.len = m[0]->m_ext.ext_size;
 1337 #elif RX_MODE == RX_MODE_3
 1338 #error missing rxmode 3.
 1339 #elif RX_MODE == RX_MODE_5
MGETHDR(m[0], M_DONTWAIT, MT_DATA);
 1341         for (i = 1; i < 5; i++) {
MGET(m[i], M_DONTWAIT, MT_DATA);
 1343         }
 1344         if (m[3])
MCLGET(m[3], M_DONTWAIT);
 1346         if (m[4])
MCLGET(m[4], M_DONTWAIT);
 1348         if (!m[0] || !m[1] || !m[2] || !m[3] || !m[4] || 
 1349             ((m[3]->m_flags & M_EXT) == 0) || ((m[4]->m_flags & M_EXT) == 0)) {
 1350                 /* Out of something */
 1351                 for (i = 0; i < 5; i++)
 1352                         if (m[i] != NULL)
m_free(m[i]);
 1354                 return (ENOBUFS);
 1355         }
 1356         /* Link'em together */
m[0]->m_next = m[1];
m[1]->m_next = m[2];
m[2]->m_next = m[3];
m[3]->m_next = m[4];
 1361 #else
 1362 #error bad mode RX_MODE
 1363 #endif
 1365         if (sc->sc_rxb[id])
bus_dmamap_unload(sc->sc_dmat, sc->sc_rxm[id]);
sc->sc_rxb[id] = m[0];
error = bus_dmamap_load_mbuf(sc->sc_dmat, sc->sc_rxm[id], m[0],
BUS_DMA_READ|BUS_DMA_NOWAIT);
 1371         if (error)
 1372                 return (error);
bus_dmamap_sync(sc->sc_dmat, sc->sc_rxm[id], 0,
sc->sc_rxm[id]->dm_mapsize, BUS_DMASYNC_PREREAD);
 1376 #if RX_MODE == RX_MODE_1
rxd->rxd_control2 = RXD_MKCTL2(m[0]->m_len, 0, 0);
rxd->rxd_buf0 = (uint64_t)sc->sc_rxm[id]->dm_segs[0].ds_addr;
rxd->rxd_control1 = RXD_CTL1_OWN;
 1380 #elif RX_MODE == RX_MODE_3
 1381 #elif RX_MODE == RX_MODE_5
rxd->rxd_control3 = RXD_MKCTL3(0, m[3]->m_len, m[4]->m_len);
rxd->rxd_control2 = RXD_MKCTL2(m[0]->m_len, m[1]->m_len, m[2]->m_len);
rxd->rxd_buf0 = (uint64_t)sc->sc_rxm[id]->dm_segs[0].ds_addr;
rxd->rxd_buf1 = (uint64_t)sc->sc_rxm[id]->dm_segs[1].ds_addr;
rxd->rxd_buf2 = (uint64_t)sc->sc_rxm[id]->dm_segs[2].ds_addr;
rxd->rxd_buf3 = (uint64_t)sc->sc_rxm[id]->dm_segs[3].ds_addr;
rxd->rxd_buf4 = (uint64_t)sc->sc_rxm[id]->dm_segs[4].ds_addr;
rxd->rxd_control1 = RXD_CTL1_OWN;
 1390 #endif
XGE_RXSYNC(id, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 1393         return (0);
 1394 }
 1396 /*
 1397  * This magic comes from the FreeBSD driver.
 1398  */
 1399 int
xge_setup_xgxs_xena(struct xge_softc *sc)
 1401 {
 1402         /* The magic numbers are described in the users guide */
 1404         /* Writing to MDIO 0x8000 (Global Config 0) */
PIF_WCSR(DTX_CONTROL, 0x8000051500000000ULL); DELAY(50);
PIF_WCSR(DTX_CONTROL, 0x80000515000000E0ULL); DELAY(50);
PIF_WCSR(DTX_CONTROL, 0x80000515D93500E4ULL); DELAY(50);
 1409         /* Writing to MDIO 0x8000 (Global Config 1) */
PIF_WCSR(DTX_CONTROL, 0x8001051500000000ULL); DELAY(50);
PIF_WCSR(DTX_CONTROL, 0x80010515000000e0ULL); DELAY(50);
PIF_WCSR(DTX_CONTROL, 0x80010515001e00e4ULL); DELAY(50);
 1414         /* Reset the Gigablaze */
PIF_WCSR(DTX_CONTROL, 0x8002051500000000ULL); DELAY(50);
PIF_WCSR(DTX_CONTROL, 0x80020515000000E0ULL); DELAY(50);
PIF_WCSR(DTX_CONTROL, 0x80020515F21000E4ULL); DELAY(50);
 1419         /* read the pole settings */
PIF_WCSR(DTX_CONTROL, 0x8000051500000000ULL); DELAY(50);
PIF_WCSR(DTX_CONTROL, 0x80000515000000e0ULL); DELAY(50);
PIF_WCSR(DTX_CONTROL, 0x80000515000000ecULL); DELAY(50);
PIF_WCSR(DTX_CONTROL, 0x8001051500000000ULL); DELAY(50);
PIF_WCSR(DTX_CONTROL, 0x80010515000000e0ULL); DELAY(50);
PIF_WCSR(DTX_CONTROL, 0x80010515000000ecULL); DELAY(50);
PIF_WCSR(DTX_CONTROL, 0x8002051500000000ULL); DELAY(50);
PIF_WCSR(DTX_CONTROL, 0x80020515000000e0ULL); DELAY(50);
PIF_WCSR(DTX_CONTROL, 0x80020515000000ecULL); DELAY(50);
 1432         /* Workaround for TX Lane XAUI initialization error.
 1433            Read Xpak PHY register 24 for XAUI lane status */
PIF_WCSR(DTX_CONTROL, 0x0018040000000000ULL); DELAY(50);
PIF_WCSR(DTX_CONTROL, 0x00180400000000e0ULL); DELAY(50);
PIF_WCSR(DTX_CONTROL, 0x00180400000000ecULL); DELAY(50);
 1438         /* 
 1439          * Reading the MDIO control with value 0x1804001c0F001c
 1440          * means the TxLanes were already in sync
 1441          * Reading the MDIO control with value 0x1804000c0x001c
 1442          * means some TxLanes are not in sync where x is a 4-bit
 1443          * value representing each lanes
 1444          */
 1445 #if 0
val = PIF_RCSR(MDIO_CONTROL);
 1447         if (val != 0x1804001c0F001cULL) {
printf("%s: MDIO_CONTROL: %llx != %llx\n", 
XNAME, val, 0x1804001c0F001cULL);
 1450                 return (1);
 1451         }
 1452 #endif
 1454         /* Set and remove the DTE XS INTLoopBackN */
PIF_WCSR(DTX_CONTROL, 0x0000051500000000ULL); DELAY(50);
PIF_WCSR(DTX_CONTROL, 0x00000515604000e0ULL); DELAY(50);
PIF_WCSR(DTX_CONTROL, 0x00000515604000e4ULL); DELAY(50);
PIF_WCSR(DTX_CONTROL, 0x00000515204000e4ULL); DELAY(50);
PIF_WCSR(DTX_CONTROL, 0x00000515204000ecULL); DELAY(50);
 1461 #if 0
 1462         /* Reading the DTX control register Should be 0x5152040001c */
val = PIF_RCSR(DTX_CONTROL);
 1464         if (val != 0x5152040001cULL) {
printf("%s: DTX_CONTROL: %llx != %llx\n", 
XNAME, val, 0x5152040001cULL);
 1467                 return (1);
 1468         }
 1469 #endif
PIF_WCSR(MDIO_CONTROL, 0x0018040000000000ULL); DELAY(50);
PIF_WCSR(MDIO_CONTROL, 0x00180400000000e0ULL); DELAY(50);
PIF_WCSR(MDIO_CONTROL, 0x00180400000000ecULL); DELAY(50);
 1475 #if 0
 1476         /* Reading the MIOD control should be 0x1804001c0f001c */
val = PIF_RCSR(MDIO_CONTROL);
 1478         if (val != 0x1804001c0f001cULL) {
printf("%s: MDIO_CONTROL2: %llx != %llx\n",
XNAME, val, 0x1804001c0f001cULL);
 1481                 return (1);
 1482         }
 1483 #endif
 1484         return (0);
 1485 }
 1487 int
xge_setup_xgxs_herc(struct xge_softc *sc)
 1489 {
 1490         int dtx_cnt = 0;
 1492         while (herc_dtx_cfg[dtx_cnt] != END_SIGN) {
PIF_WCSR(DTX_CONTROL, herc_dtx_cfg[dtx_cnt]);
DELAY(100);
dtx_cnt++;
 1496         }
 1498         return (0);
 1499 }