root/dev/pci/if_xgereg.h

INCLUDED FROM

    1 /*      $OpenBSD: if_xgereg.h,v 1.4 2007/02/27 22:39:39 kettenis Exp $  */
    2 /*      $NetBSD: if_xgereg.h,v 1.1 2005/09/09 10:30:27 ragge Exp $      */
    4 /*
    5  * Copyright (c) 2004, SUNET, Swedish University Computer Network.
    6  * All rights reserved.
    7  *
    8  * Written by Anders Magnusson for SUNET, Swedish University Computer Network.
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  * 3. All advertising materials mentioning features or use of this software
   19  *    must display the following acknowledgement:
   20  *      This product includes software developed for the NetBSD Project by
   21  *      SUNET, Swedish University Computer Network.
   22  * 4. The name of SUNET may not be used to endorse or promote products
   23  *    derived from this software without specific prior written permission.
   24  *
   25  * THIS SOFTWARE IS PROVIDED BY SUNET ``AS IS'' AND
   26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL SUNET
   29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   35  * POSSIBILITY OF SUCH DAMAGE.
   36  */
   38 /*
   39  * Defines for the Neterion Xframe adapter.
   40  */
   42 /* PCI address space */
   43 #define XGE_PIF_BAR     0x10
   44 #define XGE_TXP_BAR     0x18
   46 /* PIF register address calculation */
   47 #define DCSRB(x) (0x0000+(x))   /* 10GbE Device Control and Status Registers */
   48 #define PCIXB(x) (0x0800+(x))   /* PCI-X Interface Functional Registers */
   49 #define TDMAB(x) (0x1000+(x))   /* Transmit DMA Functional Registers */
   50 #define RDMAB(x) (0x1800+(x))   /* Receive DMA Functional Registers */
   51 #define MACRB(x) (0x2000+(x))   /* MAC functional registers */
   52 #define RLDRB(x) (0x2800+(x))   /* RLDRAM memory controller */
   53 #define XGXSB(x) (0x3000+(x))   /* XGXS functional Registers */
   55 /*
   56  * Control and Status Registers
   57  */
   58 #define GENERAL_INT_STATUS      DCSRB(0x0000)
   59 #define GENERAL_INT_MASK        DCSRB(0x0008)
   60 #define SW_RESET                DCSRB(0x0100)
   61 #define  XGXS_RESET(x)          ((uint64_t)(x) << 32)
   62 #define ADAPTER_STATUS          DCSRB(0x0108)
   63 #define  TDMA_READY             (1ULL<<63)
   64 #define  RDMA_READY             (1ULL<<62)
   65 #define  PFC_READY              (1ULL<<61)
   66 #define  TMAC_BUF_EMPTY         (1ULL<<60)
   67 #define  PIC_QUIESCENT          (1ULL<<58)
   68 #define  RMAC_REMOTE_FAULT      (1ULL<<57)
   69 #define  RMAC_LOCAL_FAULT       (1ULL<<56)
   70 #define  MC_DRAM_READY          (1ULL<<39)
   71 #define  MC_QUEUES_READY        (1ULL<<38)
   72 #define  RIC_RUNNING            (1ULL<<37)
   73 #define  M_PLL_LOCK             (1ULL<<33)
   74 #define  P_PLL_LOCK             (1ULL<<32)
   75 #define ADAPTER_CONTROL         DCSRB(0x0110)
   76 #define  ADAPTER_EN             (1ULL<<56)
   77 #define  EOI_TX_ON              (1ULL<<48)
   78 #define  LED_ON                 (1ULL<<40)
   79 #define  WAIT_INT_EN            (1ULL<<15)
   80 #define  ECC_ENABLE_N           (1ULL<<8)
   82 /* for debug of ADAPTER_STATUS */
   83 #define QUIESCENT (TDMA_READY|RDMA_READY|PFC_READY|TMAC_BUF_EMPTY|\
PIC_QUIESCENT|MC_DRAM_READY|MC_QUEUES_READY|M_PLL_LOCK|P_PLL_LOCK)
   85 #define QUIESCENT_BMSK  \
   86         "\177\20b\x3fTDMA_READY\0b\x3eRDMA_READY\0b\x3dPFC_READY\0" \
   87         "b\x3cTMAC_BUF_EMPTY\0b\x3aPIC_QUIESCENT\0\x39RMAC_REMOTE_FAULT\0" \
   88         "b\x38RMAC_LOCAL_FAULT\0b\x27MC_DRAM_READY\0b\x26MC_QUEUES_READY\0" \
   89         "b\x21M_PLL_LOCK\0b\x20P_PLL_LOCK"
   91 /*
   92  * PCI-X registers
   93  */
   94 /* Interrupt control registers */
   95 #define PIC_INT_STATUS          PCIXB(0)
   96 #define PIC_INT_MASK            PCIXB(0x008)
   97 #define TXPIC_INT_MASK          PCIXB(0x018)
   98 #define RXPIC_INT_MASK          PCIXB(0x030)
   99 #define FLASH_INT_MASK          PCIXB(0x048)
  100 #define MDIO_INT_MASK           PCIXB(0x060)
  101 #define IIC_INT_MASK            PCIXB(0x078)
  102 #define GPIO_INT_MASK           PCIXB(0x098)
  103 #define TX_TRAFFIC_INT          PCIXB(0x0e0)
  104 #define TX_TRAFFIC_MASK         PCIXB(0x0e8)
  105 #define RX_TRAFFIC_INT          PCIXB(0x0f0)
  106 #define RX_TRAFFIC_MASK         PCIXB(0x0f8)
  107 #define PIC_CONTROL             PCIXB(0x100)
  109 /* Byte swapping for little-endian */
  110 #define SWAPPER_CTRL            PCIXB(0x108)
  111 #define  PIF_R_FE               (1ULL<<63)
  112 #define  PIF_R_SE               (1ULL<<62)
  113 #define  PIF_W_FE               (1ULL<<55)
  114 #define  PIF_W_SE               (1ULL<<54)
  115 #define  TxP_FE                 (1ULL<<47)
  116 #define  TxP_SE                 (1ULL<<46)
  117 #define  TxD_R_FE               (1ULL<<45)
  118 #define  TxD_R_SE               (1ULL<<44)
  119 #define  TxD_W_FE               (1ULL<<43)
  120 #define  TxD_W_SE               (1ULL<<42)
  121 #define  TxF_R_FE               (1ULL<<41)
  122 #define  TxF_R_SE               (1ULL<<40)
  123 #define  RxD_R_FE               (1ULL<<31)
  124 #define  RxD_R_SE               (1ULL<<30)
  125 #define  RxD_W_FE               (1ULL<<29)
  126 #define  RxD_W_SE               (1ULL<<28)
  127 #define  RxF_W_FE               (1ULL<<27)
  128 #define  RxF_W_SE               (1ULL<<26)
  129 #define  XMSI_FE                (1ULL<<23)
  130 #define  XMSI_SE                (1ULL<<22)
  131 #define  STATS_FE               (1ULL<<15)
  132 #define  STATS_SE               (1ULL<<14)
  134 /* Diagnostic register to check byte-swapping conf */
  135 #define PIF_RD_SWAPPER_Fb       PCIXB(0x110)
  136 #define  SWAPPER_MAGIC          0x0123456789abcdefULL
  138 /* Stats registers */
  139 #define STAT_CFG                PCIXB(0x1d0)
  140 #define STAT_ADDR               PCIXB(0x1d8)
  142 /* DTE-XGXS Interface */
  143 #define MDIO_CONTROL            PCIXB(0x1e0)
  144 #define DTX_CONTROL             PCIXB(0x1e8)
  145 #define I2C_CONTROL             PCIXB(0x1f0)
  146 #define GPIO_CONTROL            PCIXB(0x1f8)
  148 /*
  149  * Transmit DMA registers.
  150  */
  151 #define TXDMA_INT_MASK          TDMAB(0x008)
  152 #define PFC_ERR_MASK            TDMAB(0x018)
  153 #define TDA_ERR_MASK            TDMAB(0x030)
  154 #define PCC_ERR_MASK            TDMAB(0x048)
  155 #define TTI_ERR_MASK            TDMAB(0x060)
  156 #define LSO_ERR_MASK            TDMAB(0x078)
  157 #define TPA_ERR_MASK            TDMAB(0x090)
  158 #define SM_ERR_MASK             TDMAB(0x0a8)
  160 /* Transmit FIFO config */
  161 #define TX_FIFO_P0              TDMAB(0x0108)
  162 #define TX_FIFO_P1              TDMAB(0x0110)
  163 #define TX_FIFO_P2              TDMAB(0x0118)
  164 #define TX_FIFO_P3              TDMAB(0x0120)
  165 #define  TX_FIFO_ENABLE         (1ULL<<63)
  166 #define  TX_FIFO_NUM0(x)        ((uint64_t)(x) << 56)
  167 #define  TX_FIFO_LEN0(x)        ((uint64_t)((x)-1) << 32)       
  168 #define  TX_FIFO_NUM1(x)        ((uint64_t)(x) << 24)
  169 #define  TX_FIFO_LEN1(x)        ((uint64_t)((x)-1) << 0)        
  171 /* Transmit interrupts */
  172 #define TTI_COMMAND_MEM         TDMAB(0x150)
  173 #define  TTI_CMD_MEM_WE         (1ULL<<56)
  174 #define  TTI_CMD_MEM_STROBE     (1ULL<<48)
  175 #define TTI_DATA1_MEM           TDMAB(0x158)
  176 #define  TX_TIMER_VAL(x)        ((uint64_t)(x) << 32)
  177 #define  TX_TIMER_AC            (1ULL<<25)
  178 #define  TX_TIMER_CI            (1ULL<<24)
  179 #define  TX_URNG_A(x)           ((uint64_t)(x) << 16)
  180 #define  TX_URNG_B(x)           ((uint64_t)(x) << 8)
  181 #define  TX_URNG_C(x)           ((uint64_t)(x) << 0)
  182 #define TTI_DATA2_MEM           TDMAB(0x160)
  183 #define  TX_UFC_A(x)            ((uint64_t)(x) << 48)
  184 #define  TX_UFC_B(x)            ((uint64_t)(x) << 32)
  185 #define  TX_UFC_C(x)            ((uint64_t)(x) << 16)
  186 #define  TX_UFC_D(x)            ((uint64_t)(x) << 0)
  189 /* Transmit protocol assist */
  190 #define TX_PA_CFG               TDMAB(0x0168)
  191 #define  TX_PA_CFG_IFR          (1ULL<<62)      /* Ignore frame error */
  192 #define  TX_PA_CFG_ISO          (1ULL<<61)      /* Ignore snap OUI */
  193 #define  TX_PA_CFG_ILC          (1ULL<<60)      /* Ignore LLC ctrl */
  194 #define  TX_PA_CFG_ILE          (1ULL<<57)      /* Ignore L2 error */
  196 /*
  197  * Transmit descriptor list (TxDL) pointer and control.
  198  * There may be up to 8192 TxDL's per FIFO, but with a NIC total
  199  * of 8192. The TxDL's are located in the NIC memory.
  200  * Each TxDL can have up to 256 Transmit descriptors (TxD)
  201  * that are located in host memory.
  202  *
  203  * The txdl struct fields must be written in order.
  204  */
  205 #ifdef notdef  /* Use bus_space stuff instead */
  206 struct txdl {
uint64_t txdl_pointer;  /* address of TxD's */
uint64_t txdl_control;
  209 };
  210 #endif
  211 #define TXDLOFF1(x)     (16*(x))        /* byte offset in txdl for list */
  212 #define TXDLOFF2(x)     (16*(x)+8)      /* byte offset in txdl for list */
  213 #define TXDL_NUMTXD(x)  ((uint64_t)(x) << 56)   /* # of TxD's in the list */
  214 #define TXDL_LGC_FIRST  (1ULL << 49)    /* First special list */
  215 #define TXDL_LGC_LAST   (1ULL << 48)    /* Last special list */
  216 #define TXDL_SFF        (1ULL << 40)    /* List is a special function list */
  217 #define TXDL_PAR        0               /* Pointer address register */
  218 #define TXDL_LCR        8               /* List control register */
  220 struct txd {
uint64_t txd_control1;
uint64_t txd_control2;
uint64_t txd_bufaddr;
uint64_t txd_hostctrl;
  225 };
  226 #define TXD_CTL1_OWN    (1ULL << 56)    /* Owner, 0 == host, 1 == NIC */
  227 #define TXD_CTL1_GCF    (1ULL << 41)    /* First frame or LSO */
  228 #define TXD_CTL1_GCL    (1ULL << 40)    /* Last frame or LSO */
  229 #define TXD_CTL1_LSO    (1ULL << 33)    /* LSO should be performed */
  230 #define TXD_CTL1_COF    (1ULL << 32)    /* UDP Checksum over fragments */
  231 #define TXD_CTL1_MSS(x) ((uint64_t)(x) << 16)
  233 #define TXD_CTL2_INTLST (1ULL << 16)    /* Per-list interrupt */
  234 #define TXD_CTL2_UTIL   (1ULL << 17)    /* Utilization interrupt */
  235 #define TXD_CTL2_CIPv4  (1ULL << 58)    /* Calculate IPv4 header checksum */
  236 #define TXD_CTL2_CTCP   (1ULL << 57)    /* Calculate TCP checksum */
  237 #define TXD_CTL2_CUDP   (1ULL << 56)    /* Calculate UDP checksum */
  238 #define TXD_CTL2_VLANE  (1ULL << 48)    /* Enable VLAN tag insertion */
  239 #define TXD_CTL2_VLANT(x) ((uint64_t)(x) << 32)
  241 /*
  242  * Receive DMA registers
  243  */
  244 /* Receive interrupt registers */
  245 #define RXDMA_INT_MASK          RDMAB(0x008)
  246 #define RDA_ERR_MASK            RDMAB(0x018)
  247 #define RC_ERR_MASK             RDMAB(0x030)
  248 #define PRC_PCIX_ERR_MASK       RDMAB(0x048)
  249 #define RPA_ERR_MASK            RDMAB(0x060)
  250 #define RTI_ERR_MASK            RDMAB(0x078)
  252 #define RX_QUEUE_PRIORITY       RDMAB(0x100)
  253 #define RX_W_ROUND_ROBIN_0      RDMAB(0x108)
  254 #define RX_W_ROUND_ROBIN_1      RDMAB(0x110)
  255 #define RX_W_ROUND_ROBIN_2      RDMAB(0x118)
  256 #define RX_W_ROUND_ROBIN_3      RDMAB(0x120)
  257 #define RX_W_ROUND_ROBIN_4      RDMAB(0x128)
  258 #define PRC_RXD0_0              RDMAB(0x130)
  259 #define PRC_CTRL_0              RDMAB(0x170)
  260 #define  RC_IN_SVC              (1ULL << 56)
  261 #define  RING_MODE_1            (0ULL << 48)
  262 #define  RING_MODE_3            (1ULL << 48)
  263 #define  RING_MODE_5            (2ULL << 48)
  264 #define  RC_NO_SNOOP_D          (1ULL << 41)
  265 #define  RC_NO_SNOOP_B          (1ULL << 40)
  266 #define PRC_ALARM_ACTION        RDMAB(0x1b0)
  267 #define RTI_COMMAND_MEM         RDMAB(0x1b8)
  268 #define  RTI_CMD_MEM_WE         (1ULL << 56)
  269 #define  RTI_CMD_MEM_STROBE     (1ULL << 48)
  270 #define RTI_DATA1_MEM           RDMAB(0x1c0)
  271 #define  RX_TIMER_VAL(x)        ((uint64_t)(x) << 32)
  272 #define  RX_TIMER_AC            (1ULL << 25)
  273 #define  RX_URNG_A(x)           ((uint64_t)(x) << 16)
  274 #define  RX_URNG_B(x)           ((uint64_t)(x) << 8)
  275 #define  RX_URNG_C(x)           ((uint64_t)(x) << 0)
  276 #define RTI_DATA2_MEM           RDMAB(0x1c8)
  277 #define  RX_UFC_A(x)            ((uint64_t)(x) << 48)
  278 #define  RX_UFC_B(x)            ((uint64_t)(x) << 32)
  279 #define  RX_UFC_C(x)            ((uint64_t)(x) << 16)
  280 #define  RX_UFC_D(x)            ((uint64_t)(x) << 0)
  281 #define RX_PA_CFG               RDMAB(0x1d0)
  282 #define  IGNORE_FRAME_ERROR     (1ULL << 62)
  283 #define  IGNORE_SNAP_OUI        (1ULL << 61)
  284 #define  IGNORE_LLC_CTRL        (1ULL << 60)
  285 #define  SCATTER_MODE           (1ULL << 57)
  286 #define  STRIP_VLAN_TAG         (1ULL << 48)
  288 /*
  289  * Receive descriptor (RxD) format.
  290  * There are three formats of receive descriptors, 1, 3 and 5 buffer format.
  291  */
  292 #define RX_MODE_1 1
  293 #define RX_MODE_3 3
  294 #define RX_MODE_5 5
  296 struct rxd1 {
uint64_t rxd_hcontrol;
uint64_t rxd_control1;
uint64_t rxd_control2;  
uint64_t rxd_buf0;
  301 };
  303 /* 4k struct for 5 buffer mode */
  304 #define NDESC_1BUFMODE          127     /* # desc/page for 5-buffer mode */
  305 struct rxd1_4k {
  306         struct rxd1 r4_rxd[NDESC_1BUFMODE];
uint64_t pad[3];
uint64_t r4_next; /* phys address of next 4k buffer */
  309 };
  311 struct rxd3 {
uint64_t rxd_hcontrol;
uint64_t rxd_control1;
uint64_t rxd_control2;
uint64_t rxd_buf0;
uint64_t rxd_buf1;      
uint64_t rxd_buf2;      
  318 };
  320 struct rxd5 {
uint64_t rxd_control3;
uint64_t rxd_control1;
uint64_t rxd_control2;
uint64_t rxd_buf0;
uint64_t rxd_buf1;
uint64_t rxd_buf2;
uint64_t rxd_buf3;
uint64_t rxd_buf4;
  329 };
  331 /* 4k struct for 5 buffer mode */
  332 #define NDESC_5BUFMODE          63      /* # desc/page for 5-buffer mode */
  333 #define XGE_PAGE                4096    /* page size used for receive */
  334 struct rxd5_4k {
  335         struct rxd5 r4_rxd[NDESC_5BUFMODE];
uint64_t pad[7];
uint64_t r4_next; /* phys address of next 4k buffer */
  338 };
  340 #define RXD_MKCTL3(h,bs3,bs4)   \
  341         (((uint64_t)(h) << 32) | ((uint64_t)(bs3) << 16) | (uint64_t)(bs4))
  342 #define RXD_MKCTL2(bs0,bs1,bs2) \
  343         (((uint64_t)(bs0) << 48) | ((uint64_t)(bs1) << 32) | \
  344         ((uint64_t)(bs2) << 16))
  346 #define RXD_CTL2_BUF0SIZ(x)     (((x) >> 48) & 0xffff)
  347 #define RXD_CTL2_BUF1SIZ(x)     (((x) >> 32) & 0xffff)
  348 #define RXD_CTL2_BUF2SIZ(x)     (((x) >> 16) & 0xffff)
  349 #define RXD_CTL3_BUF3SIZ(x)     (((x) >> 16) & 0xffff)
  350 #define RXD_CTL3_BUF4SIZ(x)     ((x) & 0xffff)
  351 #define RXD_CTL1_OWN            (1ULL << 56)
  352 #define RXD_CTL1_XCODE(x)       (((x) >> 48) & 0xf)     /* Status bits */
  353 #define  RXD_CTL1_X_OK          0
  354 #define  RXD_CTL1_X_PERR        1       /* Parity error */
  355 #define  RXD_CTL1_X_ABORT       2       /* Abort during xfer */
  356 #define  RXD_CTL1_X_PA          3       /* Parity error and abort */
  357 #define  RXD_CTL1_X_RDA         4       /* RDA failure */
  358 #define  RXD_CTL1_X_UP          5       /* Unknown protocol */
  359 #define  RXD_CTL1_X_FI          6       /* Frame integrity (FCS) error */
  360 #define  RXD_CTL1_X_BSZ         7       /* Buffer size error */
  361 #define  RXD_CTL1_X_ECC         8       /* Internal ECC */
  362 #define  RXD_CTL1_X_UNK         15      /* Unknown error */
  363 #define RXD_CTL1_PROTOS(x)      (((x) >> 32) & 0xff)
  364 #define  RXD_CTL1_P_VLAN        0x80    /* VLAN tagged */
  365 #define  RXD_CTL1_P_MSK         0x60    /* Mask for frame type */
  366 #define   RXD_CTL1_P_DIX        0x00
  367 #define   RXD_CTL1_P_LLC        0x20
  368 #define   RXD_CTL1_P_SNAP       0x40
  369 #define   RXD_CTL1_P_IPX        0x60
  370 #define  RXD_CTL1_P_IPv4        0x10
  371 #define  RXD_CTL1_P_IPv6        0x08
  372 #define  RXD_CTL1_P_IPFRAG      0x04
  373 #define  RXD_CTL1_P_TCP         0x02
  374 #define  RXD_CTL1_P_UDP         0x01
  375 #define RXD_CTL1_L3CSUM(x)      (((x) >> 16) & 0xffff)
  376 #define RXD_CTL1_L4CSUM(x)      ((x) & 0xffff)
  377 #define RXD_CTL2_VLANTAG(x)     ((x) & 0xffff)
  379 /*
  380  * MAC Configuration/Status
  381  */
  382 #define MAC_INT_STATUS          MACRB(0x000)
  383 #define  MAC_TMAC_INT           (1ULL<<63)
  384 #define  MAC_RMAC_INT           (1ULL<<62)
  385 #define MAC_INT_MASK            MACRB(0x008)
  386 #define MAC_TMAC_ERR_MASK       MACRB(0x018)
  387 #define MAC_RMAC_ERR_REG        MACRB(0x028)
  388 #define  RMAC_LINK_STATE_CHANGE_INT (1ULL<<32)
  389 #define MAC_RMAC_ERR_MASK       MACRB(0x030)
  391 #define MAC_CFG                 MACRB(0x0100)
  392 #define  TMAC_EN                (1ULL<<63)
  393 #define  RMAC_EN                (1ULL<<62)
  394 #define  UTILZATION_CALC_SEL    (1ULL<<61)
  395 #define  TMAC_LOOPBACK          (1ULL<<60)
  396 #define  TMAC_APPEND_PAD        (1ULL<<59)
  397 #define  RMAC_STRIP_FCS         (1ULL<<58)
  398 #define  RMAC_STRIP_PAD         (1ULL<<57)
  399 #define  RMAC_PROM_EN           (1ULL<<56)
  400 #define  RMAC_DISCARD_PFRM      (1ULL<<55)
  401 #define  RMAC_BCAST_EN          (1ULL<<54)
  402 #define  RMAC_ALL_ADDR_EN       (1ULL<<53)
  403 #define RMAC_MAX_PYLD_LEN       MACRB(0x0110)
  404 #define  RMAC_PYLD_LEN(x)       ((uint64_t)(x) << 48)
  405 #define RMAC_CFG_KEY            MACRB(0x0120)
  406 #define  RMAC_KEY_VALUE         (0x4c0dULL<<48)
  407 #define RMAC_ADDR_CMD_MEM       MACRB(0x0128)
  408 #define  RMAC_ADDR_CMD_MEM_WE   (1ULL<<56)
  409 #define  RMAC_ADDR_CMD_MEM_STR  (1ULL<<48)
  410 #define  RMAC_ADDR_CMD_MEM_OFF(x) ((uint64_t)(x) << 32)
  411 #define MAX_MCAST_ADDR          64      /* slots in mcast table */
  412 #define RMAC_ADDR_DATA0_MEM     MACRB(0x0130)
  413 #define RMAC_ADDR_DATA1_MEM     MACRB(0x0138)
  414 #define RMAC_PAUSE_CFG          MACRB(0x150)
  415 #define  RMAC_PAUSE_GEN_EN      (1ULL<<63)
  416 #define  RMAC_PAUSE_RCV_EN      (1ULL<<62)
  418 /*
  419  * RLDRAM registers.
  420  */
  421 #define MC_INT_MASK             RLDRB(0x008)
  422 #define MC_ERR_MASK             RLDRB(0x018)
  424 #define RX_QUEUE_CFG            RLDRB(0x100)
  425 #define  MC_QUEUE(q,s)          ((uint64_t)(s)<<(56-(q*8)))
  426 #define MC_RLDRAM_MRS           RLDRB(0x108)
  427 #define  MC_QUEUE_SIZE_ENABLE   (1ULL<<24)
  428 #define  MC_RLDRAM_MRS_ENABLE   (1ULL<<16)
  430 /*
  431  * XGXS registers.
  432  */
  433 /* XGXS control/statue */
  434 #define XGXS_INT_MASK           XGXSB(0x008)
  435 #define XGXS_TXGXS_ERR_MASK     XGXSB(0x018)
  436 #define XGXS_RXGXS_ERR_MASK     XGXSB(0x030)
  437 #define XGXS_CFG                XGXSB(0x0100)