PIF_WCSR 292 dev/pci/if_xge.c PIF_WCSR(RMAC_CFG_KEY, RMAC_KEY_VALUE); PIF_WCSR 297 dev/pci/if_xge.c PIF_WCSR(RMAC_CFG_KEY, RMAC_KEY_VALUE); PIF_WCSR 385 dev/pci/if_xge.c PIF_WCSR(SWAPPER_CTRL, val); PIF_WCSR 386 dev/pci/if_xge.c PIF_WCSR(SWAPPER_CTRL, val); PIF_WCSR 406 dev/pci/if_xge.c PIF_WCSR(GPIO_CONTROL, fix_mac[i]); PIF_WCSR 413 dev/pci/if_xge.c PIF_WCSR(SW_RESET, 0xa5a5a50000000000ULL); PIF_WCSR 424 dev/pci/if_xge.c PIF_WCSR(SWAPPER_CTRL, val); PIF_WCSR 425 dev/pci/if_xge.c PIF_WCSR(SWAPPER_CTRL, val); PIF_WCSR 445 dev/pci/if_xge.c PIF_WCSR(SW_RESET,val); PIF_WCSR 452 dev/pci/if_xge.c PIF_WCSR(SW_RESET, val); PIF_WCSR 480 dev/pci/if_xge.c PIF_WCSR(RMAC_ADDR_CMD_MEM, PIF_WCSR 497 dev/pci/if_xge.c PIF_WCSR(TX_FIFO_P0, TX_FIFO_LEN0(NTXDESCS)); PIF_WCSR 498 dev/pci/if_xge.c PIF_WCSR(TX_FIFO_P1, 0ULL); PIF_WCSR 499 dev/pci/if_xge.c PIF_WCSR(TX_FIFO_P2, 0ULL); PIF_WCSR 500 dev/pci/if_xge.c PIF_WCSR(TX_FIFO_P3, 0ULL); PIF_WCSR 507 dev/pci/if_xge.c PIF_WCSR(TX_FIFO_P0, val); PIF_WCSR 510 dev/pci/if_xge.c PIF_WCSR(TX_PA_CFG, PIF_WCSR 549 dev/pci/if_xge.c PIF_WCSR(RX_QUEUE_PRIORITY, 0ULL); /* only use one ring */ PIF_WCSR 552 dev/pci/if_xge.c PIF_WCSR(RX_W_ROUND_ROBIN_0, 0ULL); /* only use one ring */ PIF_WCSR 553 dev/pci/if_xge.c PIF_WCSR(RX_W_ROUND_ROBIN_1, 0ULL); PIF_WCSR 554 dev/pci/if_xge.c PIF_WCSR(RX_W_ROUND_ROBIN_2, 0ULL); PIF_WCSR 555 dev/pci/if_xge.c PIF_WCSR(RX_W_ROUND_ROBIN_3, 0ULL); PIF_WCSR 556 dev/pci/if_xge.c PIF_WCSR(RX_W_ROUND_ROBIN_4, 0ULL); PIF_WCSR 559 dev/pci/if_xge.c PIF_WCSR(PRC_RXD0_0, (uint64_t)sc->sc_rxmap->dm_segs[0].ds_addr); PIF_WCSR 563 dev/pci/if_xge.c PIF_WCSR(PRC_ALARM_ACTION, 0ULL); /* Default everything to retry */ PIF_WCSR 573 dev/pci/if_xge.c PIF_WCSR(PRC_CTRL_0, RC_IN_SVC|val); PIF_WCSR 580 dev/pci/if_xge.c PIF_WCSR(RX_QUEUE_CFG, MC_QUEUE(0, 64)); PIF_WCSR 583 dev/pci/if_xge.c PIF_WCSR(RX_QUEUE_CFG, MC_QUEUE(0, 32)); PIF_WCSR 599 dev/pci/if_xge.c PIF_WCSR(MC_RLDRAM_MRS, val); PIF_WCSR 606 dev/pci/if_xge.c PIF_WCSR(TTI_DATA1_MEM, TX_TIMER_VAL(0x1ff) | TX_TIMER_AC | PIF_WCSR 608 dev/pci/if_xge.c PIF_WCSR(TTI_DATA2_MEM, PIF_WCSR 610 dev/pci/if_xge.c PIF_WCSR(TTI_COMMAND_MEM, TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE); PIF_WCSR 615 dev/pci/if_xge.c PIF_WCSR(RTI_DATA1_MEM, RX_TIMER_VAL(0x800) | RX_TIMER_AC | PIF_WCSR 617 dev/pci/if_xge.c PIF_WCSR(RTI_DATA2_MEM, PIF_WCSR 619 dev/pci/if_xge.c PIF_WCSR(RTI_COMMAND_MEM, RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE); PIF_WCSR 705 dev/pci/if_xge.c PIF_WCSR(ADAPTER_CONTROL, val); PIF_WCSR 710 dev/pci/if_xge.c PIF_WCSR(ADAPTER_CONTROL, val); PIF_WCSR 755 dev/pci/if_xge.c PIF_WCSR(RX_PA_CFG, val); PIF_WCSR 759 dev/pci/if_xge.c PIF_WCSR(RMAC_MAX_PYLD_LEN, RMAC_PYLD_LEN(XGE_MAX_FRAMELEN)); PIF_WCSR 761 dev/pci/if_xge.c PIF_WCSR(RMAC_MAX_PYLD_LEN, RMAC_PYLD_LEN(ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN)); PIF_WCSR 767 dev/pci/if_xge.c PIF_WCSR(ADAPTER_CONTROL, val); PIF_WCSR 774 dev/pci/if_xge.c PIF_WCSR(TX_TRAFFIC_MASK, 0); PIF_WCSR 775 dev/pci/if_xge.c PIF_WCSR(RX_TRAFFIC_MASK, 0); PIF_WCSR 776 dev/pci/if_xge.c PIF_WCSR(GENERAL_INT_MASK, 0); PIF_WCSR 777 dev/pci/if_xge.c PIF_WCSR(TXPIC_INT_MASK, 0); PIF_WCSR 778 dev/pci/if_xge.c PIF_WCSR(RXPIC_INT_MASK, 0); PIF_WCSR 780 dev/pci/if_xge.c PIF_WCSR(MAC_INT_MASK, MAC_TMAC_INT); /* only from RMAC */ PIF_WCSR 781 dev/pci/if_xge.c PIF_WCSR(MAC_RMAC_ERR_MASK, ~RMAC_LINK_STATE_CHANGE_INT); PIF_WCSR 806 dev/pci/if_xge.c PIF_WCSR(ADAPTER_CONTROL, val); PIF_WCSR 835 dev/pci/if_xge.c PIF_WCSR(GENERAL_INT_STATUS, val); PIF_WCSR 844 dev/pci/if_xge.c PIF_WCSR(MAC_RMAC_ERR_REG, RMAC_LINK_STATE_CHANGE_INT); PIF_WCSR 852 dev/pci/if_xge.c PIF_WCSR(TX_TRAFFIC_INT, val); /* clear interrupt bits */ PIF_WCSR 884 dev/pci/if_xge.c PIF_WCSR(RX_TRAFFIC_INT, val); PIF_WCSR 1051 dev/pci/if_xge.c PIF_WCSR(RMAC_ADDR_DATA0_MEM, val << 16); PIF_WCSR 1052 dev/pci/if_xge.c PIF_WCSR(RMAC_ADDR_DATA1_MEM, 0xFFFFFFFFFFFFFFFFULL); PIF_WCSR 1053 dev/pci/if_xge.c PIF_WCSR(RMAC_ADDR_CMD_MEM, RMAC_ADDR_CMD_MEM_WE| PIF_WCSR 1062 dev/pci/if_xge.c PIF_WCSR(RMAC_ADDR_DATA0_MEM, 0xffffffffffff0000ULL); PIF_WCSR 1063 dev/pci/if_xge.c PIF_WCSR(RMAC_ADDR_DATA1_MEM, 0xFFFFFFFFFFFFFFFFULL); PIF_WCSR 1064 dev/pci/if_xge.c PIF_WCSR(RMAC_ADDR_CMD_MEM, RMAC_ADDR_CMD_MEM_WE| PIF_WCSR 1075 dev/pci/if_xge.c PIF_WCSR(RMAC_ADDR_DATA0_MEM, 0x8000000000000000ULL); PIF_WCSR 1076 dev/pci/if_xge.c PIF_WCSR(RMAC_ADDR_DATA1_MEM, 0xF000000000000000ULL); PIF_WCSR 1077 dev/pci/if_xge.c PIF_WCSR(RMAC_ADDR_CMD_MEM, RMAC_ADDR_CMD_MEM_WE| PIF_WCSR 1096 dev/pci/if_xge.c PIF_WCSR(MAC_CFG, val); PIF_WCSR 1405 dev/pci/if_xge.c PIF_WCSR(DTX_CONTROL, 0x8000051500000000ULL); DELAY(50); PIF_WCSR 1406 dev/pci/if_xge.c PIF_WCSR(DTX_CONTROL, 0x80000515000000E0ULL); DELAY(50); PIF_WCSR 1407 dev/pci/if_xge.c PIF_WCSR(DTX_CONTROL, 0x80000515D93500E4ULL); DELAY(50); PIF_WCSR 1410 dev/pci/if_xge.c PIF_WCSR(DTX_CONTROL, 0x8001051500000000ULL); DELAY(50); PIF_WCSR 1411 dev/pci/if_xge.c PIF_WCSR(DTX_CONTROL, 0x80010515000000e0ULL); DELAY(50); PIF_WCSR 1412 dev/pci/if_xge.c PIF_WCSR(DTX_CONTROL, 0x80010515001e00e4ULL); DELAY(50); PIF_WCSR 1415 dev/pci/if_xge.c PIF_WCSR(DTX_CONTROL, 0x8002051500000000ULL); DELAY(50); PIF_WCSR 1416 dev/pci/if_xge.c PIF_WCSR(DTX_CONTROL, 0x80020515000000E0ULL); DELAY(50); PIF_WCSR 1417 dev/pci/if_xge.c PIF_WCSR(DTX_CONTROL, 0x80020515F21000E4ULL); DELAY(50); PIF_WCSR 1420 dev/pci/if_xge.c PIF_WCSR(DTX_CONTROL, 0x8000051500000000ULL); DELAY(50); PIF_WCSR 1421 dev/pci/if_xge.c PIF_WCSR(DTX_CONTROL, 0x80000515000000e0ULL); DELAY(50); PIF_WCSR 1422 dev/pci/if_xge.c PIF_WCSR(DTX_CONTROL, 0x80000515000000ecULL); DELAY(50); PIF_WCSR 1424 dev/pci/if_xge.c PIF_WCSR(DTX_CONTROL, 0x8001051500000000ULL); DELAY(50); PIF_WCSR 1425 dev/pci/if_xge.c PIF_WCSR(DTX_CONTROL, 0x80010515000000e0ULL); DELAY(50); PIF_WCSR 1426 dev/pci/if_xge.c PIF_WCSR(DTX_CONTROL, 0x80010515000000ecULL); DELAY(50); PIF_WCSR 1428 dev/pci/if_xge.c PIF_WCSR(DTX_CONTROL, 0x8002051500000000ULL); DELAY(50); PIF_WCSR 1429 dev/pci/if_xge.c PIF_WCSR(DTX_CONTROL, 0x80020515000000e0ULL); DELAY(50); PIF_WCSR 1430 dev/pci/if_xge.c PIF_WCSR(DTX_CONTROL, 0x80020515000000ecULL); DELAY(50); PIF_WCSR 1434 dev/pci/if_xge.c PIF_WCSR(DTX_CONTROL, 0x0018040000000000ULL); DELAY(50); PIF_WCSR 1435 dev/pci/if_xge.c PIF_WCSR(DTX_CONTROL, 0x00180400000000e0ULL); DELAY(50); PIF_WCSR 1436 dev/pci/if_xge.c PIF_WCSR(DTX_CONTROL, 0x00180400000000ecULL); DELAY(50); PIF_WCSR 1455 dev/pci/if_xge.c PIF_WCSR(DTX_CONTROL, 0x0000051500000000ULL); DELAY(50); PIF_WCSR 1456 dev/pci/if_xge.c PIF_WCSR(DTX_CONTROL, 0x00000515604000e0ULL); DELAY(50); PIF_WCSR 1457 dev/pci/if_xge.c PIF_WCSR(DTX_CONTROL, 0x00000515604000e4ULL); DELAY(50); PIF_WCSR 1458 dev/pci/if_xge.c PIF_WCSR(DTX_CONTROL, 0x00000515204000e4ULL); DELAY(50); PIF_WCSR 1459 dev/pci/if_xge.c PIF_WCSR(DTX_CONTROL, 0x00000515204000ecULL); DELAY(50); PIF_WCSR 1471 dev/pci/if_xge.c PIF_WCSR(MDIO_CONTROL, 0x0018040000000000ULL); DELAY(50); PIF_WCSR 1472 dev/pci/if_xge.c PIF_WCSR(MDIO_CONTROL, 0x00180400000000e0ULL); DELAY(50); PIF_WCSR 1473 dev/pci/if_xge.c PIF_WCSR(MDIO_CONTROL, 0x00180400000000ecULL); DELAY(50); PIF_WCSR 1493 dev/pci/if_xge.c PIF_WCSR(DTX_CONTROL, herc_dtx_cfg[dtx_cnt]);