csr 97 arch/i386/pci/gscpm.c pcireg_t csr, acpibase;
csr 104 arch/i386/pci/gscpm.c csr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);
csr 106 arch/i386/pci/gscpm.c csr | PCI_COMMAND_IO_ENABLE);
csr 112 dev/cardbus/ehci_cardbus.c cardbusreg_t csr;
csr 137 dev/cardbus/ehci_cardbus.c csr = cardbus_conf_read(cc, cf, ca->ca_tag,
csr 140 dev/cardbus/ehci_cardbus.c csr | CARDBUS_COMMAND_MASTER_ENABLE
csr 111 dev/cardbus/ohci_cardbus.c cardbusreg_t csr;
csr 140 dev/cardbus/ohci_cardbus.c csr = cardbus_conf_read(cc, cf, ca->ca_tag,
csr 143 dev/cardbus/ohci_cardbus.c csr | CARDBUS_COMMAND_MASTER_ENABLE
csr 101 dev/cardbus/uhci_cardbus.c cardbusreg_t csr;
csr 129 dev/cardbus/uhci_cardbus.c csr = cardbus_conf_read(cc, cf, ca->ca_tag,
csr 132 dev/cardbus/uhci_cardbus.c csr | CARDBUS_COMMAND_MASTER_ENABLE
csr 97 dev/ic/lsi64854.c u_int32_t csr;
csr 127 dev/ic/lsi64854.c csr = L64854_GCSR(sc);
csr 128 dev/ic/lsi64854.c sc->sc_rev = csr & L64854_DEVID;
csr 152 dev/ic/lsi64854.c DPRINTF(LDB_ANY, (", burst 0x%x, csr 0x%x", sc->sc_burst, csr));
csr 175 dev/ic/lsi64854.c u_int32_t csr; \
csr 188 dev/ic/lsi64854.c csr = L64854_GCSR(sc); \
csr 190 dev/ic/lsi64854.c csr |= D_ESC_DRAIN; \
csr 192 dev/ic/lsi64854.c csr |= L64854_INVALIDATE; \
csr 194 dev/ic/lsi64854.c L64854_SCSR(sc,csr); \
csr 204 dev/ic/lsi64854.c u_int32_t csr; \
csr 212 dev/ic/lsi64854.c csr = L64854_GCSR(sc); \
csr 213 dev/ic/lsi64854.c csr &= ~(L64854_WRITE|L64854_EN_DMA); /* no-ops on ENET */ \
csr 214 dev/ic/lsi64854.c csr |= L64854_INVALIDATE; /* XXX FAS ? */ \
csr 215 dev/ic/lsi64854.c L64854_SCSR(sc,csr); \
csr 222 dev/ic/lsi64854.c u_int32_t csr;
csr 225 dev/ic/lsi64854.c csr = L64854_GCSR(sc);
csr 227 dev/ic/lsi64854.c DPRINTF(LDB_ANY, ("lsi64854_reset: csr 0x%x\n", csr));
csr 236 dev/ic/lsi64854.c L64854_SCSR(sc, csr | D_HW_RESET_FAS366);
csr 239 dev/ic/lsi64854.c csr |= L64854_RESET; /* reset DMA */
csr 240 dev/ic/lsi64854.c L64854_SCSR(sc, csr);
csr 244 dev/ic/lsi64854.c csr = L64854_GCSR(sc);
csr 245 dev/ic/lsi64854.c csr &= ~L64854_RESET; /* de-assert reset line */
csr 246 dev/ic/lsi64854.c L64854_SCSR(sc, csr);
csr 249 dev/ic/lsi64854.c csr = L64854_GCSR(sc);
csr 250 dev/ic/lsi64854.c csr |= L64854_INT_EN; /* enable interrupts */
csr 253 dev/ic/lsi64854.c csr |= D_TWO_CYCLE;
csr 255 dev/ic/lsi64854.c csr |= D_FASTER;
csr 262 dev/ic/lsi64854.c csr &= ~L64854_BURST_SIZE;
csr 264 dev/ic/lsi64854.c csr |= L64854_BURST_32;
csr 266 dev/ic/lsi64854.c csr |= L64854_BURST_16;
csr 268 dev/ic/lsi64854.c csr |= L64854_BURST_0;
csr 272 dev/ic/lsi64854.c csr |= D_ESC_AUTODRAIN; /* Auto-drain */
csr 274 dev/ic/lsi64854.c csr &= ~D_ESC_BURST;
csr 276 dev/ic/lsi64854.c csr |= D_ESC_BURST;
csr 281 dev/ic/lsi64854.c L64854_SCSR(sc, csr);
csr 285 dev/ic/lsi64854.c sc->sc_dmactl = csr;
csr 289 dev/ic/lsi64854.c DPRINTF(LDB_ANY, ("lsi64854_reset: done, csr 0x%x\n", csr));
csr 305 dev/ic/lsi64854.c u_int32_t csr;
csr 364 dev/ic/lsi64854.c csr = L64854_GCSR(sc);
csr 367 dev/ic/lsi64854.c csr |= L64854_WRITE;
csr 369 dev/ic/lsi64854.c csr &= ~L64854_WRITE;
csr 370 dev/ic/lsi64854.c csr |= L64854_INT_EN;
csr 373 dev/ic/lsi64854.c csr |= (D_DSBL_SCSI_DRN | D_EN_DMA);
csr 376 dev/ic/lsi64854.c L64854_SCSR(sc, csr);
csr 396 dev/ic/lsi64854.c u_int32_t csr;
csr 398 dev/ic/lsi64854.c csr = L64854_GCSR(sc);
csr 402 dev/ic/lsi64854.c csr, DDMACSR_BITS));
csr 404 dev/ic/lsi64854.c if (csr & (D_ERR_PEND|D_SLAVE_ERR)) {
csr 405 dev/ic/lsi64854.c snprintf(bits, sizeof(bits), "%b", csr, DDMACSR_BITS);
csr 407 dev/ic/lsi64854.c csr &= ~D_EN_DMA; /* Stop DMA */
csr 409 dev/ic/lsi64854.c csr |= D_INVALIDATE|D_SLAVE_ERR;
csr 410 dev/ic/lsi64854.c L64854_SCSR(sc, csr);
csr 421 dev/ic/lsi64854.c csr &= ~D_EN_DMA;
csr 422 dev/ic/lsi64854.c L64854_SCSR(sc, csr);
csr 442 dev/ic/lsi64854.c if (!(csr & D_WRITE) &&
csr 490 dev/ic/lsi64854.c (csr & D_WRITE) != 0
csr 520 dev/ic/lsi64854.c u_int32_t csr;
csr 524 dev/ic/lsi64854.c csr = L64854_GCSR(sc);
csr 527 dev/ic/lsi64854.c rv = ((csr & E_INT_PEND) != 0) ? 1 : 0;
csr 529 dev/ic/lsi64854.c if (csr & (E_ERR_PEND|E_SLAVE_ERR)) {
csr 530 dev/ic/lsi64854.c snprintf(bits, sizeof(bits), "%b", csr, EDMACSR_BITS);
csr 532 dev/ic/lsi64854.c csr &= ~L64854_EN_DMA; /* Stop DMA */
csr 534 dev/ic/lsi64854.c csr |= E_INVALIDATE|E_SLAVE_ERR;
csr 535 dev/ic/lsi64854.c L64854_SCSR(sc, csr);
csr 543 dev/ic/lsi64854.c csr |= E_DRAIN;
csr 544 dev/ic/lsi64854.c L64854_SCSR(sc, csr);
csr 563 dev/ic/lsi64854.c u_int32_t csr;
csr 604 dev/ic/lsi64854.c csr = L64854_GCSR(sc);
csr 605 dev/ic/lsi64854.c csr &= ~L64854_BURST_SIZE;
csr 607 dev/ic/lsi64854.c csr |= L64854_BURST_32;
csr 609 dev/ic/lsi64854.c csr |= L64854_BURST_16;
csr 611 dev/ic/lsi64854.c csr |= L64854_BURST_0;
csr 613 dev/ic/lsi64854.c csr |= P_EN_DMA|P_INT_EN|P_EN_CNT;
csr 617 dev/ic/lsi64854.c csr |= P_WRITE;
csr 619 dev/ic/lsi64854.c csr &= ~P_WRITE;
csr 621 dev/ic/lsi64854.c L64854_SCSR(sc, csr);
csr 634 dev/ic/lsi64854.c u_int32_t csr;
csr 636 dev/ic/lsi64854.c csr = L64854_GCSR(sc);
csr 640 dev/ic/lsi64854.c csr, PDMACSR_BITS));
csr 642 dev/ic/lsi64854.c if (csr & (P_ERR_PEND|P_SLAVE_ERR)) {
csr 646 dev/ic/lsi64854.c resid, csr, PDMACSR_BITS);
csr 647 dev/ic/lsi64854.c csr &= ~P_EN_DMA; /* Stop DMA */
csr 649 dev/ic/lsi64854.c csr |= P_INVALIDATE|P_SLAVE_ERR;
csr 650 dev/ic/lsi64854.c L64854_SCSR(sc, csr);
csr 654 dev/ic/lsi64854.c ret = (csr & P_INT_PEND) != 0;
csr 663 dev/ic/lsi64854.c csr &= ~D_EN_DMA;
csr 664 dev/ic/lsi64854.c L64854_SCSR(sc, csr);
csr 676 dev/ic/lsi64854.c (csr & D_WRITE) != 0
csr 76 dev/ic/lsi64854var.h #define L64854_SCSR(sc, csr) \
csr 77 dev/ic/lsi64854var.h bus_space_write_4((sc)->sc_bustag, (sc)->sc_regs, L64854_REG_CSR, csr)
csr 90 dev/ic/lsi64854var.h u_int32_t csr = L64854_GCSR(sc); \
csr 91 dev/ic/lsi64854var.h csr |= L64854_INT_EN; \
csr 92 dev/ic/lsi64854var.h L64854_SCSR(sc, csr); \
csr 98 dev/ic/lsi64854var.h u_int32_t csr = L64854_GCSR(sc); \
csr 99 dev/ic/lsi64854var.h csr |= D_EN_DMA; \
csr 100 dev/ic/lsi64854var.h L64854_SCSR(sc, csr); \
csr 148 dev/ic/mk48txx.c u_int8_t csr;
csr 153 dev/ic/mk48txx.c csr = bus_space_read_1(bt, bh, clkoff + MK48TXX_ICSR);
csr 154 dev/ic/mk48txx.c csr |= MK48TXX_CSR_READ;
csr 155 dev/ic/mk48txx.c bus_space_write_1(bt, bh, clkoff + MK48TXX_ICSR, csr);
csr 172 dev/ic/mk48txx.c csr = bus_space_read_1(bt, bh, clkoff + MK48TXX_ICSR);
csr 173 dev/ic/mk48txx.c csr &= ~MK48TXX_CSR_READ;
csr 174 dev/ic/mk48txx.c bus_space_write_1(bt, bh, clkoff + MK48TXX_ICSR, csr);
csr 201 dev/ic/mk48txx.c u_int8_t csr;
csr 213 dev/ic/mk48txx.c csr = bus_space_read_1(bt, bh, clkoff + MK48TXX_ICSR);
csr 214 dev/ic/mk48txx.c csr |= MK48TXX_CSR_WRITE;
csr 215 dev/ic/mk48txx.c bus_space_write_1(bt, bh, clkoff + MK48TXX_ICSR, csr);
csr 226 dev/ic/mk48txx.c csr = bus_space_read_1(bt, bh, clkoff + MK48TXX_ICSR);
csr 227 dev/ic/mk48txx.c csr &= ~MK48TXX_CSR_WRITE;
csr 228 dev/ic/mk48txx.c bus_space_write_1(bt, bh, clkoff + MK48TXX_ICSR, csr);
csr 148 dev/ic/pdqvar.h #define PDQ_CSR_WRITE(csr, name, data) PDQ_OS_IOWR_32((csr)->csr_bus, (csr)->csr_base, (csr)->name, data)
csr 149 dev/ic/pdqvar.h #define PDQ_CSR_READ(csr, name) PDQ_OS_IORD_32((csr)->csr_bus, (csr)->csr_base, (csr)->name)
csr 151 dev/ic/pdqvar.h #define PDQ_CSR_WRITE(csr, name, data) PDQ_OS_MEMWR_32((csr)->csr_bus, (csr)->csr_base, (csr)->name, data)
csr 152 dev/ic/pdqvar.h #define PDQ_CSR_READ(csr, name) PDQ_OS_MEMRD_32((csr)->csr_bus, (csr)->csr_base, (csr)->name)
csr 182 dev/ic/pdqvar.h #define PDQ_CSR_WRITE(csr, name, data) PDQ_OS_MEMWR_32((csr)->csr_bus, (csr)->name, 0, data)
csr 183 dev/ic/pdqvar.h #define PDQ_CSR_READ(csr, name) PDQ_OS_MEMRD_32((csr)->csr_bus, (csr)->name, 0)
csr 772 dev/ic/rtl81x9reg.h #define CSR_WRITE_RAW_4(sc, csr, val) \
csr 773 dev/ic/rtl81x9reg.h bus_space_write_raw_region_4(sc->rl_btag, sc->rl_bhandle, csr, val, 4)
csr 774 dev/ic/rtl81x9reg.h #define CSR_WRITE_4(sc, csr, val) \
csr 775 dev/ic/rtl81x9reg.h bus_space_write_4(sc->rl_btag, sc->rl_bhandle, csr, val)
csr 776 dev/ic/rtl81x9reg.h #define CSR_WRITE_2(sc, csr, val) \
csr 777 dev/ic/rtl81x9reg.h bus_space_write_2(sc->rl_btag, sc->rl_bhandle, csr, val)
csr 778 dev/ic/rtl81x9reg.h #define CSR_WRITE_1(sc, csr, val) \
csr 779 dev/ic/rtl81x9reg.h bus_space_write_1(sc->rl_btag, sc->rl_bhandle, csr, val)
csr 781 dev/ic/rtl81x9reg.h #define CSR_READ_4(sc, csr) \
csr 782 dev/ic/rtl81x9reg.h bus_space_read_4(sc->rl_btag, sc->rl_bhandle, csr)
csr 783 dev/ic/rtl81x9reg.h #define CSR_READ_2(sc, csr) \
csr 784 dev/ic/rtl81x9reg.h bus_space_read_2(sc->rl_btag, sc->rl_bhandle, csr)
csr 785 dev/ic/rtl81x9reg.h #define CSR_READ_1(sc, csr) \
csr 786 dev/ic/rtl81x9reg.h bus_space_read_1(sc->rl_btag, sc->rl_bhandle, csr)
csr 245 dev/mii/lxtphy.c int bmcr, bmsr, csr;
csr 255 dev/mii/lxtphy.c csr = PHY_READ(sc, MII_LXTPHY_CSR);
csr 256 dev/mii/lxtphy.c if (csr & CSR_LINK)
csr 276 dev/mii/lxtphy.c if (csr & CSR_SPEED)
csr 281 dev/mii/lxtphy.c if (csr & CSR_DUPLEX)
csr 196 dev/pci/ami_pci.c pcireg_t csr;
csr 199 dev/pci/ami_pci.c csr = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AMI_BAR);
csr 200 dev/pci/ami_pci.c if (pci_mapreg_map(pa, AMI_BAR, csr, 0,
csr 206 dev/pci/ami_pci.c if (PCI_MAPREG_TYPE(csr) == PCI_MAPREG_TYPE_IO) {
csr 239 dev/pci/ami_pci.c csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
csr 241 dev/pci/ami_pci.c if (ssp->id == csr) {
csr 268 dev/pci/ami_pci.c vp->id && vp->id != (csr & 0xffff); vp++);
csr 271 dev/pci/ami_pci.c (csr >> 16) & 0xffff);
csr 274 dev/pci/ami_pci.c csr);
csr 352 dev/pci/auich.c pcireg_t csr;
csr 368 dev/pci/auich.c csr = pci_conf_read(pa->pa_pc, pa->pa_tag, AUICH_CFG);
csr 370 dev/pci/auich.c csr | AUICH_CFG_IOSE);
csr 380 dev/pci/auich.c csr = pci_conf_read(pa->pa_pc, pa->pa_tag, AUICH_CFG);
csr 382 dev/pci/auich.c csr | AUICH_CFG_IOSE);
csr 95 dev/pci/if_de.c #define EMIT do { TULIP_CSR_WRITE(sc, csr_srom_mii, csr); tulip_delay_300ns(sc); } while (0)
csr 96 dev/pci/if_de.c #define MII_EMIT do { TULIP_CSR_WRITE(sc, csr_srom_mii, csr); tulip_delay_300ns(sc); } while (0)
csr 212 dev/pci/if_de.c void tulip_print_abnormal_interrupt(tulip_softc_t * const sc, u_int32_t csr);
csr 1605 dev/pci/if_de.c u_int32_t csr = TULIP_CSR_READ(sc, csr_gp);
csr 1606 dev/pci/if_de.c if ((csr & (TULIP_GP_SMC_9332_OK10|TULIP_GP_SMC_9332_OK100)) == (TULIP_GP_SMC_9332_OK10|TULIP_GP_SMC_9332_OK100)) {
csr 1609 dev/pci/if_de.c } else if ((csr & TULIP_GP_SMC_9332_OK10) == 0)
csr 1704 dev/pci/if_de.c u_int32_t csr = TULIP_CSR_READ(sc, csr_gp);
csr 1705 dev/pci/if_de.c if ((csr & (TULIP_GP_ZX34X_LNKFAIL|TULIP_GP_ZX34X_SYMDET|TULIP_GP_ZX34X_SIGDET)) == (TULIP_GP_ZX34X_LNKFAIL|TULIP_GP_ZX34X_SYMDET|TULIP_GP_ZX34X_SIGDET)) {
csr 1708 dev/pci/if_de.c } else if ((csr & TULIP_GP_ZX34X_LNKFAIL) == 0) {
csr 1775 dev/pci/if_de.c unsigned bit, csr;
csr 1777 dev/pci/if_de.c csr = SROMSEL ; EMIT;
csr 1778 dev/pci/if_de.c csr = SROMSEL | SROMRD; EMIT;
csr 1779 dev/pci/if_de.c csr ^= SROMCS; EMIT;
csr 1780 dev/pci/if_de.c csr ^= SROMCLKON; EMIT;
csr 1786 dev/pci/if_de.c csr ^= SROMCLKOFF; EMIT; /* clock low; data not valid */
csr 1787 dev/pci/if_de.c csr ^= SROMCLKON; EMIT; /* clock high; data valid */
csr 1789 dev/pci/if_de.c csr ^= SROMCLKOFF; EMIT;
csr 1790 dev/pci/if_de.c csr ^= SROMCS; EMIT;
csr 1791 dev/pci/if_de.c csr = 0; EMIT;
csr 1806 dev/pci/if_de.c unsigned lastbit, data, bits, bit, csr;
csr 1807 dev/pci/if_de.c csr = SROMSEL ; EMIT;
csr 1808 dev/pci/if_de.c csr = SROMSEL | SROMRD; EMIT;
csr 1809 dev/pci/if_de.c csr ^= SROMCSON; EMIT;
csr 1810 dev/pci/if_de.c csr ^= SROMCLKON; EMIT;
csr 1815 dev/pci/if_de.c csr ^= SROMCLKOFF; EMIT; /* clock low; data not valid */
csr 1817 dev/pci/if_de.c csr ^= SROMDOUT; EMIT; /* clock low; invert data */
csr 1821 dev/pci/if_de.c csr ^= SROMCLKON; EMIT; /* clock high; data valid */
csr 1824 dev/pci/if_de.c csr ^= SROMCLKOFF; EMIT;
csr 1828 dev/pci/if_de.c csr ^= SROMCLKON; EMIT; /* clock high; data valid */
csr 1830 dev/pci/if_de.c csr ^= SROMCLKOFF; EMIT; /* clock low; data not valid */
csr 1834 dev/pci/if_de.c csr = SROMSEL | SROMRD; EMIT;
csr 1835 dev/pci/if_de.c csr = 0; EMIT;
csr 1844 dev/pci/if_de.c unsigned csr = TULIP_CSR_READ(sc, csr_srom_mii) & (MII_RD|MII_DOUT|MII_CLK);
csr 1845 dev/pci/if_de.c unsigned lastbit = (csr & MII_DOUT) ? msb : 0;
csr 1847 dev/pci/if_de.c csr |= MII_WR; MII_EMIT; /* clock low; assert write */
csr 1852 dev/pci/if_de.c csr ^= MII_DOUT; MII_EMIT; /* clock low; invert data */
csr 1853 dev/pci/if_de.c csr ^= MII_CLKON; MII_EMIT; /* clock high; data valid */
csr 1855 dev/pci/if_de.c csr ^= MII_CLKOFF; MII_EMIT; /* clock low; data not valid */
csr 1862 dev/pci/if_de.c unsigned csr = TULIP_CSR_READ(sc, csr_srom_mii) & (MII_RD|MII_DOUT|MII_CLK);
csr 1865 dev/pci/if_de.c csr |= MII_DOUT; MII_EMIT; /* clock low; change data */
csr 1866 dev/pci/if_de.c csr ^= MII_CLKON; MII_EMIT; /* clock high; data valid */
csr 1867 dev/pci/if_de.c csr ^= MII_CLKOFF; MII_EMIT; /* clock low; data not valid */
csr 1868 dev/pci/if_de.c csr ^= MII_DOUT; MII_EMIT; /* clock low; change data */
csr 1870 dev/pci/if_de.c csr |= MII_RD; MII_EMIT; /* clock low; switch to read */
csr 1871 dev/pci/if_de.c csr ^= MII_CLKON; MII_EMIT; /* clock high; data valid */
csr 1872 dev/pci/if_de.c csr ^= MII_CLKOFF; MII_EMIT; /* clock low; data not valid */
csr 1879 dev/pci/if_de.c unsigned csr = TULIP_CSR_READ(sc, csr_srom_mii) & (MII_RD|MII_DOUT|MII_CLK);
csr 1884 dev/pci/if_de.c csr ^= MII_CLKON; MII_EMIT; /* clock high; data valid */
csr 1887 dev/pci/if_de.c csr ^= MII_CLKOFF; MII_EMIT; /* clock low; data not valid */
csr 1889 dev/pci/if_de.c csr ^= MII_RD; MII_EMIT; /* clock low; turn off read */
csr 1897 dev/pci/if_de.c unsigned csr = TULIP_CSR_READ(sc, csr_srom_mii) & (MII_RD|MII_DOUT|MII_CLK);
csr 1900 dev/pci/if_de.c csr &= ~(MII_RD|MII_CLK); MII_EMIT;
csr 1919 dev/pci/if_de.c unsigned csr;
csr 1921 dev/pci/if_de.c csr = TULIP_CSR_READ(sc, csr_srom_mii) & (MII_RD|MII_DOUT|MII_CLK);
csr 1922 dev/pci/if_de.c csr &= ~(MII_RD|MII_CLK); MII_EMIT;
csr 2609 dev/pci/if_de.c u_int32_t csr;
csr 2619 dev/pci/if_de.c while (((csr = TULIP_CSR_READ(sc, csr_enetrom)) & 0x80000000L) && cnt < 10000)
csr 2621 dev/pci/if_de.c sc->tulip_rombuf[idx] = csr & 0xFF;
csr 3594 dev/pci/if_de.c tulip_print_abnormal_interrupt(tulip_softc_t * const sc, u_int32_t csr)
csr 3602 dev/pci/if_de.c csr &= (1 << (sizeof(tulip_status_bits)/sizeof(tulip_status_bits[0]))) - 1;
csr 3604 dev/pci/if_de.c for (sep = " ", mask = 1; mask <= csr; mask <<= 1, msgp++) {
csr 3605 dev/pci/if_de.c if ((csr & mask) && *msgp != NULL) {
csr 3627 dev/pci/if_de.c u_int32_t csr;
csr 3629 dev/pci/if_de.c while ((csr = TULIP_CSR_READ(sc, csr_status)) & sc->tulip_intrmask) {
csr 3631 dev/pci/if_de.c TULIP_CSR_WRITE(sc, csr_status, csr);
csr 3633 dev/pci/if_de.c if (csr & TULIP_STS_SYSERROR) {
csr 3634 dev/pci/if_de.c sc->tulip_last_system_error = (csr & TULIP_STS_ERRORMASK) >> TULIP_STS_ERR_SHIFT;
csr 3648 dev/pci/if_de.c if (csr & (TULIP_STS_LINKPASS|TULIP_STS_LINKFAIL) & sc->tulip_intrmask) {
csr 3653 dev/pci/if_de.c (*sc->tulip_boardsw->bd_media_poll)(sc, csr & TULIP_STS_LINKFAIL
csr 3656 dev/pci/if_de.c csr &= ~TULIP_STS_ABNRMLINTR;
csr 3660 dev/pci/if_de.c if (csr & (TULIP_STS_RXINTR|TULIP_STS_RXNOBUF)) {
csr 3662 dev/pci/if_de.c if (csr & TULIP_STS_RXNOBUF)
csr 3689 dev/pci/if_de.c if (csr & TULIP_STS_ABNRMLINTR) {
csr 3690 dev/pci/if_de.c u_int32_t tmp = csr & sc->tulip_intrmask
csr 3692 dev/pci/if_de.c if (csr & TULIP_STS_TXUNDERFLOW) {
csr 30 dev/pci/if_devar.h #define TULIP_CSR_READ(sc, csr) \
csr 31 dev/pci/if_devar.h bus_space_read_4((sc)->tulip_bustag, (sc)->tulip_bushandle, (sc)->tulip_csrs.csr)
csr 32 dev/pci/if_devar.h #define TULIP_CSR_WRITE(sc, csr, val) \
csr 33 dev/pci/if_devar.h bus_space_write_4((sc)->tulip_bustag, (sc)->tulip_bushandle, (sc)->tulip_csrs.csr, (val))
csr 35 dev/pci/if_devar.h #define TULIP_CSR_READBYTE(sc, csr) \
csr 36 dev/pci/if_devar.h bus_space_read_1((sc)->tulip_bustag, (sc)->tulip_bushandle, (sc)->tulip_csrs.csr)
csr 37 dev/pci/if_devar.h #define TULIP_CSR_WRITEBYTE(sc, csr, val) \
csr 38 dev/pci/if_devar.h bus_space_write_1((sc)->tulip_bustag, (sc)->tulip_bushandle, (sc)->tulip_csrs.csr, (val))
csr 207 dev/pci/if_hme_pci.c pcireg_t csr;
csr 220 dev/pci/if_hme_pci.c csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
csr 223 dev/pci/if_hme_pci.c csr |= PCI_COMMAND_MEM_ENABLE;
csr 227 dev/pci/if_hme_pci.c csr |= PCI_COMMAND_IO_ENABLE;
csr 231 dev/pci/if_hme_pci.c csr | PCI_COMMAND_MEM_ENABLE);
csr 144 dev/pci/if_lmc.c LMC_CSR_WRITE(sc, csr_srom_mii, csr); \
csr 151 dev/pci/if_lmc.c unsigned bit, csr;
csr 153 dev/pci/if_lmc.c csr = SROMSEL ; EMIT;
csr 154 dev/pci/if_lmc.c csr = SROMSEL | SROMRD; EMIT;
csr 155 dev/pci/if_lmc.c csr ^= SROMCS; EMIT;
csr 156 dev/pci/if_lmc.c csr ^= SROMCLKON; EMIT;
csr 162 dev/pci/if_lmc.c csr ^= SROMCLKOFF; EMIT; /* clock low; data not valid */
csr 163 dev/pci/if_lmc.c csr ^= SROMCLKON; EMIT; /* clock high; data valid */
csr 165 dev/pci/if_lmc.c csr ^= SROMCLKOFF; EMIT;
csr 166 dev/pci/if_lmc.c csr ^= SROMCS; EMIT;
csr 167 dev/pci/if_lmc.c csr = 0; EMIT;
csr 183 dev/pci/if_lmc.c unsigned lastbit, data, bits, bit, csr;
csr 184 dev/pci/if_lmc.c csr = SROMSEL ; EMIT;
csr 185 dev/pci/if_lmc.c csr = SROMSEL | SROMRD; EMIT;
csr 186 dev/pci/if_lmc.c csr ^= SROMCSON; EMIT;
csr 187 dev/pci/if_lmc.c csr ^= SROMCLKON; EMIT;
csr 194 dev/pci/if_lmc.c csr ^= SROMCLKOFF; EMIT; /* clock L data invalid */
csr 196 dev/pci/if_lmc.c csr ^= SROMDOUT; EMIT;/* clock L invert data */
csr 200 dev/pci/if_lmc.c csr ^= SROMCLKON; EMIT; /* clock H data valid */
csr 203 dev/pci/if_lmc.c csr ^= SROMCLKOFF; EMIT;
csr 207 dev/pci/if_lmc.c csr ^= SROMCLKON; EMIT; /* clock H data valid */
csr 209 dev/pci/if_lmc.c csr ^= SROMCLKOFF; EMIT; /* clock L data invalid */
csr 213 dev/pci/if_lmc.c csr = SROMSEL | SROMRD; EMIT;
csr 214 dev/pci/if_lmc.c csr = 0; EMIT;
csr 219 dev/pci/if_lmc.c #define MII_EMIT do { LMC_CSR_WRITE(sc, csr_srom_mii, csr); lmc_delay_300ns(sc); } while (0)
csr 225 dev/pci/if_lmc.c unsigned csr = LMC_CSR_READ(sc, csr_srom_mii) & (MII_RD|MII_DOUT|MII_CLK);
csr 226 dev/pci/if_lmc.c unsigned lastbit = (csr & MII_DOUT) ? msb : 0;
csr 228 dev/pci/if_lmc.c csr |= MII_WR; MII_EMIT; /* clock low; assert write */
csr 233 dev/pci/if_lmc.c csr ^= MII_DOUT; MII_EMIT; /* clock low; invert data */
csr 235 dev/pci/if_lmc.c csr ^= MII_CLKON; MII_EMIT; /* clock high; data valid */
csr 237 dev/pci/if_lmc.c csr ^= MII_CLKOFF; MII_EMIT; /* clock low; data not valid */
csr 244 dev/pci/if_lmc.c u_int32_t csr;
csr 246 dev/pci/if_lmc.c csr = LMC_CSR_READ(sc, csr_srom_mii) & (MII_RD|MII_DOUT|MII_CLK);
csr 248 dev/pci/if_lmc.c csr |= MII_DOUT; MII_EMIT; /* clock low; change data */
csr 249 dev/pci/if_lmc.c csr ^= MII_CLKON; MII_EMIT; /* clock high; data valid */
csr 250 dev/pci/if_lmc.c csr ^= MII_CLKOFF; MII_EMIT; /* clock low; data not valid */
csr 251 dev/pci/if_lmc.c csr ^= MII_DOUT; MII_EMIT; /* clock low; change data */
csr 253 dev/pci/if_lmc.c csr |= MII_RD; MII_EMIT; /* clock low; switch to read */
csr 255 dev/pci/if_lmc.c csr ^= MII_CLKON; MII_EMIT; /* clock high; data valid */
csr 256 dev/pci/if_lmc.c csr ^= MII_CLKOFF; MII_EMIT; /* clock low; data not valid */
csr 263 dev/pci/if_lmc.c u_int32_t csr = LMC_CSR_READ(sc, csr_srom_mii) & (MII_RD|MII_DOUT|MII_CLK);
csr 268 dev/pci/if_lmc.c csr ^= MII_CLKON; MII_EMIT; /* clock high; data valid */
csr 271 dev/pci/if_lmc.c csr ^= MII_CLKOFF; MII_EMIT; /* clock low; data not valid */
csr 273 dev/pci/if_lmc.c csr ^= MII_RD; MII_EMIT; /* clock low; turn off read */
csr 281 dev/pci/if_lmc.c u_int32_t csr = LMC_CSR_READ(sc, csr_srom_mii) & (MII_RD|MII_DOUT|MII_CLK);
csr 284 dev/pci/if_lmc.c csr &= ~(MII_RD|MII_CLK); MII_EMIT;
csr 299 dev/pci/if_lmc.c u_int32_t csr;
csr 301 dev/pci/if_lmc.c csr = LMC_CSR_READ(sc, csr_srom_mii) & (MII_RD|MII_DOUT|MII_CLK);
csr 302 dev/pci/if_lmc.c csr &= ~(MII_RD|MII_CLK); MII_EMIT;
csr 814 dev/pci/if_lmc.c lmc_print_abnormal_interrupt (lmc_softc_t * const sc, u_int32_t csr)
csr 833 dev/pci/if_lmc.c u_int32_t csr;
csr 835 dev/pci/if_lmc.c while ((csr = LMC_CSR_READ(sc, csr_status)) & sc->lmc_intrmask) {
csr 838 dev/pci/if_lmc.c LMC_CSR_WRITE(sc, csr_status, csr);
csr 840 dev/pci/if_lmc.c if (csr & TULIP_STS_SYSERROR) {
csr 841 dev/pci/if_lmc.c sc->lmc_last_system_error = (csr & TULIP_STS_ERRORMASK) >> TULIP_STS_ERR_SHIFT;
csr 853 dev/pci/if_lmc.c if (csr & (TULIP_STS_RXINTR | TULIP_STS_RXNOBUF)) {
csr 855 dev/pci/if_lmc.c if (csr & TULIP_STS_RXNOBUF)
csr 882 dev/pci/if_lmc.c if (csr & TULIP_STS_ABNRMLINTR) {
csr 883 dev/pci/if_lmc.c u_int32_t tmp = csr & sc->lmc_intrmask
csr 885 dev/pci/if_lmc.c if (csr & TULIP_STS_TXUNDERFLOW) {
csr 903 dev/pci/if_lmc.c if (csr & TULIP_STS_TXINTR)
csr 140 dev/pci/if_lmcvar.h #define LMC_CSR_READ(sc, csr) \
csr 141 dev/pci/if_lmcvar.h bus_space_read_4((sc)->lmc_bustag, (sc)->lmc_bushandle, (sc)->lmc_csrs.csr)
csr 142 dev/pci/if_lmcvar.h #define LMC_CSR_WRITE(sc, csr, val) \
csr 143 dev/pci/if_lmcvar.h bus_space_write_4((sc)->lmc_bustag, (sc)->lmc_bushandle, (sc)->lmc_csrs.csr, (val))
csr 145 dev/pci/if_lmcvar.h #define LMC_CSR_READBYTE(sc, csr) \
csr 146 dev/pci/if_lmcvar.h bus_space_read_1((sc)->lmc_bustag, (sc)->lmc_bushandle, (sc)->lmc_csrs.csr)
csr 147 dev/pci/if_lmcvar.h #define LMC_CSR_WRITEBYTE(sc, csr, val) \
csr 148 dev/pci/if_lmcvar.h bus_space_write_1((sc)->lmc_bustag, (sc)->lmc_bushandle, (sc)->lmc_csrs.csr, (val))
csr 242 dev/pci/if_xge.c #define PIF_WCSR(csr, val) pif_wcsr(sc, csr, val)
csr 243 dev/pci/if_xge.c #define PIF_RCSR(csr) pif_rcsr(sc, csr)
csr 244 dev/pci/if_xge.c #define TXP_WCSR(csr, val) txp_wcsr(sc, csr, val)
csr 245 dev/pci/if_xge.c #define PIF_WKEY(csr, val) pif_wkey(sc, csr, val)
csr 248 dev/pci/if_xge.c pif_wcsr(struct xge_softc *sc, bus_size_t csr, uint64_t val)
csr 255 dev/pci/if_xge.c bus_space_write_4(sc->sc_st, sc->sc_sh, csr, lval);
csr 256 dev/pci/if_xge.c bus_space_write_4(sc->sc_st, sc->sc_sh, csr+4, hval);
csr 260 dev/pci/if_xge.c pif_rcsr(struct xge_softc *sc, bus_size_t csr)
csr 264 dev/pci/if_xge.c val = bus_space_read_4(sc->sc_st, sc->sc_sh, csr);
csr 265 dev/pci/if_xge.c val2 = bus_space_read_4(sc->sc_st, sc->sc_sh, csr+4);
csr 271 dev/pci/if_xge.c txp_wcsr(struct xge_softc *sc, bus_size_t csr, uint64_t val)
csr 278 dev/pci/if_xge.c bus_space_write_4(sc->sc_txt, sc->sc_txh, csr, lval);
csr 279 dev/pci/if_xge.c bus_space_write_4(sc->sc_txt, sc->sc_txh, csr+4, hval);
csr 284 dev/pci/if_xge.c pif_wkey(struct xge_softc *sc, bus_size_t csr, uint64_t val)
csr 294 dev/pci/if_xge.c bus_space_write_4(sc->sc_st, sc->sc_sh, csr, lval);
csr 299 dev/pci/if_xge.c bus_space_write_4(sc->sc_st, sc->sc_sh, csr+4, hval);
csr 109 dev/pci/mfi_pci.c pcireg_t csr;
csr 120 dev/pci/mfi_pci.c csr = pci_mapreg_type(pa->pa_pc, pa->pa_tag, MFI_BAR);
csr 121 dev/pci/mfi_pci.c csr |= PCI_MAPREG_MEM_TYPE_32BIT;
csr 122 dev/pci/mfi_pci.c if (pci_mapreg_map(pa, MFI_BAR, csr, 0,
csr 472 dev/pci/noct.c u_int32_t csr;
csr 475 dev/pci/noct.c csr = NOCT_READ_4(sc, NOCT_PKH_CSR);
csr 476 dev/pci/noct.c NOCT_WRITE_4(sc, NOCT_PKH_CSR, csr |
csr 496 dev/pci/noct.c if (csr & PKHCSR_CMDSI) {
csr 500 dev/pci/noct.c if (csr & PKHCSR_SKSWR)
csr 502 dev/pci/noct.c if (csr & PKHCSR_SKSOFF)
csr 504 dev/pci/noct.c if (csr & PKHCSR_PKHLEN)
csr 506 dev/pci/noct.c if (csr & PKHCSR_PKHOPCODE)
csr 508 dev/pci/noct.c if (csr & PKHCSR_BADQBASE)
csr 510 dev/pci/noct.c if (csr & PKHCSR_LOADERR)
csr 512 dev/pci/noct.c if (csr & PKHCSR_STOREERR)
csr 514 dev/pci/noct.c if (csr & PKHCSR_CMDERR)
csr 516 dev/pci/noct.c if (csr & PKHCSR_ILL)
csr 518 dev/pci/noct.c if (csr & PKHCSR_PKERESV)
csr 520 dev/pci/noct.c if (csr & PKHCSR_PKEWDT)
csr 522 dev/pci/noct.c if (csr & PKHCSR_PKENOTPRIME)
csr 524 dev/pci/noct.c if (csr & PKHCSR_PKE_B)
csr 526 dev/pci/noct.c if (csr & PKHCSR_PKE_A)
csr 528 dev/pci/noct.c if (csr & PKHCSR_PKE_M)
csr 530 dev/pci/noct.c if (csr & PKHCSR_PKE_R)
csr 532 dev/pci/noct.c if (csr & PKHCSR_PKEOPCODE)
csr 540 dev/pci/noct.c u_int64_t csr;
csr 566 dev/pci/noct.c csr = NOCT_READ_8(sc, NOCT_RNG_CTL);
csr 567 dev/pci/noct.c csr &= ~RNGCTL_RNG_ENA;
csr 568 dev/pci/noct.c NOCT_WRITE_8(sc, NOCT_RNG_CTL, csr);
csr 661 dev/pci/noct.c u_int32_t csr;
csr 664 dev/pci/noct.c csr = NOCT_READ_4(sc, NOCT_RNG_CSR);
csr 665 dev/pci/noct.c NOCT_WRITE_4(sc, NOCT_RNG_CSR, csr);
csr 667 dev/pci/noct.c if (csr & RNGCSR_ERR_KEY) {
csr 679 dev/pci/noct.c if (csr & RNGCSR_ERR_BUS) {
csr 683 dev/pci/noct.c if (csr & RNGCSR_ERR_DUP) {
csr 687 dev/pci/noct.c if (csr & RNGCSR_ERR_ACCESS) {
csr 1273 dev/pci/noct.c u_int32_t csr, rp;
csr 1275 dev/pci/noct.c csr = NOCT_READ_4(sc, NOCT_EA_CSR);
csr 1276 dev/pci/noct.c NOCT_WRITE_4(sc, NOCT_EA_CSR, csr |
csr 1304 dev/pci/noct.c if (csr & EACSR_QALIGN)
csr 1306 dev/pci/noct.c if (csr & EACSR_OPERR)
csr 1308 dev/pci/noct.c if (csr & EACSR_CMDREAD)
csr 1310 dev/pci/noct.c if (csr & EACSR_CMDWRITE)
csr 1312 dev/pci/noct.c if (csr & EACSR_DATAREAD)
csr 1314 dev/pci/noct.c if (csr & EACSR_DATAWRITE)
csr 1316 dev/pci/noct.c if (csr & EACSR_INTRNLLEN)
csr 1318 dev/pci/noct.c if (csr & EACSR_EXTRNLLEN)
csr 1320 dev/pci/noct.c if (csr & EACSR_DESBLOCK)
csr 1322 dev/pci/noct.c if (csr & EACSR_DESKEY)
csr 1324 dev/pci/noct.c if (csr & EACSR_ILL)
csr 248 dev/pci/pci.c pcireg_t id, csr, class, intr, bhlcr;
csr 258 dev/pci/pci.c csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
csr 61 dev/pci/pci_map.c pcireg_t address, mask, csr;
csr 86 dev/pci/pci_map.c csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
csr 87 dev/pci/pci_map.c if (csr & PCI_COMMAND_IO_ENABLE)
csr 89 dev/pci/pci_map.c csr & ~PCI_COMMAND_IO_ENABLE);
csr 94 dev/pci/pci_map.c if (csr & PCI_COMMAND_IO_ENABLE)
csr 95 dev/pci/pci_map.c pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
csr 126 dev/pci/pci_map.c pcireg_t address, mask, address1 = 0, mask1 = 0xffffffff, csr;
csr 157 dev/pci/pci_map.c csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
csr 158 dev/pci/pci_map.c if (csr & PCI_COMMAND_MEM_ENABLE)
csr 160 dev/pci/pci_map.c csr & ~PCI_COMMAND_MEM_ENABLE);
csr 171 dev/pci/pci_map.c if (csr & PCI_COMMAND_MEM_ENABLE)
csr 172 dev/pci/pci_map.c pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
csr 276 dev/pci/pci_map.c pcireg_t address, mask, csr;
csr 280 dev/pci/pci_map.c csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
csr 281 dev/pci/pci_map.c if (csr & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE))
csr 282 dev/pci/pci_map.c pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr &
csr 288 dev/pci/pci_map.c if (csr & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE))
csr 289 dev/pci/pci_map.c pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
csr 322 dev/pci/pci_map.c pcireg_t csr;
csr 332 dev/pci/pci_map.c csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
csr 334 dev/pci/pci_map.c csr |= PCI_COMMAND_IO_ENABLE;
csr 336 dev/pci/pci_map.c csr |= PCI_COMMAND_MEM_ENABLE;
csr 338 dev/pci/pci_map.c csr |= PCI_COMMAND_MASTER_ENABLE;
csr 339 dev/pci/pci_map.c pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr);
csr 1287 dev/pci/pciide.c pcireg_t csr;
csr 1293 dev/pci/pciide.c csr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);
csr 1295 dev/pci/pciide.c csr | PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE);
csr 1965 dev/pci/pciide.c pcireg_t csr;
csr 2031 dev/pci/pciide.c csr = pci_conf_read(sc->sc_pc, sc->sc_tag,
csr 2034 dev/pci/pciide.c csr & ~PCI_COMMAND_IO_ENABLE);
csr 2038 dev/pci/pciide.c PCI_COMMAND_STATUS_REG, csr);
csr 186 dev/sbus/apio.c u_int8_t csr;
csr 188 dev/sbus/apio.c csr = bus_space_read_1(sc->sc_bt, sc->sc_csr_h, 0);
csr 189 dev/sbus/apio.c csr &= ~(ASIO_CSR_SBUS_INT7 | ASIO_CSR_SBUS_INT6);
csr 190 dev/sbus/apio.c csr |= ASIO_CSR_SBUS_INT5 | en;
csr 191 dev/sbus/apio.c bus_space_write_1(sc->sc_bt, sc->sc_csr_h, 0, csr);
csr 189 dev/sbus/asio.c u_int8_t csr;
csr 191 dev/sbus/asio.c csr = bus_space_read_1(sc->sc_bt, sc->sc_csr_h, 0);
csr 192 dev/sbus/asio.c csr &= ~(ASIO_CSR_SBUS_INT7 | ASIO_CSR_SBUS_INT6);
csr 193 dev/sbus/asio.c csr |= ASIO_CSR_SBUS_INT5 | en;
csr 194 dev/sbus/asio.c bus_space_write_1(sc->sc_bt, sc->sc_csr_h, 0, csr);
csr 134 dev/sbus/cgtwelvereg.h u_int32_t csr;
csr 1317 dev/sbus/cs4231.c u_int32_t csr;
csr 1322 dev/sbus/cs4231.c csr = APC_READ(sc, APC_CSR);
csr 1323 dev/sbus/cs4231.c APC_WRITE(sc, APC_CSR, csr);
csr 1325 dev/sbus/cs4231.c if ((csr & APC_CSR_EIE) && (csr & APC_CSR_EI)) {
csr 1330 dev/sbus/cs4231.c if ((csr & APC_CSR_PIE) && (csr & APC_CSR_PI)) {
csr 1335 dev/sbus/cs4231.c if ((csr & APC_CSR_GIE) && (csr & APC_CSR_GI)) {
csr 1354 dev/sbus/cs4231.c if (csr & (APC_CSR_PI|APC_CSR_PMI|APC_CSR_PIE|APC_CSR_PD))
csr 1357 dev/sbus/cs4231.c if ((csr & APC_CSR_PMIE) && (csr & APC_CSR_PMI)) {
csr 1381 dev/sbus/cs4231.c if ((csr & APC_CSR_CIE) && (csr & APC_CSR_CI)) {
csr 1382 dev/sbus/cs4231.c if (csr & APC_CSR_CD) {
csr 1409 dev/sbus/cs4231.c if ((csr & APC_CSR_CMIE) && (csr & APC_CSR_CMI)) {
csr 1490 dev/sbus/cs4231.c u_int32_t csr;
csr 1526 dev/sbus/cs4231.c csr = APC_READ(sc, APC_CSR);
csr 1531 dev/sbus/cs4231.c if ((csr & APC_CSR_PDMA_GO) == 0 || (csr & APC_CSR_PPAUSE) != 0) {
csr 1552 dev/sbus/cs4231.c u_int32_t csr;
csr 1589 dev/sbus/cs4231.c csr = APC_READ(sc, APC_CSR);
csr 1590 dev/sbus/cs4231.c if ((csr & APC_CSR_CDMA_GO) == 0 || (csr & APC_CSR_CPAUSE) != 0) {
csr 1591 dev/sbus/cs4231.c csr &= APC_CSR_CPAUSE;
csr 1592 dev/sbus/cs4231.c csr |= APC_CSR_GIE | APC_CSR_CMIE | APC_CSR_CIE | APC_CSR_EI |
csr 1594 dev/sbus/cs4231.c APC_WRITE(sc, APC_CSR, csr);
csr 205 dev/sbus/dma_sbus.c u_int32_t csr;
csr 214 dev/sbus/dma_sbus.c csr = L64854_GCSR(sc);
csr 216 dev/sbus/dma_sbus.c csr |= E_TP_AUI;
csr 218 dev/sbus/dma_sbus.c csr &= ~E_TP_AUI;
csr 221 dev/sbus/dma_sbus.c csr |= E_TP_AUI;
csr 223 dev/sbus/dma_sbus.c L64854_SCSR(sc, csr);
csr 668 dev/sbus/esp_sbus.c u_int32_t csr;
csr 670 dev/sbus/esp_sbus.c csr = L64854_GCSR(esc->sc_dma);
csr 671 dev/sbus/esp_sbus.c csr &= ~D_EN_DMA;
csr 672 dev/sbus/esp_sbus.c L64854_SCSR(esc->sc_dma, csr);
csr 153 dev/sbus/if_le_ledma.c u_int32_t csr;
csr 155 dev/sbus/if_le_ledma.c csr = L64854_GCSR(dma);
csr 156 dev/sbus/if_le_ledma.c csr |= E_TP_AUI;
csr 157 dev/sbus/if_le_ledma.c L64854_SCSR(dma, csr);
csr 165 dev/sbus/if_le_ledma.c u_int32_t csr;
csr 167 dev/sbus/if_le_ledma.c csr = L64854_GCSR(dma);
csr 168 dev/sbus/if_le_ledma.c csr &= ~E_TP_AUI;
csr 169 dev/sbus/if_le_ledma.c L64854_SCSR(dma, csr);
csr 227 dev/sbus/if_le_ledma.c u_int32_t csr;
csr 233 dev/sbus/if_le_ledma.c csr = L64854_GCSR(dma);
csr 234 dev/sbus/if_le_ledma.c aui_bit = csr & E_TP_AUI;
csr 247 dev/sbus/if_le_ledma.c csr = L64854_GCSR(dma);
csr 248 dev/sbus/if_le_ledma.c csr |= (E_DSBL_WR_INVAL | aui_bit);
csr 249 dev/sbus/if_le_ledma.c L64854_SCSR(dma, csr);