root/dev/sbus/be.c

DEFINITIONS

1. bematch
2. beattach
3. be_put
4. be_get
5. be_read
6. bestart
7. bestop
8. bereset
9. bewatchdog
10. beintr
11. beqint
12. beeint
13. betint
14. berint
15. beioctl
16. beinit
17. be_mcreset
18. be_mii_sync
19. be_pal_gate
20. be_tcvr_read_bit
21. be_tcvr_write_bit
22. be_mii_sendbits
23. be_mii_readreg
24. be_mii_writereg
25. be_mii_reset
26. be_tick
27. be_mii_statchg
28. be_ifmedia_sts
29. be_ifmedia_upd
30. be_intphy_service
31. be_intphy_status

    1 /*      $OpenBSD: be.c,v 1.19 2006/06/02 20:00:56 miod Exp $    */
    2 /*      $NetBSD: be.c,v 1.26 2001/03/20 15:39:20 pk Exp $       */
    4 /*-
    5  * Copyright (c) 1999 The NetBSD Foundation, Inc.
    6  * All rights reserved.
    7  *
    8  * This code is derived from software contributed to The NetBSD Foundation
    9  * by Paul Kranenburg.
   10  *
   11  * Redistribution and use in source and binary forms, with or without
   12  * modification, are permitted provided that the following conditions
   13  * are met:
   14  * 1. Redistributions of source code must retain the above copyright
   15  *    notice, this list of conditions and the following disclaimer.
   16  * 2. Redistributions in binary form must reproduce the above copyright
   17  *    notice, this list of conditions and the following disclaimer in the
   18  *    documentation and/or other materials provided with the distribution.
   19  * 3. All advertising materials mentioning features or use of this software
   20  *    must display the following acknowledgement:
   21  *        This product includes software developed by the NetBSD
   22  *        Foundation, Inc. and its contributors.
   23  * 4. Neither the name of The NetBSD Foundation nor the names of its
   24  *    contributors may be used to endorse or promote products derived
   25  *    from this software without specific prior written permission.
   26  *
   27  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   29  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   30  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   37  * POSSIBILITY OF SUCH DAMAGE.
   38  */
   40 /*
   41  * Copyright (c) 1998 Theo de Raadt and Jason L. Wright.
   42  * All rights reserved.
   43  *
   44  * Redistribution and use in source and binary forms, with or without
   45  * modification, are permitted provided that the following conditions
   46  * are met:
   47  * 1. Redistributions of source code must retain the above copyright
   48  *    notice, this list of conditions and the following disclaimer.
   49  * 2. Redistributions in binary form must reproduce the above copyright
   50  *    notice, this list of conditions and the following disclaimer in the
   51  *    documentation and/or other materials provided with the distribution.
   52  *
   53  * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
   54  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   55  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   56  * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
   57  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   58  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   59  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   60  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   61  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   62  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   63  */
   65 #include "bpfilter.h"
   67 #include <sys/param.h>
   68 #include <sys/systm.h>
   69 #include <sys/timeout.h>
   70 #include <sys/kernel.h>
   71 #include <sys/errno.h>
   72 #include <sys/ioctl.h>
   73 #include <sys/mbuf.h>
   74 #include <sys/socket.h>
   75 #include <sys/syslog.h>
   76 #include <sys/device.h>
   77 #include <sys/malloc.h>
   79 #include <net/if.h>
   80 #include <net/if_dl.h>
   81 #include <net/if_types.h>
   82 #include <net/netisr.h>
   83 #include <net/if_media.h>
   85 #ifdef INET
   86 #include <netinet/in.h>
   87 #include <netinet/in_systm.h>
   88 #include <netinet/in_var.h>
   89 #include <netinet/ip.h>
   90 #include <netinet/if_ether.h>
   91 #endif
   93 #if NBPFILTER > 0
   94 #include <net/bpf.h>
   95 #endif
   97 #include <machine/bus.h>
   98 #include <machine/intr.h>
   99 #include <machine/autoconf.h>
  101 #include <dev/sbus/sbusvar.h>
  103 #include <dev/mii/mii.h>
  104 #include <dev/mii/miivar.h>
  106 #include <dev/sbus/qecreg.h>
  107 #include <dev/sbus/qecvar.h>
  108 #include <dev/sbus/bereg.h>
  110 struct be_softc {
  111         struct  device  sc_dev;
bus_space_tag_t sc_bustag;      /* bus & dma tags */
bus_dma_tag_t   sc_dmatag;
bus_dmamap_t    sc_dmamap;
  115         struct  arpcom sc_arpcom;
  116         /*struct        ifmedia sc_ifmedia;     -* interface media */
  117         struct mii_data sc_mii;         /* MII media control */
  118 #define sc_media        sc_mii.mii_media/* shorthand */
  119         int             sc_phys[2];     /* MII instance -> phy */
  121         struct timeout sc_tick_ch;
  123         /*
  124          * Some `mii_softc' items we need to emulate MII operation
  125          * for our internal transceiver.
  126          */
  127         int             sc_mii_inst;    /* instance of internal phy */
  128         int             sc_mii_active;  /* currently active medium */
  129         int             sc_mii_ticks;   /* tick counter */
  130         int             sc_mii_flags;   /* phy status flags */
  131 #define MIIF_HAVELINK   0x04000000
  132         int             sc_intphy_curspeed;     /* Established link speed */
  134         struct  qec_softc *sc_qec;      /* QEC parent */
bus_space_handle_t      sc_qr;  /* QEC registers */
bus_space_handle_t      sc_br;  /* BE registers */
bus_space_handle_t      sc_cr;  /* channel registers */
bus_space_handle_t      sc_tr;  /* transceiver registers */
u_int   sc_rev;
  143         int     sc_channel;             /* channel number */
  144         int     sc_burst;
  146         struct  qec_ring        sc_rb;  /* Packet Ring Buffer */
  147 };
  149 int     bematch(struct device *, void *, void *);
  150 void    beattach(struct device *, struct device *, void *);
  152 void    beinit(struct be_softc *);
  153 void    bestart(struct ifnet *);
  154 void    bestop(struct be_softc *);
  155 void    bewatchdog(struct ifnet *);
  156 int     beioctl(struct ifnet *, u_long, caddr_t);
  157 void    bereset(struct be_softc *);
  159 int     beintr(void *);
  160 int     berint(struct be_softc *);
  161 int     betint(struct be_softc *);
  162 int     beqint(struct be_softc *, u_int32_t);
  163 int     beeint(struct be_softc *, u_int32_t);
  165 static void     be_read(struct be_softc *, int, int);
  166 static int      be_put(struct be_softc *, int, struct mbuf *);
  167 static struct mbuf *be_get(struct be_softc *, int, int);
  169 void    be_pal_gate(struct be_softc *, int);
  171 /* ifmedia callbacks */
  172 void    be_ifmedia_sts(struct ifnet *, struct ifmediareq *);
  173 int     be_ifmedia_upd(struct ifnet *);
  175 void    be_mcreset(struct be_softc *);
  177 /* MII methods & callbacks */
  178 static int      be_mii_readreg(struct device *, int, int);
  179 static void     be_mii_writereg(struct device *, int, int, int);
  180 static void     be_mii_statchg(struct device *);
  182 /* MII helpers */
  183 static void     be_mii_sync(struct be_softc *);
  184 static void     be_mii_sendbits(struct be_softc *, int, u_int32_t, int);
  185 static int      be_mii_reset(struct be_softc *, int);
  186 static int      be_tcvr_read_bit(struct be_softc *, int);
  187 static void     be_tcvr_write_bit(struct be_softc *, int, int);
  189 void    be_tick(void *);
  190 void    be_intphy_auto(struct be_softc *);
  191 void    be_intphy_status(struct be_softc *);
  192 int     be_intphy_service(struct be_softc *, struct mii_data *, int);
  195 struct cfattach be_ca = {
  196         sizeof(struct be_softc), bematch, beattach
  197 };
  199 struct cfdriver be_cd = {
NULL, "be", DV_IFNET
  201 };
  203 int
bematch(struct device *parent, void *vcf, void *aux)
  205 {
  206         struct cfdata *cf = vcf;
  207         struct sbus_attach_args *sa = aux;
  209         return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0);
  210 }
  212 void
beattach(struct device *parent, struct device *self, void *aux)
  214 {
  215         struct sbus_attach_args *sa = aux;
  216         struct qec_softc *qec = (struct qec_softc *)parent;
  217         struct be_softc *sc = (struct be_softc *)self;
  218         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
  219         struct mii_data *mii = &sc->sc_mii;
  220         struct mii_softc *child;
  221         int node = sa->sa_node;
bus_dma_tag_t dmatag = sa->sa_dmatag;
bus_dma_segment_t seg;
bus_size_t size;
  225         int instance;
  226         int rseg, error;
u_int32_t v;
  228         extern void myetheraddr(u_char *);
  230         /* Pass on the bus tags */
sc->sc_bustag = sa->sa_bustag;
sc->sc_dmatag = sa->sa_dmatag;
  234         if (sa->sa_nreg < 3) {
printf("%s: only %d register sets\n",
self->dv_xname, sa->sa_nreg);
  237                 return;
  238         }
  240         if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot,
  241             (bus_addr_t)sa->sa_reg[0].sbr_offset,
  242             (bus_size_t)sa->sa_reg[0].sbr_size, 0, 0, &sc->sc_cr) != 0) {
printf("beattach: cannot map registers\n");
  244                 return;
  245         }
  247         if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[1].sbr_slot,
  248             (bus_addr_t)sa->sa_reg[1].sbr_offset,
  249             (bus_size_t)sa->sa_reg[1].sbr_size, 0, 0, &sc->sc_br) != 0) {
printf("beattach: cannot map registers\n");
  251                 return;
  252         }
  254         if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[2].sbr_slot,
  255             (bus_addr_t)sa->sa_reg[2].sbr_offset,
  256             (bus_size_t)sa->sa_reg[2].sbr_size, 0, 0, &sc->sc_tr) != 0) {
printf("beattach: cannot map registers\n");
  258                 return;
  259         }
sc->sc_qec = qec;
sc->sc_qr = qec->sc_regs;
sc->sc_rev = getpropint(node, "board-version", -1);
printf(" rev %x", sc->sc_rev);
bestop(sc);
sc->sc_channel = getpropint(node, "channel#", -1);
  270         if (sc->sc_channel == -1)
sc->sc_channel = 0;
sc->sc_burst = getpropint(node, "burst-sizes", -1);
  274         if (sc->sc_burst == -1)
sc->sc_burst = qec->sc_burst;
  277         /* Clamp at parent's burst sizes */
sc->sc_burst &= qec->sc_burst;
  280         /* Establish interrupt handler */
  281         if (sa->sa_nintr == 0 || bus_intr_establish(sa->sa_bustag, sa->sa_pri,
IPL_NET, 0, beintr, sc, self->dv_xname) == NULL) {
printf(": no interrupt established\n");
  284                 return;
  285         }
myetheraddr(sc->sc_arpcom.ac_enaddr);
printf(" address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr));
  290         /*
  291          * Allocate descriptor ring and buffers.
  292          */
  294         /* for now, allocate as many bufs as there are ring descriptors */
sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE;
sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE;
size =  QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) +
QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) +
sc->sc_rb.rb_ntbuf * BE_PKT_BUF_SZ +
sc->sc_rb.rb_nrbuf * BE_PKT_BUF_SZ;
  303         /* Get a DMA handle */
  304         if ((error = bus_dmamap_create(dmatag, size, 1, size, 0,
BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) {
printf("%s: DMA map create error %d\n", self->dv_xname, error);
  307                 return;
  308         }
  310         /* Allocate DMA buffer */
  311         if ((error = bus_dmamem_alloc(sa->sa_dmatag, size, 0, 0,
  312             &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
printf("%s: DMA buffer alloc error %d\n",
self->dv_xname, error);
  315                 return;
  316         }
  318         /* Map DMA memory in CPU addressable space */
  319         if ((error = bus_dmamem_map(sa->sa_dmatag, &seg, rseg, size,
  320             &sc->sc_rb.rb_membase, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
printf("%s: DMA buffer map error %d\n",
self->dv_xname, error);
bus_dmamem_free(sa->sa_dmatag, &seg, rseg);
  324                 return;
  325         }
  327         /* Load the buffer */
  328         if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap,
sc->sc_rb.rb_membase, size, NULL, BUS_DMA_NOWAIT)) != 0) {
printf("%s: DMA buffer map load error %d\n",
self->dv_xname, error);
bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size);
bus_dmamem_free(dmatag, &seg, rseg);
  334                 return;
  335         }
sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr;
  338         /*
  339          * Initialize our media structures and MII info.
  340          */
mii->mii_ifp = ifp;
mii->mii_readreg = be_mii_readreg;
mii->mii_writereg = be_mii_writereg;
mii->mii_statchg = be_mii_statchg;
ifmedia_init(&mii->mii_media, 0, be_ifmedia_upd, be_ifmedia_sts);
timeout_set(&sc->sc_tick_ch, be_tick, sc);
  350         /*
  351          * Initialize transceiver and determine which PHY connection to use.
  352          */
be_mii_sync(sc);
v = bus_space_read_4(sc->sc_bustag, sc->sc_tr, BE_TRI_MGMTPAL);
instance = 0;
  358         if ((v & MGMT_PAL_EXT_MDIO) != 0) {
mii_attach(&sc->sc_dev, mii, 0xffffffff, BE_PHY_EXTERNAL,
MII_OFFSET_ANY, 0);
child = LIST_FIRST(&mii->mii_phys);
  364                 if (child == NULL) {
  365                         /* No PHY attached */
ifmedia_add(&sc->sc_media,
IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance),
  368                             0, NULL);
ifmedia_set(&sc->sc_media,
IFM_MAKEWORD(IFM_ETHER,IFM_NONE,0,instance));
  371                 } else {
  372                         /*
  373                          * Note: we support just one PHY on the external
  374                          * MII connector.
  375                          */
  376 #ifdef DIAGNOSTIC
  377                         if (LIST_NEXT(child, mii_list) != NULL) {
printf("%s: spurious MII device %s attached\n",
sc->sc_dev.dv_xname,
child->mii_dev.dv_xname);
  381                         }
  382 #endif
  383                         if (child->mii_phy != BE_PHY_EXTERNAL ||
child->mii_inst > 0) {
printf("%s: cannot accommodate MII device %s"
  386                                     " at phy %d, instance %d\n",
sc->sc_dev.dv_xname,
child->mii_dev.dv_xname,
child->mii_phy, child->mii_inst);
  390                         } else {
sc->sc_phys[instance] = child->mii_phy;
  392                         }
  394                         /*
  395                          * XXX - we can really do the following ONLY if the
  396                          * phy indeed has the auto negotiation capability!!
  397                          */
ifmedia_set(&sc->sc_media,
IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance));
  401                         /* Mark our current media setting */
be_pal_gate(sc, BE_PHY_EXTERNAL);
instance++;
  404                 }
  406         }
  408         if ((v & MGMT_PAL_INT_MDIO) != 0) {
  409                 /*
  410                  * The be internal phy looks vaguely like MII hardware,
  411                  * but not enough to be able to use the MII device
  412                  * layer. Hence, we have to take care of media selection
  413                  * ourselves.
  414                  */
sc->sc_mii_inst = instance;
sc->sc_phys[instance] = BE_PHY_INTERNAL;
  419                 /* Use `ifm_data' to store BMCR bits */
ifmedia_add(&sc->sc_media,
IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,instance), 0, NULL);
ifmedia_add(&sc->sc_media,
IFM_MAKEWORD(IFM_ETHER,IFM_100_TX,0,instance),
BMCR_S100, NULL);
ifmedia_add(&sc->sc_media,
IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance), 0, NULL);
printf("on-board transceiver at %s: 10baseT, 100baseTX, auto\n",
self->dv_xname);
be_mii_reset(sc, BE_PHY_INTERNAL);
  432                 /* Only set default medium here if there's no external PHY */
  433                 if (instance == 0) {
be_pal_gate(sc, BE_PHY_INTERNAL);
ifmedia_set(&sc->sc_media,
IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,instance));
  437                 } else
be_mii_writereg((void *)sc,
BE_PHY_INTERNAL, MII_BMCR, BMCR_ISO);
  440         }
bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
ifp->if_softc = sc;
ifp->if_start = bestart;
ifp->if_ioctl = beioctl;
ifp->if_watchdog = bewatchdog;
ifp->if_flags =
IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST;
IFQ_SET_READY(&ifp->if_snd);
  451         /* Attach the interface. */
if_attach(ifp);
ether_ifattach(ifp);
  454 }
  457 /*
  458  * Routine to copy from mbuf chain to transmit buffer in
  459  * network buffer memory.
  460  */
  461 static __inline__ int
be_put(struct be_softc *sc, int idx, struct mbuf *m)
  463 {
  464         struct mbuf *n;
  465         int len, tlen = 0, boff = 0;
caddr_t bp;
bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * BE_PKT_BUF_SZ;
  470         for (; m; m = n) {
len = m->m_len;
  472                 if (len == 0) {
MFREE(m, n);
  474                         continue;
  475                 }
bcopy(mtod(m, caddr_t), bp+boff, len);
boff += len;
tlen += len;
MFREE(m, n);
  480         }
  481         return (tlen);
  482 }
  484 /*
  485  * Pull data off an interface.
  486  * Len is the length of data, with local net header stripped.
  487  * We copy the data into mbufs.  When full cluster sized units are present,
  488  * we copy into clusters.
  489  */
  490 static __inline__ struct mbuf *
be_get(struct be_softc *sc, int idx, int totlen)
  492 {
  493         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
  494         struct mbuf *m;
  495         struct mbuf *top, **mp;
  496         int len, pad, boff = 0;
caddr_t bp;
bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * BE_PKT_BUF_SZ;
MGETHDR(m, M_DONTWAIT, MT_DATA);
  502         if (m == NULL)
  503                 return (NULL);
m->m_pkthdr.rcvif = ifp;
m->m_pkthdr.len = totlen;
pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header);
m->m_data += pad;
len = MHLEN - pad;
top = NULL;
mp = &top;
  513         while (totlen > 0) {
  514                 if (top) {
MGET(m, M_DONTWAIT, MT_DATA);
  516                         if (m == NULL) {
m_freem(top);
  518                                 return (NULL);
  519                         }
len = MLEN;
  521                 }
  522                 if (top && totlen >= MINCLSIZE) {
MCLGET(m, M_DONTWAIT);
  524                         if (m->m_flags & M_EXT)
len = MCLBYTES;
  526                 }
m->m_len = len = min(totlen, len);
bcopy(bp + boff, mtod(m, caddr_t), len);
boff += len;
totlen -= len;
  531                 *mp = m;
mp = &m->m_next;
  533         }
  535         return (top);
  536 }
  538 /*
  539  * Pass a packet to the higher levels.
  540  */
  541 static __inline__ void
be_read(struct be_softc *sc, int idx, int len)
  543 {
  544         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
  545         struct mbuf *m;
  547         if (len <= sizeof(struct ether_header) ||
len > ETHERMTU + sizeof(struct ether_header)) {
printf("%s: invalid packet size %d; dropping\n",
ifp->if_xname, len);
ifp->if_ierrors++;
  554                 return;
  555         }
  557         /*
  558          * Pull packet off interface.
  559          */
m = be_get(sc, idx, len);
  561         if (m == NULL) {
ifp->if_ierrors++;
  563                 return;
  564         }
ifp->if_ipackets++;
  567 #if NBPFILTER > 0
  568         /*
  569          * Check if there's a BPF listener on this interface.
  570          * If so, hand off the raw packet to BPF.
  571          */
  572         if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN);
  574 #endif
  575         /* Pass the packet up. */
ether_input_mbuf(ifp, m);
  577 }
  579 /*
  580  * Start output on interface.
  581  * We make two assumptions here:
  582  *  1) that the current priority is set to splnet _before_ this code
  583  *     is called *and* is returned to the appropriate priority after
  584  *     return
  585  *  2) that the IFF_OACTIVE flag is checked before this code is called
  586  *     (i.e. that the output part of the interface is idle)
  587  */
  588 void
bestart(struct ifnet *ifp)
  590 {
  591         struct be_softc *sc = (struct be_softc *)ifp->if_softc;
  592         struct qec_xd *txd = sc->sc_rb.rb_txd;
  593         struct mbuf *m;
  594         unsigned int bix, len;
  595         unsigned int ntbuf = sc->sc_rb.rb_ntbuf;
  597         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
  598                 return;
bix = sc->sc_rb.rb_tdhead;
  602         for (;;) {
IFQ_DEQUEUE(&ifp->if_snd, m);
  604                 if (m == 0)
  605                         break;
  607 #if NBPFILTER > 0
  608                 /*
  609                  * If BPF is listening on this interface, let it see the
  610                  * packet before we commit it to the wire.
  611                  */
  612                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT);
  614 #endif
  616                 /*
  617                  * Copy the mbuf chain into the transmit buffer.
  618                  */
len = be_put(sc, bix, m);
  621                 /*
  622                  * Initialize transmit registers and start transmission
  623                  */
txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP |
  625                                     (len & QEC_XD_LENGTH);
bus_space_write_4(sc->sc_bustag, sc->sc_cr, BE_CRI_CTRL,
BE_CR_CTRL_TWAKEUP);
  629                 if (++bix == QEC_XD_RING_MAXSIZE)
bix = 0;
  632                 if (++sc->sc_rb.rb_td_nbusy == ntbuf) {
ifp->if_flags |= IFF_OACTIVE;
  634                         break;
  635                 }
  636         }
sc->sc_rb.rb_tdhead = bix;
  639 }
  641 void
bestop(struct be_softc *sc)
  643 {
  644         int n;
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t br = sc->sc_br;
timeout_del(&sc->sc_tick_ch);
  650         /* Down the MII. */
mii_down(&sc->sc_mii);
  652         (void)be_intphy_service(sc, &sc->sc_mii, MII_DOWN);
  654         /* Stop the transmitter */
bus_space_write_4(t, br, BE_BRI_TXCFG, 0);
  656         for (n = 32; n > 0; n--) {
  657                 if (bus_space_read_4(t, br, BE_BRI_TXCFG) == 0)
  658                         break;
DELAY(20);
  660         }
  662         /* Stop the receiver */
bus_space_write_4(t, br, BE_BRI_RXCFG, 0);
  664         for (n = 32; n > 0; n--) {
  665                 if (bus_space_read_4(t, br, BE_BRI_RXCFG) == 0)
  666                         break;
DELAY(20);
  668         }
  669 }
  671 /*
  672  * Reset interface.
  673  */
  674 void
bereset(struct be_softc *sc)
  676 {
  677         int s;
s = splnet();
bestop(sc);
  681         if ((sc->sc_arpcom.ac_if.if_flags & IFF_UP) != 0)
beinit(sc);
splx(s);
  684 }
  686 void
bewatchdog(struct ifnet *ifp)
  688 {
  689         struct be_softc *sc = ifp->if_softc;
log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname);
  692         ++sc->sc_arpcom.ac_if.if_oerrors;
bereset(sc);
  694 }
  696 int
beintr(void *v)
  698 {
  699         struct be_softc *sc = (struct be_softc *)v;
bus_space_tag_t t = sc->sc_bustag;
u_int32_t whyq, whyb, whyc;
  702         int r = 0;
  704         /* Read QEC status, channel status and BE status */
whyq = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT);
whyc = bus_space_read_4(t, sc->sc_cr, BE_CRI_STAT);
whyb = bus_space_read_4(t, sc->sc_br, BE_BRI_STAT);
  709         if (whyq & QEC_STAT_BM)
r |= beeint(sc, whyb);
  712         if (whyq & QEC_STAT_ER)
r |= beqint(sc, whyc);
  715         if (whyq & QEC_STAT_TX && whyc & BE_CR_STAT_TXIRQ)
r |= betint(sc);
  718         if (whyq & QEC_STAT_RX && whyc & BE_CR_STAT_RXIRQ)
r |= berint(sc);
  721         return (r);
  722 }
  724 /*
  725  * QEC Interrupt.
  726  */
  727 int
beqint(struct be_softc *sc, u_int32_t why)
  729 {
  730         int r = 0, rst = 0;
  732         if (why & BE_CR_STAT_TXIRQ)
r |= 1;
  734         if (why & BE_CR_STAT_RXIRQ)
r |= 1;
  737         if (why & BE_CR_STAT_BERROR) {
r |= 1;
rst = 1;
printf("%s: bigmac error\n", sc->sc_dev.dv_xname);
  741         }
  743         if (why & BE_CR_STAT_TXDERR) {
r |= 1;
rst = 1;
printf("%s: bogus tx descriptor\n", sc->sc_dev.dv_xname);
  747         }
  749         if (why & (BE_CR_STAT_TXLERR | BE_CR_STAT_TXPERR | BE_CR_STAT_TXSERR)) {
r |= 1;
rst = 1;
printf("%s: tx dma error ( ", sc->sc_dev.dv_xname);
  753                 if (why & BE_CR_STAT_TXLERR)
printf("Late ");
  755                 if (why & BE_CR_STAT_TXPERR)
printf("Parity ");
  757                 if (why & BE_CR_STAT_TXSERR)
printf("Generic ");
printf(")\n");
  760         }
  762         if (why & BE_CR_STAT_RXDROP) {
r |= 1;
rst = 1;
printf("%s: out of rx descriptors\n", sc->sc_dev.dv_xname);
  766         }
  768         if (why & BE_CR_STAT_RXSMALL) {
r |= 1;
rst = 1;
printf("%s: rx descriptor too small\n", sc->sc_dev.dv_xname);
  772         }
  774         if (why & (BE_CR_STAT_RXLERR | BE_CR_STAT_RXPERR | BE_CR_STAT_RXSERR)) {
r |= 1;
rst = 1;
printf("%s: rx dma error ( ", sc->sc_dev.dv_xname);
  778                 if (why & BE_CR_STAT_RXLERR)
printf("Late ");
  780                 if (why & BE_CR_STAT_RXPERR)
printf("Parity ");
  782                 if (why & BE_CR_STAT_RXSERR)
printf("Generic ");
printf(")\n");
  785         }
  787         if (!r) {
rst = 1;
printf("%s: unexpected error interrupt %08x\n",
sc->sc_dev.dv_xname, why);
  791         }
  793         if (rst) {
printf("%s: resetting\n", sc->sc_dev.dv_xname);
bereset(sc);
  796         }
  798         return (r);
  799 }
  801 /*
  802  * Error interrupt.
  803  */
  804 int
beeint(struct be_softc *sc, u_int32_t why)
  806 {
  807         int r = 0, rst = 0;
  809         if (why & BE_BR_STAT_RFIFOVF) {
r |= 1;
rst = 1;
printf("%s: receive fifo overrun\n", sc->sc_dev.dv_xname);
  813         }
  814         if (why & BE_BR_STAT_TFIFO_UND) {
r |= 1;
rst = 1;
printf("%s: transmit fifo underrun\n", sc->sc_dev.dv_xname);
  818         }
  819         if (why & BE_BR_STAT_MAXPKTERR) {
r |= 1;
rst = 1;
printf("%s: max packet size error\n", sc->sc_dev.dv_xname);
  823         }
  825         if (!r) {
rst = 1;
printf("%s: unexpected error interrupt %08x\n",
sc->sc_dev.dv_xname, why);
  829         }
  831         if (rst) {
printf("%s: resetting\n", sc->sc_dev.dv_xname);
bereset(sc);
  834         }
  836         return (r);
  837 }
  839 /*
  840  * Transmit interrupt.
  841  */
  842 int
betint(struct be_softc *sc)
  844 {
  845         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t br = sc->sc_br;
  848         unsigned int bix, txflags;
  850         /*
  851          * Unload collision counters
  852          */
ifp->if_collisions +=
bus_space_read_4(t, br, BE_BRI_NCCNT) +
bus_space_read_4(t, br, BE_BRI_FCCNT) +
bus_space_read_4(t, br, BE_BRI_EXCNT) +
bus_space_read_4(t, br, BE_BRI_LTCNT);
  859         /*
  860          * the clear the hardware counters
  861          */
bus_space_write_4(t, br, BE_BRI_NCCNT, 0);
bus_space_write_4(t, br, BE_BRI_FCCNT, 0);
bus_space_write_4(t, br, BE_BRI_EXCNT, 0);
bus_space_write_4(t, br, BE_BRI_LTCNT, 0);
bix = sc->sc_rb.rb_tdtail;
  869         for (;;) {
  870                 if (sc->sc_rb.rb_td_nbusy <= 0)
  871                         break;
txflags = sc->sc_rb.rb_txd[bix].xd_flags;
  875                 if (txflags & QEC_XD_OWN)
  876                         break;
ifp->if_flags &= ~IFF_OACTIVE;
ifp->if_opackets++;
  881                 if (++bix == QEC_XD_RING_MAXSIZE)
bix = 0;
  884                 --sc->sc_rb.rb_td_nbusy;
  885         }
sc->sc_rb.rb_tdtail = bix;
bestart(ifp);
  891         if (sc->sc_rb.rb_td_nbusy == 0)
ifp->if_timer = 0;
  894         return (1);
  895 }
  897 /*
  898  * Receive interrupt.
  899  */
  900 int
berint(struct be_softc *sc)
  902 {
  903         struct qec_xd *xd = sc->sc_rb.rb_rxd;
  904         unsigned int bix, len;
  905         unsigned int nrbuf = sc->sc_rb.rb_nrbuf;
bix = sc->sc_rb.rb_rdtail;
  909         /*
  910          * Process all buffers with valid data.
  911          */
  912         for (;;) {
len = xd[bix].xd_flags;
  914                 if (len & QEC_XD_OWN)
  915                         break;
len &= QEC_XD_LENGTH;
be_read(sc, bix, len);
  920                 /* ... */
xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags =
QEC_XD_OWN | (BE_PKT_BUF_SZ & QEC_XD_LENGTH);
  924                 if (++bix == QEC_XD_RING_MAXSIZE)
bix = 0;
  926         }
sc->sc_rb.rb_rdtail = bix;
  930         return (1);
  931 }
  933 int
beioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
  935 {
  936         struct be_softc *sc = ifp->if_softc;
  937         struct ifaddr *ifa = (struct ifaddr *)data;
  938         struct ifreq *ifr = (struct ifreq *)data;
  939         int s, error = 0;
s = splnet();
  943         if ((error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data)) > 0) {
splx(s);
  945                 return (error);
  946         }
  948         switch (cmd) {
  949         case SIOCSIFADDR:
ifp->if_flags |= IFF_UP;
  951                 switch (ifa->ifa_addr->sa_family) {
  952 #ifdef INET
  953                 case AF_INET:
beinit(sc);
arp_ifinit(&sc->sc_arpcom, ifa);
  956                         break;
  957 #endif /* INET */
  958                 default:
beinit(sc);
  960                         break;
  961                 }
  962                 break;
  964         case SIOCSIFFLAGS:
  965                 if ((ifp->if_flags & IFF_UP) == 0 &&
  966                     (ifp->if_flags & IFF_RUNNING) != 0) {
  967                         /*
  968                          * If interface is marked down and it is running, then
  969                          * stop it.
  970                          */
bestop(sc);
ifp->if_flags &= ~IFF_RUNNING;
  973                 } else if ((ifp->if_flags & IFF_UP) != 0 &&
  974                     (ifp->if_flags & IFF_RUNNING) == 0) {
  975                         /*
  976                          * If interface is marked up and it is stopped, then
  977                          * start it.
  978                          */
beinit(sc);
  980                 } else {
  981                         /*
  982                          * Reset the interface to pick up changes in any other
  983                          * flags that affect hardware registers.
  984                          */
bestop(sc);
beinit(sc);
  987                 }
  988 #ifdef BEDEBUG
  989                 if (ifp->if_flags & IFF_DEBUG)
sc->sc_debug = 1;
  991                 else
sc->sc_debug = 0;
  993 #endif
  994                 break;
  996         case SIOCADDMULTI:
  997         case SIOCDELMULTI:
error = (cmd == SIOCADDMULTI) ?
ether_addmulti(ifr, &sc->sc_arpcom):
ether_delmulti(ifr, &sc->sc_arpcom);
 1002                 if (error == ENETRESET) {
 1003                         /*
 1004                          * Multicast list has changed; set the hardware filter
 1005                          * accordingly.
 1006                          */
 1007                         if (ifp->if_flags & IFF_RUNNING)
be_mcreset(sc);
error = 0;
 1010                 }
 1011                 break;
 1012         case SIOCGIFMEDIA:
 1013         case SIOCSIFMEDIA:
error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd);
 1015                 break;
 1016         default:
error = EINVAL;
 1018                 break;
 1019         }
splx(s);
 1021         return (error);
 1022 }
 1025 void
beinit(struct be_softc *sc)
 1027 {
 1028         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t br = sc->sc_br;
bus_space_handle_t cr = sc->sc_cr;
 1032         struct qec_softc *qec = sc->sc_qec;
u_int32_t v;
u_int32_t qecaddr;
u_int8_t *ea;
 1036         int s;
s = splnet();
qec_meminit(&sc->sc_rb, BE_PKT_BUF_SZ);
bestop(sc);
ea = sc->sc_arpcom.ac_enaddr;
bus_space_write_4(t, br, BE_BRI_MACADDR0, (ea[0] << 8) | ea[1]);
bus_space_write_4(t, br, BE_BRI_MACADDR1, (ea[2] << 8) | ea[3]);
bus_space_write_4(t, br, BE_BRI_MACADDR2, (ea[4] << 8) | ea[5]);
 1049         /* Clear hash table */
bus_space_write_4(t, br, BE_BRI_HASHTAB0, 0);
bus_space_write_4(t, br, BE_BRI_HASHTAB1, 0);
bus_space_write_4(t, br, BE_BRI_HASHTAB2, 0);
bus_space_write_4(t, br, BE_BRI_HASHTAB3, 0);
 1055         /* Re-initialize RX configuration */
v = BE_BR_RXCFG_FIFO;
bus_space_write_4(t, br, BE_BRI_RXCFG, v);
be_mcreset(sc);
bus_space_write_4(t, br, BE_BRI_RANDSEED, 0xbd);
bus_space_write_4(t, br, BE_BRI_XIFCFG,
BE_BR_XCFG_ODENABLE | BE_BR_XCFG_RESV);
bus_space_write_4(t, br, BE_BRI_JSIZE, 4);
 1068         /*
 1069          * Turn off counter expiration interrupts as well as
 1070          * 'gotframe' and 'sentframe'
 1071          */
bus_space_write_4(t, br, BE_BRI_IMASK,
BE_BR_IMASK_GOTFRAME  |
BE_BR_IMASK_RCNTEXP   |
BE_BR_IMASK_ACNTEXP   |
BE_BR_IMASK_CCNTEXP   |
BE_BR_IMASK_LCNTEXP   |
BE_BR_IMASK_CVCNTEXP  |
BE_BR_IMASK_SENTFRAME |
BE_BR_IMASK_NCNTEXP   |
BE_BR_IMASK_ECNTEXP   |
BE_BR_IMASK_LCCNTEXP  |
BE_BR_IMASK_FCNTEXP   |
BE_BR_IMASK_DTIMEXP);
 1086         /* Channel registers: */
bus_space_write_4(t, cr, BE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma);
bus_space_write_4(t, cr, BE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma);
qecaddr = sc->sc_channel * qec->sc_msize;
bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr);
bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr);
bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize);
bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize);
bus_space_write_4(t, cr, BE_CRI_RIMASK, 0);
bus_space_write_4(t, cr, BE_CRI_TIMASK, 0);
bus_space_write_4(t, cr, BE_CRI_QMASK, 0);
bus_space_write_4(t, cr, BE_CRI_BMASK, 0);
bus_space_write_4(t, cr, BE_CRI_CCNT, 0);
 1102         /* Enable transmitter */
bus_space_write_4(t, br, BE_BRI_TXCFG,
BE_BR_TXCFG_FIFO | BE_BR_TXCFG_ENABLE);
 1106         /* Enable receiver */
v = bus_space_read_4(t, br, BE_BRI_RXCFG);
v |= BE_BR_RXCFG_FIFO | BE_BR_RXCFG_ENABLE;
bus_space_write_4(t, br, BE_BRI_RXCFG, v);
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
be_ifmedia_upd(ifp);
timeout_add(&sc->sc_tick_ch, hz);
splx(s);
 1117 }
 1119 void
be_mcreset(struct be_softc *sc)
 1121 {
 1122         struct arpcom *ac = &sc->sc_arpcom;
 1123         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t br = sc->sc_br;
u_int32_t crc;
u_int16_t hash[4];
u_int8_t octet;
u_int32_t v;
 1130         int i, j;
 1131         struct ether_multi *enm;
 1132         struct ether_multistep step;
 1134         if (ifp->if_flags & IFF_PROMISC) {
v = bus_space_read_4(t, br, BE_BRI_RXCFG);
v |= BE_BR_RXCFG_PMISC;
bus_space_write_4(t, br, BE_BRI_RXCFG, v);
 1138                 return;
 1139         }
 1141         if (ifp->if_flags & IFF_ALLMULTI) {
hash[3] = hash[2] = hash[1] = hash[0] = 0xffff;
 1143                 goto chipit;
 1144         }
hash[3] = hash[2] = hash[1] = hash[0] = 0;
ETHER_FIRST_MULTI(step, ac, enm);
 1149         while (enm != NULL) {
 1150                 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
 1151                         /*
 1152                          * We must listen to a range of multicast
 1153                          * addresses.  For now, just accept all
 1154                          * multicasts, rather than trying to set only
 1155                          * those filter bits needed to match the range.
 1156                          * (At this time, the only use of address
 1157                          * ranges is for IP multicast routing, for
 1158                          * which the range is big enough to require
 1159                          * all bits set.)
 1160                          */
hash[3] = hash[2] = hash[1] = hash[0] = 0xffff;
ifp->if_flags |= IFF_ALLMULTI;
 1163                         goto chipit;
 1164                 }
crc = 0xffffffff;
 1168                 for (i = 0; i < ETHER_ADDR_LEN; i++) {
octet = enm->enm_addrlo[i];
 1171                         for (j = 0; j < 8; j++) {
 1172                                 if ((crc & 1) ^ (octet & 1)) {
crc >>= 1;
crc ^= MC_POLY_LE;
 1175                                 }
 1176                                 else
crc >>= 1;
octet >>= 1;
 1179                         }
 1180                 }
crc >>= 26;
hash[crc >> 4] |= 1 << (crc & 0xf);
ETHER_NEXT_MULTI(step, enm);
 1185         }
ifp->if_flags &= ~IFF_ALLMULTI;
chipit:
 1190         /* Enable the hash filter */
bus_space_write_4(t, br, BE_BRI_HASHTAB0, hash[0]);
bus_space_write_4(t, br, BE_BRI_HASHTAB1, hash[1]);
bus_space_write_4(t, br, BE_BRI_HASHTAB2, hash[2]);
bus_space_write_4(t, br, BE_BRI_HASHTAB3, hash[3]);
v = bus_space_read_4(t, br, BE_BRI_RXCFG);
v &= ~BE_BR_RXCFG_PMISC;
v |= BE_BR_RXCFG_HENABLE;
bus_space_write_4(t, br, BE_BRI_RXCFG, v);
 1200 }
 1202 /*
 1203  * Set the tcvr to an idle state
 1204  */
 1205 void
be_mii_sync(struct be_softc *sc)
 1207 {
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t tr = sc->sc_tr;
 1210         int n = 32;
 1212         while (n--) {
bus_space_write_4(t, tr, BE_TRI_MGMTPAL,
MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | MGMT_PAL_OENAB);
 1215                 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
bus_space_write_4(t, tr, BE_TRI_MGMTPAL,
MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO |
MGMT_PAL_OENAB | MGMT_PAL_DCLOCK);
 1219                 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
 1220         }
 1221 }
 1223 void
be_pal_gate(struct be_softc *sc, int phy)
 1225 {
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t tr = sc->sc_tr;
u_int32_t v;
be_mii_sync(sc);
v = ~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE);
 1233         if (phy == BE_PHY_INTERNAL)
v &= ~TCVR_PAL_SERIAL;
bus_space_write_4(t, tr, BE_TRI_TCVRPAL, v);
 1237         (void)bus_space_read_4(t, tr, BE_TRI_TCVRPAL);
 1238 }
 1240 static int
be_tcvr_read_bit(struct be_softc *sc, int phy)
 1242 {
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t tr = sc->sc_tr;
 1245         int ret;
 1247         if (phy == BE_PHY_INTERNAL) {
bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_EXT_MDIO);
 1249                 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
bus_space_write_4(t, tr, BE_TRI_MGMTPAL,
MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK);
 1252                 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) &
MGMT_PAL_INT_MDIO) >> MGMT_PAL_INT_MDIO_SHIFT;
 1255         } else {
bus_space_write_4(t, tr, BE_TRI_MGMTPAL, MGMT_PAL_INT_MDIO);
 1257                 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
ret = (bus_space_read_4(t, tr, BE_TRI_MGMTPAL) &
MGMT_PAL_EXT_MDIO) >> MGMT_PAL_EXT_MDIO_SHIFT;
bus_space_write_4(t, tr, BE_TRI_MGMTPAL,
MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK);
 1262                 (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
 1263         }
 1265         return (ret);
 1266 }
 1268 static void
be_tcvr_write_bit(struct be_softc *sc, int phy, int bit)
 1270 {
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t tr = sc->sc_tr;
u_int32_t v;
 1275         if (phy == BE_PHY_INTERNAL) {
v = ((bit & 1) << MGMT_PAL_INT_MDIO_SHIFT) |
MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO;
 1278         } else {
v = ((bit & 1) << MGMT_PAL_EXT_MDIO_SHIFT)
 1280                     | MGMT_PAL_OENAB | MGMT_PAL_INT_MDIO;
 1281         }
bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v);
 1283         (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
bus_space_write_4(t, tr, BE_TRI_MGMTPAL, v | MGMT_PAL_DCLOCK);
 1285         (void)bus_space_read_4(t, tr, BE_TRI_MGMTPAL);
 1286 }
 1288 static void
be_mii_sendbits(struct be_softc *sc, int phy, u_int32_t data, int nbits)
 1290 {
 1291         int i;
 1293         for (i = 1 << (nbits - 1); i != 0; i >>= 1)
be_tcvr_write_bit(sc, phy, (data & i) != 0);
 1295 }
 1297 static int
be_mii_readreg(struct device *self, int phy, int reg)
 1299 {
 1300         struct be_softc *sc = (struct be_softc *)self;
 1301         int val = 0, i;
 1303         /*
 1304          * Read the PHY register by manually driving the MII control lines.
 1305          */
be_mii_sync(sc);
be_mii_sendbits(sc, phy, MII_COMMAND_START, 2);
be_mii_sendbits(sc, phy, MII_COMMAND_READ, 2);
be_mii_sendbits(sc, phy, phy, 5);
be_mii_sendbits(sc, phy, reg, 5);
 1312         (void) be_tcvr_read_bit(sc, phy);
 1313         (void) be_tcvr_read_bit(sc, phy);
 1315         for (i = 15; i >= 0; i--)
val |= (be_tcvr_read_bit(sc, phy) << i);
 1318         (void) be_tcvr_read_bit(sc, phy);
 1319         (void) be_tcvr_read_bit(sc, phy);
 1320         (void) be_tcvr_read_bit(sc, phy);
 1322         return (val);
 1323 }
 1325 void
be_mii_writereg(struct device *self, int phy, int reg, int val)
 1327 {
 1328         struct be_softc *sc = (struct be_softc *)self;
 1329         int i;
 1331         /*
 1332          * Write the PHY register by manually driving the MII control lines.
 1333          */
be_mii_sync(sc);
be_mii_sendbits(sc, phy, MII_COMMAND_START, 2);
be_mii_sendbits(sc, phy, MII_COMMAND_WRITE, 2);
be_mii_sendbits(sc, phy, phy, 5);
be_mii_sendbits(sc, phy, reg, 5);
be_tcvr_write_bit(sc, phy, 1);
be_tcvr_write_bit(sc, phy, 0);
 1343         for (i = 15; i >= 0; i--)
be_tcvr_write_bit(sc, phy, (val >> i) & 1);
 1345 }
 1347 int
be_mii_reset(struct be_softc *sc, int phy)
 1349 {
 1350         int n;
be_mii_writereg((struct device *)sc, phy, MII_BMCR,
BMCR_LOOP | BMCR_PDOWN | BMCR_ISO);
be_mii_writereg((struct device *)sc, phy, MII_BMCR, BMCR_RESET);
 1356         for (n = 16; n >= 0; n--) {
 1357                 int bmcr = be_mii_readreg((struct device *)sc, phy, MII_BMCR);
 1358                 if ((bmcr & BMCR_RESET) == 0)
 1359                         break;
DELAY(20);
 1361         }
 1362         if (n == 0) {
printf("%s: bmcr reset failed\n", sc->sc_dev.dv_xname);
 1364                 return (EIO);
 1365         }
 1367         return (0);
 1368 }
 1370 void
be_tick(void *arg)
 1372 {
 1373         struct be_softc *sc = arg;
 1374         int s = splnet();
mii_tick(&sc->sc_mii);
 1377         (void)be_intphy_service(sc, &sc->sc_mii, MII_TICK);
timeout_add(&sc->sc_tick_ch, hz);
splx(s);
 1381 }
 1383 void
be_mii_statchg(struct device *self)
 1385 {
 1386         struct be_softc *sc = (struct be_softc *)self;
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t br = sc->sc_br;
u_int instance;
u_int32_t v;
instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media);
 1393 #ifdef DIAGNOSTIC
 1394         if (instance > 1)
panic("be_mii_statchg: instance %d out of range", instance);
 1396 #endif
 1398         /* Update duplex mode in TX configuration */
v = bus_space_read_4(t, br, BE_BRI_TXCFG);
 1400         if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0)
v |= BE_BR_TXCFG_FULLDPLX;
 1402         else
v &= ~BE_BR_TXCFG_FULLDPLX;
bus_space_write_4(t, br, BE_BRI_TXCFG, v);
 1406         /* Change to appropriate gate in transceiver PAL */
be_pal_gate(sc, sc->sc_phys[instance]);
 1408 }
 1410 /*
 1411  * Get current media settings.
 1412  */
 1413 void
be_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
 1415 {
 1416         struct be_softc *sc = ifp->if_softc;
mii_pollstat(&sc->sc_mii);
 1419         (void)be_intphy_service(sc, &sc->sc_mii, MII_POLLSTAT);
ifmr->ifm_status = sc->sc_mii.mii_media_status;
ifmr->ifm_active = sc->sc_mii.mii_media_active;
 1423         return;
 1424 }
 1426 /*
 1427  * Set media options.
 1428  */
 1429 int
be_ifmedia_upd(struct ifnet *ifp)
 1431 {
 1432         struct be_softc *sc = ifp->if_softc;
 1433         int error;
 1435         if ((error = mii_mediachg(&sc->sc_mii)) != 0)
 1436                 return (error);
 1438         return (be_intphy_service(sc, &sc->sc_mii, MII_MEDIACHG));
 1439 }
 1441 /*
 1442  * Service routine for our pseudo-MII internal transceiver.
 1443  */
 1444 int
be_intphy_service(struct be_softc *sc, struct mii_data *mii, int cmd)
 1446 {
 1447         struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
 1448         int bmcr, bmsr;
 1449         int error;
 1451         switch (cmd) {
 1452         case MII_POLLSTAT:
 1453                 /*
 1454                  * If we're not polling our PHY instance, just return.
 1455                  */
 1456                 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst)
 1457                         return (0);
 1459                 break;
 1461         case MII_MEDIACHG:
 1463                 /*
 1464                  * If the media indicates a different PHY instance,
 1465                  * isolate ourselves.
 1466                  */
 1467                 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst) {
bmcr = be_mii_readreg((void *)sc,
BE_PHY_INTERNAL, MII_BMCR);
be_mii_writereg((void *)sc,
BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO);
sc->sc_mii_flags &= ~MIIF_HAVELINK;
sc->sc_intphy_curspeed = 0;
 1474                         return (0);
 1475                 }
 1478                 if ((error = be_mii_reset(sc, BE_PHY_INTERNAL)) != 0)
 1479                         return (error);
bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR);
 1483                 /*
 1484                  * Select the new mode and take out of isolation
 1485                  */
 1486                 if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX)
bmcr |= BMCR_S100;
 1488                 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_10_T)
bmcr &= ~BMCR_S100;
 1490                 else if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
 1491                         if ((sc->sc_mii_flags & MIIF_HAVELINK) != 0) {
bmcr &= ~BMCR_S100;
bmcr |= sc->sc_intphy_curspeed;
 1494                         } else {
 1495                                 /* Keep isolated until link is up */
bmcr |= BMCR_ISO;
sc->sc_mii_flags |= MIIF_DOINGAUTO;
 1498                         }
 1499                 }
 1501                 if ((IFM_OPTIONS(ife->ifm_media) & IFM_FDX) != 0)
bmcr |= BMCR_FDX;
 1503                 else
bmcr &= ~BMCR_FDX;
be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr);
 1507                 break;
 1509         case MII_TICK:
 1510                 /*
 1511                  * If we're not currently selected, just return.
 1512                  */
 1513                 if (IFM_INST(ife->ifm_media) != sc->sc_mii_inst)
 1514                         return (0);
 1516                 /* Only used for automatic media selection */
 1517                 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
 1518                         return (0);
 1520                 /* Is the interface even up? */
 1521                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
 1522                         return (0);
 1524                 /*
 1525                  * Check link status; if we don't have a link, try another
 1526                  * speed. We can't detect duplex mode, so half-duplex is
 1527                  * what we have to settle for.
 1528                  */
 1530                 /* Read twice in case the register is latched */
bmsr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR) |
be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMSR);
 1534                 if ((bmsr & BMSR_LINK) != 0) {
 1535                         /* We have a carrier */
bmcr = be_mii_readreg((void *)sc,
BE_PHY_INTERNAL, MII_BMCR);
 1539                         if ((sc->sc_mii_flags & MIIF_DOINGAUTO) != 0) {
bmcr = be_mii_readreg((void *)sc,
BE_PHY_INTERNAL, MII_BMCR);
sc->sc_mii_flags |= MIIF_HAVELINK;
sc->sc_intphy_curspeed = (bmcr & BMCR_S100);
sc->sc_mii_flags &= ~MIIF_DOINGAUTO;
bmcr &= ~BMCR_ISO;
be_mii_writereg((void *)sc,
BE_PHY_INTERNAL, MII_BMCR, bmcr);
printf("%s: link up at %s Mbps\n",
sc->sc_dev.dv_xname,
 1553                                     (bmcr & BMCR_S100) ? "100" : "10");
 1554                         }
 1555                         return (0);
 1556                 }
 1558                 if ((sc->sc_mii_flags & MIIF_DOINGAUTO) == 0) {
sc->sc_mii_flags |= MIIF_DOINGAUTO;
sc->sc_mii_flags &= ~MIIF_HAVELINK;
sc->sc_intphy_curspeed = 0;
printf("%s: link down\n", sc->sc_dev.dv_xname);
 1563                 }
 1565                 /* Only retry autonegotiation every 5 seconds. */
 1566                 if (++sc->sc_mii_ticks < 5)
 1567                         return(0);
sc->sc_mii_ticks = 0;
bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR);
 1571                 /* Just flip the fast speed bit */
bmcr ^= BMCR_S100;
be_mii_writereg((void *)sc, BE_PHY_INTERNAL, MII_BMCR, bmcr);
 1575                 break;
 1577         case MII_DOWN:
 1578                 /* Isolate this phy */
bmcr = be_mii_readreg((void *)sc, BE_PHY_INTERNAL, MII_BMCR);
be_mii_writereg((void *)sc,
BE_PHY_INTERNAL, MII_BMCR, bmcr | BMCR_ISO);
 1582                 return (0);
 1583         }
 1585         /* Update the media status. */
be_intphy_status(sc);
 1588         /* Callback if something changed. */
 1589         if (sc->sc_mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) {
 1590                 (*mii->mii_statchg)((struct device *)sc);
sc->sc_mii_active = mii->mii_media_active;
 1592         }
 1593         return (0);
 1594 }
 1596 /*
 1597  * Determine status of internal transceiver
 1598  */
 1599 void
be_intphy_status(struct be_softc *sc)
 1601 {
 1602         struct mii_data *mii = &sc->sc_mii;
 1603         int media_active, media_status;
 1604         int bmcr, bmsr;
media_status = IFM_AVALID;
media_active = 0;
 1609         /*
 1610          * Internal transceiver; do the work here.
 1611          */
bmcr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMCR);
 1614         switch (bmcr & (BMCR_S100 | BMCR_FDX)) {
 1615         case (BMCR_S100 | BMCR_FDX):
media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
 1617                 break;
 1618         case BMCR_S100:
media_active = IFM_ETHER | IFM_100_TX | IFM_HDX;
 1620                 break;
 1621         case BMCR_FDX:
media_active = IFM_ETHER | IFM_10_T | IFM_FDX;
 1623                 break;
 1624         case 0:
media_active = IFM_ETHER | IFM_10_T | IFM_HDX;
 1626                 break;
 1627         }
 1629         /* Read twice in case the register is latched */
bmsr = be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR)|
be_mii_readreg((struct device *)sc, BE_PHY_INTERNAL, MII_BMSR);
 1632         if (bmsr & BMSR_LINK)
media_status |=  IFM_ACTIVE;
mii->mii_media_status = media_status;
mii->mii_media_active = media_active;
 1637 }