cr 182 arch/i386/i386/db_interface.c uint32_t cr;
cr 199 arch/i386/i386/db_interface.c __asm__ __volatile__("movl %%cr0,%0" : "=r" (cr));
cr 200 arch/i386/i386/db_interface.c db_printf("cr0: 0x%08x\n", cr);
cr 202 arch/i386/i386/db_interface.c __asm__ __volatile__("movl %%cr2,%0" : "=r" (cr));
cr 203 arch/i386/i386/db_interface.c db_printf("cr2: 0x%08x\n", cr);
cr 205 arch/i386/i386/db_interface.c __asm__ __volatile__("movl %%cr3,%0" : "=r" (cr));
cr 206 arch/i386/i386/db_interface.c db_printf("cr3: 0x%08x\n", cr);
cr 208 arch/i386/i386/db_interface.c __asm__ __volatile__("movl %%cr4,%0" : "=r" (cr));
cr 209 arch/i386/i386/db_interface.c db_printf("cr4: 0x%08x\n", cr);
cr 51 crypto/crypto.c struct cryptoini *cr;
cr 95 crypto/crypto.c for (cr = cri; cr; cr = cr->cri_next) {
cr 96 crypto/crypto.c if (cpc->cc_alg[cr->cri_alg] == 0)
cr 104 crypto/crypto.c if (cr != NULL)
cr 77 dev/cardbus/cardbusvar.h #define CARDBUS_CLASS(cr) \
cr 78 dev/cardbus/cardbusvar.h (((cr) >> CARDBUS_CLASS_SHIFT) & CARDBUS_CLASS_MASK)
cr 82 dev/cardbus/cardbusvar.h #define CARDBUS_SUBCLASS(cr) \
cr 83 dev/cardbus/cardbusvar.h (((cr) >> CARDBUS_SUBCLASS_SHIFT) & CARDBUS_SUBCLASS_MASK)
cr 87 dev/cardbus/cardbusvar.h #define CARDBUS_INTERFACE(cr) \
cr 88 dev/cardbus/cardbusvar.h (((cr) >> CARDBUS_INTERFACE_SHIFT) & CARDBUS_INTERFACE_MASK)
cr 92 dev/cardbus/cardbusvar.h #define CARDBUS_REVISION(cr) \
cr 93 dev/cardbus/cardbusvar.h (((cr) >> CARDBUS_REVISION_SHIFT) & CARDBUS_REVISION_MASK)
cr 61 dev/ic/am7930reg.h u_char cr; /* command register (wo) */
cr 62 dev/ic/am7930reg.h #define ir cr /* interrupt register (ro) */
cr 426 dev/ic/rtw.c u_int8_t cr;
cr 434 dev/ic/rtw.c if ((cr = RTW_READ8(regs, RTW_CR) & RTW_CR_RST) == 0) {
cr 1102 dev/ic/rtw.c u_int8_t cr;
cr 1107 dev/ic/rtw.c cr = RTW_READ8(regs, RTW_CR);
cr 1112 dev/ic/rtw.c cr |= RTW_CR_MULRW;
cr 1117 dev/ic/rtw.c cr |= flags;
cr 1119 dev/ic/rtw.c cr &= ~flags;
cr 1120 dev/ic/rtw.c RTW_WRITE8(regs, RTW_CR, cr);
cr 1739 dev/ic/rtw.c uint8_t cr = 0;
cr 1747 dev/ic/rtw.c cr |= RTW_CR_TE | RTW_CR_RE;
cr 1751 dev/ic/rtw.c cr |= RTW_CR_RE;
cr 1762 dev/ic/rtw.c rtw_io_enable(regs, cr, 0);
cr 1790 dev/ic/rtw.c rtw_io_enable(regs, cr, 1);
cr 129 dev/isa/aps.c u_int8_t cr;
cr 160 dev/isa/aps.c cr = bus_space_read_1(iot, ioh, APS_STATE);
cr 161 dev/isa/aps.c if (cr > 0 && cr < 6)
cr 167 dev/isa/aps.c DPRINTF(("aps: state register 0x%x\n", cr));
cr 168 dev/isa/aps.c if (cr < 1 || cr > 5) {
cr 169 dev/isa/aps.c DPRINTF(("aps0: unsupported state %d\n", cr));
cr 298 dev/isa/aps.c u_int8_t cr;
cr 301 dev/isa/aps.c cr = bus_space_read_1(iot, ioh, reg);
cr 302 dev/isa/aps.c if (cr == val)
cr 100 dev/isa/it.c u_int8_t cr;
cr 112 dev/isa/it.c cr = bus_space_read_1(iot, ioh, ITC_DATA);
cr 114 dev/isa/it.c DPRINTF(("it: vendor id 0x%x\n", cr));
cr 115 dev/isa/it.c if (cr != IT_ID_IT87)
cr 135 dev/isa/it.c u_int8_t cr;
cr 165 dev/isa/it.c cr = it_readreg(sc, ITD_CONFIG);
cr 166 dev/isa/it.c cr |= 0x01 | 0x08;
cr 167 dev/isa/it.c it_writereg(sc, ITD_CONFIG, cr);
cr 1263 dev/pci/autri.c u_int32_t reg, cr[5];
cr 1343 dev/pci/autri.c cr[0] = (cso << 16) | (alpha_fms & 0x0000ffff);
cr 1344 dev/pci/autri.c cr[1] = dmaaddr;
cr 1345 dev/pci/autri.c cr[2] = (eso << 16) | (dch[ch] & 0x0000ffff);
cr 1346 dev/pci/autri.c cr[3] = fm_vol;
cr 1347 dev/pci/autri.c cr[4] = ctrl;
cr 1350 dev/pci/autri.c cr[0] = (dch[ch] << 24) | (cso & 0x00ffffff);
cr 1351 dev/pci/autri.c cr[1] = dmaaddr;
cr 1352 dev/pci/autri.c cr[2] = ((dch[ch] << 16) & 0xff000000) | (eso & 0x00ffffff);
cr 1353 dev/pci/autri.c cr[3] = (alpha_fms << 16) | (fm_vol & 0x0000ffff);
cr 1354 dev/pci/autri.c cr[4] = ctrl;
cr 1357 dev/pci/autri.c cr[0] = (cso << 16) | (alpha_fms & 0x0000ffff);
cr 1358 dev/pci/autri.c cr[1] = dmaaddr;
cr 1359 dev/pci/autri.c cr[2] = (eso << 16) | (dch[ch] & 0x0000ffff);
cr 1360 dev/pci/autri.c cr[3] = attribute;
cr 1361 dev/pci/autri.c cr[4] = ctrl;
cr 1364 dev/pci/autri.c cr[0] = (cso << 16) | (alpha_fms & 0x0000ffff);
cr 1365 dev/pci/autri.c cr[1] = dmaaddr;
cr 1366 dev/pci/autri.c cr[2] = (eso << 16) | (dch[ch] & 0x0000ffff);
cr 1367 dev/pci/autri.c cr[3] = 0;
cr 1368 dev/pci/autri.c cr[4] = ctrl;
cr 1379 dev/pci/autri.c TWRITE4(sc, AUTRI_ARAM_CR + i*sizeof(cr[0]), cr[i]);
cr 1380 dev/pci/autri.c DPRINTFN(5,("cr[%d] : 0x%08X\n", i, cr[i]));
cr 1648 dev/pci/noct.c noct_ksigbits(cr)
cr 1649 dev/pci/noct.c struct crparam *cr;
cr 1651 dev/pci/noct.c u_int plen = (cr->crp_nbits + 7) / 8;
cr 1653 dev/pci/noct.c u_int8_t c, *p = cr->crp_p;
cr 1670 dev/pci/noct.c noct_kload(sc, cr, wp)
cr 1672 dev/pci/noct.c struct crparam *cr;
cr 1687 dev/pci/noct.c bits = noct_ksigbits(cr);
cr 1713 dev/pci/noct.c cr->crp_p[i];
cr 5319 dev/pci/pciide.c pcireg_t cr, interface;
cr 5362 dev/pci/pciide.c cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG);
cr 5363 dev/pci/pciide.c cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT);
cr 5364 dev/pci/pciide.c pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr);
cr 5396 dev/pci/pciide.c cr &= ~(PCIIDE_CHAN_EN(channel) << PCI_INTERFACE_SHIFT);
cr 5398 dev/pci/pciide.c PCI_CLASS_REG, cr);
cr 114 dev/pci/pcireg.h #define PCI_CLASS(cr) \
cr 115 dev/pci/pcireg.h (((cr) >> PCI_CLASS_SHIFT) & PCI_CLASS_MASK)
cr 119 dev/pci/pcireg.h #define PCI_SUBCLASS(cr) \
cr 120 dev/pci/pcireg.h (((cr) >> PCI_SUBCLASS_SHIFT) & PCI_SUBCLASS_MASK)
cr 124 dev/pci/pcireg.h #define PCI_INTERFACE(cr) \
cr 125 dev/pci/pcireg.h (((cr) >> PCI_INTERFACE_SHIFT) & PCI_INTERFACE_MASK)
cr 129 dev/pci/pcireg.h #define PCI_REVISION(cr) \
cr 130 dev/pci/pcireg.h (((cr) >> PCI_REVISION_SHIFT) & PCI_REVISION_MASK)
cr 467 dev/pci/pcireg.h #define PCI_CAPLIST_NEXT(cr) (((cr) >> 8) & 0xff)
cr 468 dev/pci/pcireg.h #define PCI_CAPLIST_CAP(cr) ((cr) & 0xff)
cr 93 dev/pci/safe.c int safe_ksigbits(struct crparam *cr);
cr 1940 dev/pci/safe.c safe_ksigbits(struct crparam *cr)
cr 1942 dev/pci/safe.c u_int plen = (cr->crp_nbits + 7) / 8;
cr 1944 dev/pci/safe.c u_int8_t c, *p = cr->crp_p;
cr 2439 dev/pci/ubsec.c ubsec_ksigbits(struct crparam *cr)
cr 2441 dev/pci/ubsec.c u_int plen = (cr->crp_nbits + 7) / 8;
cr 2443 dev/pci/ubsec.c u_int8_t c, *p = cr->crp_p;
cr 1031 dev/sbus/be.c bus_space_handle_t cr = sc->sc_cr;
cr 1087 dev/sbus/be.c bus_space_write_4(t, cr, BE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma);
cr 1088 dev/sbus/be.c bus_space_write_4(t, cr, BE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma);
cr 1091 dev/sbus/be.c bus_space_write_4(t, cr, BE_CRI_RXWBUF, qecaddr);
cr 1092 dev/sbus/be.c bus_space_write_4(t, cr, BE_CRI_RXRBUF, qecaddr);
cr 1093 dev/sbus/be.c bus_space_write_4(t, cr, BE_CRI_TXWBUF, qecaddr + qec->sc_rsize);
cr 1094 dev/sbus/be.c bus_space_write_4(t, cr, BE_CRI_TXRBUF, qecaddr + qec->sc_rsize);
cr 1096 dev/sbus/be.c bus_space_write_4(t, cr, BE_CRI_RIMASK, 0);
cr 1097 dev/sbus/be.c bus_space_write_4(t, cr, BE_CRI_TIMASK, 0);
cr 1098 dev/sbus/be.c bus_space_write_4(t, cr, BE_CRI_QMASK, 0);
cr 1099 dev/sbus/be.c bus_space_write_4(t, cr, BE_CRI_BMASK, 0);
cr 1100 dev/sbus/be.c bus_space_write_4(t, cr, BE_CRI_CCNT, 0);
cr 521 dev/sbus/qe.c bus_space_handle_t cr = sc->sc_cr;
cr 534 dev/sbus/qe.c bus_space_write_4(t, cr, QE_CRI_CTRL, QE_CR_CTRL_RESET);
cr 536 dev/sbus/qe.c if ((bus_space_read_4(t, cr, QE_CRI_CTRL) &
cr 1003 dev/sbus/qe.c bus_space_handle_t cr = sc->sc_cr;
cr 1020 dev/sbus/qe.c bus_space_write_4(t, cr, QE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma);
cr 1021 dev/sbus/qe.c bus_space_write_4(t, cr, QE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma);
cr 1023 dev/sbus/qe.c bus_space_write_4(t, cr, QE_CRI_RIMASK, 0);
cr 1024 dev/sbus/qe.c bus_space_write_4(t, cr, QE_CRI_TIMASK, 0);
cr 1025 dev/sbus/qe.c bus_space_write_4(t, cr, QE_CRI_QMASK, 0);
cr 1026 dev/sbus/qe.c bus_space_write_4(t, cr, QE_CRI_MMASK, QE_CR_MMASK_RXCOLL);
cr 1027 dev/sbus/qe.c bus_space_write_4(t, cr, QE_CRI_CCNT, 0);
cr 1028 dev/sbus/qe.c bus_space_write_4(t, cr, QE_CRI_PIPG, 0);
cr 1031 dev/sbus/qe.c bus_space_write_4(t, cr, QE_CRI_RXWBUF, qecaddr);
cr 1032 dev/sbus/qe.c bus_space_write_4(t, cr, QE_CRI_RXRBUF, qecaddr);
cr 1033 dev/sbus/qe.c bus_space_write_4(t, cr, QE_CRI_TXWBUF, qecaddr + qec->sc_rsize);
cr 1034 dev/sbus/qe.c bus_space_write_4(t, cr, QE_CRI_TXRBUF, qecaddr + qec->sc_rsize);
cr 1041 dev/sbus/qe.c bus_space_read_4(t, cr, QE_CRI_QMASK);
cr 108 dev/sbus/vigra.c u_int32_t cr;
cr 1772 dev/softraid.c sr_print_uuid(struct sr_uuid *uuid, int cr)
cr 1780 dev/softraid.c if (cr)
cr 775 kern/kern_prot.c struct ucred *cr;
cr 777 kern/kern_prot.c cr = pool_get(&ucred_pool, PR_WAITOK);
cr 778 kern/kern_prot.c bzero((caddr_t)cr, sizeof(*cr));
cr 779 kern/kern_prot.c cr->cr_ref = 1;
cr 780 kern/kern_prot.c return (cr);
cr 788 kern/kern_prot.c crfree(struct ucred *cr)
cr 791 kern/kern_prot.c if (--cr->cr_ref == 0)
cr 792 kern/kern_prot.c pool_put(&ucred_pool, cr);
cr 799 kern/kern_prot.c crcopy(struct ucred *cr)
cr 803 kern/kern_prot.c if (cr->cr_ref == 1)
cr 804 kern/kern_prot.c return (cr);
cr 806 kern/kern_prot.c *newcr = *cr;
cr 807 kern/kern_prot.c crfree(cr);
cr 816 kern/kern_prot.c crdup(struct ucred *cr)
cr 821 kern/kern_prot.c *newcr = *cr;
cr 69 miscfs/procfs/procfs_status.c struct ucred *cr;
cr 132 miscfs/procfs/procfs_status.c cr = p->p_ucred;
cr 134 miscfs/procfs/procfs_status.c snprintf(ps, sizeof(ps), " %u, %u", cr->cr_uid, cr->cr_gid);
cr 136 miscfs/procfs/procfs_status.c for (i = 0; i < cr->cr_ngroups; i++) {
cr 137 miscfs/procfs/procfs_status.c snprintf(ps, sizeof(ps), ",%u", cr->cr_groups[i]);
cr 218 netbt/rfcomm.h #define RFCOMM_MKADDRESS(cr, dlci) \
cr 219 netbt/rfcomm.h ((((dlci) & 0x3f) << 2) | ((cr) << 1) | 0x01)
cr 227 netbt/rfcomm.h #define RFCOMM_MKMCC_TYPE(cr, type) ((((type) << 2) | ((cr) << 1) | 0x01))
cr 991 netbt/rfcomm_session.c int type, cr, len;
cr 1018 netbt/rfcomm_session.c cr = RFCOMM_CR(b);
cr 1040 netbt/rfcomm_session.c (cr ? "command" : "response"), type, len);
cr 1047 netbt/rfcomm_session.c rfcomm_session_recv_mcc_test(rs, cr, m);
cr 1051 netbt/rfcomm_session.c rfcomm_session_recv_mcc_fcon(rs, cr);
cr 1055 netbt/rfcomm_session.c rfcomm_session_recv_mcc_fcoff(rs, cr);
cr 1059 netbt/rfcomm_session.c rfcomm_session_recv_mcc_msc(rs, cr, m);
cr 1063 netbt/rfcomm_session.c rfcomm_session_recv_mcc_rpn(rs, cr, m);
cr 1067 netbt/rfcomm_session.c rfcomm_session_recv_mcc_rls(rs, cr, m);
cr 1071 netbt/rfcomm_session.c rfcomm_session_recv_mcc_pn(rs, cr, m);
cr 1075 netbt/rfcomm_session.c rfcomm_session_recv_mcc_nsc(rs, cr, m);
cr 1079 netbt/rfcomm_session.c b = RFCOMM_MKMCC_TYPE(cr, type);
cr 1091 netbt/rfcomm_session.c rfcomm_session_recv_mcc_test(struct rfcomm_session *rs, int cr, struct mbuf *m)
cr 1096 netbt/rfcomm_session.c if (cr == 0) /* ignore ack */
cr 1120 netbt/rfcomm_session.c rfcomm_session_recv_mcc_fcon(struct rfcomm_session *rs, int cr)
cr 1123 netbt/rfcomm_session.c if (cr == 0) /* ignore ack */
cr 1134 netbt/rfcomm_session.c rfcomm_session_recv_mcc_fcoff(struct rfcomm_session *rs, int cr)
cr 1137 netbt/rfcomm_session.c if (cr == 0) /* ignore ack */
cr 1148 netbt/rfcomm_session.c rfcomm_session_recv_mcc_msc(struct rfcomm_session *rs, int cr, struct mbuf *m)
cr 1164 netbt/rfcomm_session.c if (cr == 0) { /* ignore acks */
cr 1206 netbt/rfcomm_session.c rfcomm_session_recv_mcc_rpn(struct rfcomm_session *rs, int cr, struct mbuf *m)
cr 1211 netbt/rfcomm_session.c if (cr == 0) /* ignore ack */
cr 1270 netbt/rfcomm_session.c rfcomm_session_recv_mcc_rls(struct rfcomm_session *rs, int cr, struct mbuf *m)
cr 1274 netbt/rfcomm_session.c if (cr == 0) /* ignore ack */
cr 1299 netbt/rfcomm_session.c rfcomm_session_recv_mcc_pn(struct rfcomm_session *rs, int cr, struct mbuf *m)
cr 1316 netbt/rfcomm_session.c if (cr) { /* Command */
cr 1421 netbt/rfcomm_session.c int cr, struct mbuf *m)
cr 1453 netbt/rfcomm_session.c uint8_t fcs, cr;
cr 1473 netbt/rfcomm_session.c cr = IS_INITIATOR(rs) ? 0 : 1;
cr 1475 netbt/rfcomm_session.c cr = IS_INITIATOR(rs) ? 1 : 0;
cr 1478 netbt/rfcomm_session.c hdr->address = RFCOMM_MKADDRESS(cr, dlci);
cr 1626 netbt/rfcomm_session.c rfcomm_session_send_mcc(struct rfcomm_session *rs, int cr,
cr 1643 netbt/rfcomm_session.c *hdr++ = RFCOMM_MKMCC_TYPE(cr, type);
cr 1687 netbt/rfcomm_session.c (cr ? "command" : "response"), type, m->m_pkthdr.len);
cr 566 nfs/nfs_subs.c nfsm_rpchead(cr, nmflag, procid, auth_type, auth_len, auth_str, verf_len,
cr 568 nfs/nfs_subs.c struct ucred *cr;
cr 640 nfs/nfs_subs.c *tl++ = txdr_unsigned(cr->cr_uid);
cr 641 nfs/nfs_subs.c *tl++ = txdr_unsigned(cr->cr_gid);
cr 645 nfs/nfs_subs.c *tl++ = txdr_unsigned(cr->cr_groups[i]);
cr 52 sys/ucred.h #define crhold(cr) (cr)->cr_ref++
cr 56 sys/ucred.h struct ucred *crcopy(struct ucred *cr);
cr 57 sys/ucred.h struct ucred *crdup(struct ucred *cr);
cr 58 sys/ucred.h void crfree(struct ucred *cr);
cr 129 ufs/ufs/quota.h #define ufs_quota_alloc_blocks(i, c, cr) ufs_quota_alloc_blocks2(i, c, cr, 0)
cr 130 ufs/ufs/quota.h #define ufs_quota_free_blocks(i, c, cr) ufs_quota_free_blocks2(i, c, cr, 0)
cr 131 ufs/ufs/quota.h #define ufs_quota_alloc_inode(i, cr) ufs_quota_alloc_inode2(i, cr, 0)
cr 132 ufs/ufs/quota.h #define ufs_quota_free_inode(i, cr) ufs_quota_free_inode2(i, cr, 0)
cr 700 ufs/ufs/ufs_lookup.c struct ucred *cr;
cr 711 ufs/ufs/ufs_lookup.c cr = cnp->cn_cred;
cr 729 ufs/ufs/ufs_lookup.c cr, flags, &bp)) != 0) {
cr 929 ufs/ufs/ufs_lookup.c error = UFS_TRUNCATE(dp, (off_t)dp->i_endoff, IO_SYNC, cr);
cr 79 xfs/xfs_syscalls-common.c xfs_crcopy(struct ucred *cr)
cr 83 xfs/xfs_syscalls-common.c if (crshared(cr)) {
cr 84 xfs/xfs_syscalls-common.c ncr = crdup(cr);
cr 85 xfs/xfs_syscalls-common.c crfree(cr);
cr 88 xfs/xfs_syscalls-common.c return cr;