root/dev/sbus/qe.c

DEFINITIONS

1. qematch
2. qeattach
3. qe_get
4. qe_put
5. qe_read
6. qestart
7. qestop
8. qereset
9. qewatchdog
10. qeintr
11. qe_tint
12. qe_rint
13. qe_eint
14. qeioctl
15. qeinit
16. qe_mcreset
17. qe_ifmedia_sts
18. qe_ifmedia_upd

    1 /*      $OpenBSD: qe.c,v 1.20 2006/06/21 18:08:47 jason Exp $   */
    2 /*      $NetBSD: qe.c,v 1.16 2001/03/30 17:30:18 christos Exp $ */
    4 /*-
    5  * Copyright (c) 1999 The NetBSD Foundation, Inc.
    6  * All rights reserved.
    7  *
    8  * This code is derived from software contributed to The NetBSD Foundation
    9  * by Paul Kranenburg.
   10  *
   11  * Redistribution and use in source and binary forms, with or without
   12  * modification, are permitted provided that the following conditions
   13  * are met:
   14  * 1. Redistributions of source code must retain the above copyright
   15  *    notice, this list of conditions and the following disclaimer.
   16  * 2. Redistributions in binary form must reproduce the above copyright
   17  *    notice, this list of conditions and the following disclaimer in the
   18  *    documentation and/or other materials provided with the distribution.
   19  * 3. All advertising materials mentioning features or use of this software
   20  *    must display the following acknowledgement:
   21  *        This product includes software developed by the NetBSD
   22  *        Foundation, Inc. and its contributors.
   23  * 4. Neither the name of The NetBSD Foundation nor the names of its
   24  *    contributors may be used to endorse or promote products derived
   25  *    from this software without specific prior written permission.
   26  *
   27  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   29  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   30  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   37  * POSSIBILITY OF SUCH DAMAGE.
   38  */
   40 /*
   41  * Copyright (c) 1998 Jason L. Wright.
   42  * All rights reserved.
   43  *
   44  * Redistribution and use in source and binary forms, with or without
   45  * modification, are permitted provided that the following conditions
   46  * are met:
   47  * 1. Redistributions of source code must retain the above copyright
   48  *    notice, this list of conditions and the following disclaimer.
   49  * 2. Redistributions in binary form must reproduce the above copyright
   50  *    notice, this list of conditions and the following disclaimer in the
   51  *    documentation and/or other materials provided with the distribution.
   52  *
   53  * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
   54  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   55  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   56  * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
   57  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   58  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   59  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   60  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   61  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   62  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   63  */
   65 /*
   66  * Driver for the SBus qec+qe QuadEthernet board.
   67  *
   68  * This driver was written using the AMD MACE Am79C940 documentation, some
   69  * ideas gleaned from the S/Linux driver for this card, Solaris header files,
   70  * and a loan of a card from Paul Southworth of the Internet Engineering
   71  * Group (www.ieng.com).
   72  */
   74 #define QEDEBUG
   76 #include "bpfilter.h"
   78 #include <sys/param.h>
   79 #include <sys/systm.h>
   80 #include <sys/kernel.h>
   81 #include <sys/errno.h>
   82 #include <sys/ioctl.h>
   83 #include <sys/mbuf.h>
   84 #include <sys/socket.h>
   85 #include <sys/syslog.h>
   86 #include <sys/device.h>
   87 #include <sys/malloc.h>
   89 #include <net/if.h>
   90 #include <net/if_dl.h>
   91 #include <net/if_types.h>
   92 #include <net/netisr.h>
   93 #include <net/if_media.h>
   95 #ifdef INET
   96 #include <netinet/in.h>
   97 #include <netinet/in_systm.h>
   98 #include <netinet/in_var.h>
   99 #include <netinet/ip.h>
  100 #include <netinet/if_ether.h>
  101 #endif
  103 #if NBPFILTER > 0
  104 #include <net/bpf.h>
  105 #endif
  107 #include <machine/bus.h>
  108 #include <machine/intr.h>
  109 #include <machine/autoconf.h>
  111 #include <dev/sbus/sbusvar.h>
  112 #include <dev/sbus/qecreg.h>
  113 #include <dev/sbus/qecvar.h>
  114 #include <dev/sbus/qereg.h>
  116 struct qe_softc {
  117         struct  device  sc_dev;         /* base device */
bus_space_tag_t sc_bustag;      /* bus & dma tags */
bus_dma_tag_t   sc_dmatag;
bus_dmamap_t    sc_dmamap;
  121         struct  arpcom sc_arpcom;
  122         struct  ifmedia sc_ifmedia;     /* interface media */
  124         struct  qec_softc *sc_qec;      /* QEC parent */
bus_space_handle_t      sc_qr;  /* QEC registers */
bus_space_handle_t      sc_mr;  /* MACE registers */
bus_space_handle_t      sc_cr;  /* channel registers */
  130         int     sc_channel;             /* channel number */
u_int   sc_rev;                 /* board revision */
  133         int     sc_burst;
  135         struct  qec_ring        sc_rb;  /* Packet Ring Buffer */
  137 #ifdef QEDEBUG
  138         int     sc_debug;
  139 #endif
  140 };
  142 int     qematch(struct device *, void *, void *);
  143 void    qeattach(struct device *, struct device *, void *);
  145 void    qeinit(struct qe_softc *);
  146 void    qestart(struct ifnet *);
  147 void    qestop(struct qe_softc *);
  148 void    qewatchdog(struct ifnet *);
  149 int     qeioctl(struct ifnet *, u_long, caddr_t);
  150 void    qereset(struct qe_softc *);
  152 int     qeintr(void *);
  153 int     qe_eint(struct qe_softc *, u_int32_t);
  154 int     qe_rint(struct qe_softc *);
  155 int     qe_tint(struct qe_softc *);
  156 void    qe_mcreset(struct qe_softc *);
  158 int     qe_put(struct qe_softc *, int, struct mbuf *);
  159 void    qe_read(struct qe_softc *, int, int);
  160 struct mbuf     *qe_get(struct qe_softc *, int, int);
  162 /* ifmedia callbacks */
  163 void    qe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
  164 int     qe_ifmedia_upd(struct ifnet *);
  166 struct cfattach qe_ca = {
  167         sizeof(struct qe_softc), qematch, qeattach
  168 };
  170 struct cfdriver qe_cd = {
NULL, "qe", DV_IFNET
  172 };
  174 int
qematch(parent, vcf, aux)
  176         struct device *parent;
  177         void *vcf;
  178         void *aux;
  179 {
  180         struct cfdata *cf = vcf;
  181         struct sbus_attach_args *sa = aux;
  183         return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0);
  184 }
  186 void
qeattach(parent, self, aux)
  188         struct device *parent, *self;
  189         void *aux;
  190 {
  191         struct sbus_attach_args *sa = aux;
  192         struct qec_softc *qec = (struct qec_softc *)parent;
  193         struct qe_softc *sc = (struct qe_softc *)self;
  194         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
  195         int node = sa->sa_node;
bus_dma_tag_t dmatag = sa->sa_dmatag;
bus_dma_segment_t seg;
bus_size_t size;
  199         int rseg, error;
  200         extern void myetheraddr(u_char *);
  202         /* Pass on the bus tags */
sc->sc_bustag = sa->sa_bustag;
sc->sc_dmatag = sa->sa_dmatag;
  206         if (sa->sa_nreg < 2) {
printf("%s: only %d register sets\n",
self->dv_xname, sa->sa_nreg);
  209                 return;
  210         }
  212         if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot,
  213             (bus_addr_t)sa->sa_reg[0].sbr_offset,
  214             (bus_size_t)sa->sa_reg[0].sbr_size, 0, 0, &sc->sc_cr) != 0) {
printf("%s: cannot map registers\n", self->dv_xname);
  216                 return;
  217         }
  219         if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[1].sbr_slot,
  220             (bus_addr_t)sa->sa_reg[1].sbr_offset,
  221             (bus_size_t)sa->sa_reg[1].sbr_size, 0, 0, &sc->sc_mr) != 0) {
printf("%s: cannot map registers\n", self->dv_xname);
  223                 return;
  224         }
sc->sc_rev = getpropint(node, "mace-version", -1);
printf(" rev %x", sc->sc_rev);
sc->sc_qec = qec;
sc->sc_qr = qec->sc_regs;
sc->sc_channel = getpropint(node, "channel#", -1);
sc->sc_burst = qec->sc_burst;
qestop(sc);
  237         /* Note: no interrupt level passed */
  238         if (bus_intr_establish(sa->sa_bustag, 0, IPL_NET, 0, qeintr, sc,
self->dv_xname) == NULL) {
printf(": no interrupt established\n");
  241                 return;
  242         }
myetheraddr(sc->sc_arpcom.ac_enaddr);
  246         /*
  247          * Allocate descriptor ring and buffers.
  248          */
  250         /* for now, allocate as many bufs as there are ring descriptors */
sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE;
sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE;
size =
QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) +
QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) +
sc->sc_rb.rb_ntbuf * QE_PKT_BUF_SZ +
sc->sc_rb.rb_nrbuf * QE_PKT_BUF_SZ;
  260         /* Get a DMA handle */
  261         if ((error = bus_dmamap_create(dmatag, size, 1, size, 0,
BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) {
printf("%s: DMA map create error %d\n", self->dv_xname, error);
  264                 return;
  265         }
  267         /* Allocate DMA buffer */
  268         if ((error = bus_dmamem_alloc(dmatag, size, 0, 0,
  269             &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
printf("%s: DMA buffer alloc error %d\n",
self->dv_xname, error);
  272                 return;
  273         }
  275         /* Map DMA buffer in CPU addressable space */
  276         if ((error = bus_dmamem_map(dmatag, &seg, rseg, size,
  277             &sc->sc_rb.rb_membase,
BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
printf("%s: DMA buffer map error %d\n",
self->dv_xname, error);
bus_dmamem_free(dmatag, &seg, rseg);
  282                 return;
  283         }
  285         /* Load the buffer */
  286         if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap,
sc->sc_rb.rb_membase, size, NULL, BUS_DMA_NOWAIT)) != 0) {
printf("%s: DMA buffer map load error %d\n",
self->dv_xname, error);
bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size);
bus_dmamem_free(dmatag, &seg, rseg);
  292                 return;
  293         }
sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr;
  296         /* Initialize media properties */
ifmedia_init(&sc->sc_ifmedia, 0, qe_ifmedia_upd, qe_ifmedia_sts);
ifmedia_add(&sc->sc_ifmedia,
IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,0), 0, NULL);
ifmedia_add(&sc->sc_ifmedia,
IFM_MAKEWORD(IFM_ETHER,IFM_10_5,0,0), 0, NULL);
ifmedia_add(&sc->sc_ifmedia,
IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,0), 0, NULL);
ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO);
bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
ifp->if_softc = sc;
ifp->if_start = qestart;
ifp->if_ioctl = qeioctl;
ifp->if_watchdog = qewatchdog;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS |
IFF_MULTICAST;
IFQ_SET_READY(&ifp->if_snd);
  315         /* Attach the interface. */
if_attach(ifp);
ether_ifattach(ifp);
printf(" address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr));
  320 }
  322 /*
  323  * Pull data off an interface.
  324  * Len is the length of data, with local net header stripped.
  325  * We copy the data into mbufs.  When full cluster sized units are present,
  326  * we copy into clusters.
  327  */
  328 struct mbuf *
qe_get(sc, idx, totlen)
  330         struct qe_softc *sc;
  331         int idx, totlen;
  332 {
  333         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
  334         struct mbuf *m;
  335         struct mbuf *top, **mp;
  336         int len, pad, boff = 0;
caddr_t bp;
bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * QE_PKT_BUF_SZ;
MGETHDR(m, M_DONTWAIT, MT_DATA);
  342         if (m == NULL)
  343                 return (NULL);
m->m_pkthdr.rcvif = ifp;
m->m_pkthdr.len = totlen;
pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header);
m->m_data += pad;
len = MHLEN - pad;
top = NULL;
mp = &top;
  352         while (totlen > 0) {
  353                 if (top) {
MGET(m, M_DONTWAIT, MT_DATA);
  355                         if (m == NULL) {
m_freem(top);
  357                                 return (NULL);
  358                         }
len = MLEN;
  360                 }
  361                 if (top && totlen >= MINCLSIZE) {
MCLGET(m, M_DONTWAIT);
  363                         if (m->m_flags & M_EXT)
len = MCLBYTES;
  365                 }
m->m_len = len = min(totlen, len);
bcopy(bp + boff, mtod(m, caddr_t), len);
boff += len;
totlen -= len;
  370                 *mp = m;
mp = &m->m_next;
  372         }
  374         return (top);
  375 }
  377 /*
  378  * Routine to copy from mbuf chain to transmit buffer in
  379  * network buffer memory.
  380  */
  381 __inline__ int
qe_put(sc, idx, m)
  383         struct qe_softc *sc;
  384         int idx;
  385         struct mbuf *m;
  386 {
  387         struct mbuf *n;
  388         int len, tlen = 0, boff = 0;
caddr_t bp;
bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * QE_PKT_BUF_SZ;
  393         for (; m; m = n) {
len = m->m_len;
  395                 if (len == 0) {
MFREE(m, n);
  397                         continue;
  398                 }
bcopy(mtod(m, caddr_t), bp+boff, len);
boff += len;
tlen += len;
MFREE(m, n);
  403         }
  404         return (tlen);
  405 }
  407 /*
  408  * Pass a packet to the higher levels.
  409  */
  410 __inline__ void
qe_read(sc, idx, len)
  412         struct qe_softc *sc;
  413         int idx, len;
  414 {
  415         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
  416         struct mbuf *m;
  418         if (len <= sizeof(struct ether_header) ||
len > ETHERMTU + sizeof(struct ether_header)) {
printf("%s: invalid packet size %d; dropping\n",
ifp->if_xname, len);
ifp->if_ierrors++;
  425                 return;
  426         }
  428         /*
  429          * Pull packet off interface.
  430          */
m = qe_get(sc, idx, len);
  432         if (m == NULL) {
ifp->if_ierrors++;
  434                 return;
  435         }
ifp->if_ipackets++;
  438 #if NBPFILTER > 0
  439         /*
  440          * Check if there's a BPF listener on this interface.
  441          * If so, hand off the raw packet to BPF.
  442          */
  443         if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN);
  445 #endif
  446         /* Pass the packet up. */
ether_input_mbuf(ifp, m);
  448 }
  450 /*
  451  * Start output on interface.
  452  * We make two assumptions here:
  453  *  1) that the current priority is set to splnet _before_ this code
  454  *     is called *and* is returned to the appropriate priority after
  455  *     return
  456  *  2) that the IFF_OACTIVE flag is checked before this code is called
  457  *     (i.e. that the output part of the interface is idle)
  458  */
  459 void
qestart(ifp)
  461         struct ifnet *ifp;
  462 {
  463         struct qe_softc *sc = (struct qe_softc *)ifp->if_softc;
  464         struct qec_xd *txd = sc->sc_rb.rb_txd;
  465         struct mbuf *m;
  466         unsigned int bix, len;
  467         unsigned int ntbuf = sc->sc_rb.rb_ntbuf;
  469         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
  470                 return;
bix = sc->sc_rb.rb_tdhead;
  474         for (;;) {
IFQ_POLL(&ifp->if_snd, m);
  476                 if (m == NULL)
  477                         break;
IFQ_DEQUEUE(&ifp->if_snd, m);
  481 #if NBPFILTER > 0
  482                 /*
  483                  * If BPF is listening on this interface, let it see the
  484                  * packet before we commit it to the wire.
  485                  */
  486                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT);
  488 #endif
  490                 /*
  491                  * Copy the mbuf chain into the transmit buffer.
  492                  */
len = qe_put(sc, bix, m);
  495                 /*
  496                  * Initialize transmit registers and start transmission
  497                  */
txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP |
  499                     (len & QEC_XD_LENGTH);
bus_space_write_4(sc->sc_bustag, sc->sc_cr, QE_CRI_CTRL,
QE_CR_CTRL_TWAKEUP);
  503                 if (++bix == QEC_XD_RING_MAXSIZE)
bix = 0;
  506                 if (++sc->sc_rb.rb_td_nbusy == ntbuf) {
ifp->if_flags |= IFF_OACTIVE;
  508                         break;
  509                 }
  510         }
sc->sc_rb.rb_tdhead = bix;
  513 }
  515 void
qestop(sc)
  517         struct qe_softc *sc;
  518 {       
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t mr = sc->sc_mr;
bus_space_handle_t cr = sc->sc_cr;
  522         int n;
  524         /* Stop the schwurst */
bus_space_write_1(t, mr, QE_MRI_BIUCC, QE_MR_BIUCC_SWRST);
  526         for (n = 200; n > 0; n--) {
  527                 if ((bus_space_read_1(t, mr, QE_MRI_BIUCC) &
QE_MR_BIUCC_SWRST) == 0)
  529                         break;
DELAY(20);
  531         }
  533         /* then reset */
bus_space_write_4(t, cr, QE_CRI_CTRL, QE_CR_CTRL_RESET);
  535         for (n = 200; n > 0; n--) {
  536                 if ((bus_space_read_4(t, cr, QE_CRI_CTRL) &
QE_CR_CTRL_RESET) == 0)
  538                         break;
DELAY(20);
  540         }
  541 }
  543 /*
  544  * Reset interface.
  545  */
  546 void
qereset(sc)
  548         struct qe_softc *sc;
  549 {
  550         int s;
s = splnet();
qestop(sc);
qeinit(sc);
splx(s);
  556 }
  558 void
qewatchdog(ifp)
  560         struct ifnet *ifp;
  561 {
  562         struct qe_softc *sc = ifp->if_softc;
log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname);
ifp->if_oerrors++;
qereset(sc);
  568 }
  570 /*
  571  * Interrupt dispatch.
  572  */
  573 int
qeintr(arg)
  575         void *arg;
  576 {
  577         struct qe_softc *sc = (struct qe_softc *)arg;
bus_space_tag_t t = sc->sc_bustag;
u_int32_t qecstat, qestat;
  580         int r = 0;
  582         /* Read QEC status and channel status */
qecstat = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT);
  584 #ifdef QEDEBUG
  585         if (sc->sc_debug) {
printf("qe%d: intr: qecstat=%x\n", sc->sc_channel, qecstat);
  587         }
  588 #endif
  590         /* Filter out status for this channel */
qecstat = qecstat >> (4 * sc->sc_channel);
  592         if ((qecstat & 0xf) == 0)
  593                 return (r);
qestat = bus_space_read_4(t, sc->sc_cr, QE_CRI_STAT);
  597 #ifdef QEDEBUG
  598         if (sc->sc_debug) {
  599                 int i;
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t mr = sc->sc_mr;
printf("qe%d: intr: qestat=%b\n", sc->sc_channel,
qestat, QE_CR_STAT_BITS);
printf("MACE registers:\n");
  607                 for (i = 0 ; i < 32; i++) {
printf("  m[%d]=%x,", i, bus_space_read_1(t, mr, i));
  609                         if (((i+1) & 7) == 0)
printf("\n");
  611                 }
  612         }
  613 #endif
  615         if (qestat & QE_CR_STAT_ALLERRORS) {
  616 #ifdef QEDEBUG
  617                 if (sc->sc_debug)
printf("qe%d: eint: qestat=%b\n", sc->sc_channel,
qestat, QE_CR_STAT_BITS);
  620 #endif
r |= qe_eint(sc, qestat);
  622                 if (r == -1)
  623                         return (1);
  624         }
  626         if (qestat & QE_CR_STAT_TXIRQ)
r |= qe_tint(sc);
  629         if (qestat & QE_CR_STAT_RXIRQ)
r |= qe_rint(sc);
  632         return (1);
  633 }
  635 /*
  636  * Transmit interrupt.
  637  */
  638 int
qe_tint(sc)
  640         struct qe_softc *sc;
  641 {
  642         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
  643         unsigned int bix, txflags;
bix = sc->sc_rb.rb_tdtail;
  647         for (;;) {
  648                 if (sc->sc_rb.rb_td_nbusy <= 0)
  649                         break;
txflags = sc->sc_rb.rb_txd[bix].xd_flags;
  653                 if (txflags & QEC_XD_OWN)
  654                         break;
ifp->if_flags &= ~IFF_OACTIVE;
ifp->if_opackets++;
  659                 if (++bix == QEC_XD_RING_MAXSIZE)
bix = 0;
  662                 --sc->sc_rb.rb_td_nbusy;
  663         }
  665         if (sc->sc_rb.rb_td_nbusy == 0)
ifp->if_timer = 0;
  668         if (sc->sc_rb.rb_tdtail != bix) {
sc->sc_rb.rb_tdtail = bix;
  670                 if (ifp->if_flags & IFF_OACTIVE) {
ifp->if_flags &= ~IFF_OACTIVE;
qestart(ifp);
  673                 }
  674         }
  676         return (1);
  677 }
  679 /*
  680  * Receive interrupt.
  681  */
  682 int
qe_rint(sc)
  684         struct qe_softc *sc;
  685 {
  686         struct qec_xd *xd = sc->sc_rb.rb_rxd;
  687         unsigned int bix, len;
  688         unsigned int nrbuf = sc->sc_rb.rb_nrbuf;
  689 #ifdef QEDEBUG
  690         int npackets = 0;
  691 #endif
bix = sc->sc_rb.rb_rdtail;
  695         /*
  696          * Process all buffers with valid data.
  697          */
  698         for (;;) {
len = xd[bix].xd_flags;
  700                 if (len & QEC_XD_OWN)
  701                         break;
  703 #ifdef QEDEBUG
npackets++;
  705 #endif
len &= QEC_XD_LENGTH;
len -= 4;
qe_read(sc, bix, len);
  711                 /* ... */
xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags =
QEC_XD_OWN | (QE_PKT_BUF_SZ & QEC_XD_LENGTH);
  715                 if (++bix == QEC_XD_RING_MAXSIZE)
bix = 0;
  717         }
  718 #ifdef QEDEBUG
  719         if (npackets == 0 && sc->sc_debug)
printf("%s: rint: no packets; rb index %d; status 0x%x\n",
sc->sc_dev.dv_xname, bix, len);
  722 #endif
sc->sc_rb.rb_rdtail = bix;
  726         return (1);
  727 }
  729 /*
  730  * Error interrupt.
  731  */
  732 int
qe_eint(sc, why)
  734         struct qe_softc *sc;
u_int32_t why;
  736 {
  737         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
  738         int r = 0, rst = 0;
  740         if (why & QE_CR_STAT_EDEFER) {
printf("%s: excessive tx defers.\n", sc->sc_dev.dv_xname);
r |= 1;
ifp->if_oerrors++;
  744         }
  746         if (why & QE_CR_STAT_CLOSS) {
ifp->if_oerrors++;
r |= 1;
  749         }
  751         if (why & QE_CR_STAT_ERETRIES) {
printf("%s: excessive tx retries\n", sc->sc_dev.dv_xname);
ifp->if_oerrors++;
r |= 1;
rst = 1;
  756         }
  759         if (why & QE_CR_STAT_LCOLL) {
printf("%s: late tx transmission\n", sc->sc_dev.dv_xname);
ifp->if_oerrors++;
r |= 1;
rst = 1;
  764         }
  766         if (why & QE_CR_STAT_FUFLOW) {
printf("%s: tx fifo underflow\n", sc->sc_dev.dv_xname);
ifp->if_oerrors++;
r |= 1;
rst = 1;
  771         }
  773         if (why & QE_CR_STAT_JERROR) {
printf("%s: jabber seen\n", sc->sc_dev.dv_xname);
r |= 1;
  776         }
  778         if (why & QE_CR_STAT_BERROR) {
printf("%s: babble seen\n", sc->sc_dev.dv_xname);
r |= 1;
  781         }
  783         if (why & QE_CR_STAT_TCCOFLOW) {
ifp->if_collisions += 256;
ifp->if_oerrors += 256;
r |= 1;
  787         }
  789         if (why & QE_CR_STAT_TXDERROR) {
printf("%s: tx descriptor is bad\n", sc->sc_dev.dv_xname);
rst = 1;
r |= 1;
  793         }
  795         if (why & QE_CR_STAT_TXLERR) {
printf("%s: tx late error\n", sc->sc_dev.dv_xname);
ifp->if_oerrors++;
rst = 1;
r |= 1;
  800         }
  802         if (why & QE_CR_STAT_TXPERR) {
printf("%s: tx dma parity error\n", sc->sc_dev.dv_xname);
ifp->if_oerrors++;
rst = 1;
r |= 1;
  807         }
  809         if (why & QE_CR_STAT_TXSERR) {
printf("%s: tx dma sbus error ack\n", sc->sc_dev.dv_xname);
ifp->if_oerrors++;
rst = 1;
r |= 1;
  814         }
  816         if (why & QE_CR_STAT_RCCOFLOW) {
ifp->if_collisions += 256;
ifp->if_ierrors += 256;
r |= 1;
  820         }
  822         if (why & QE_CR_STAT_RUOFLOW) {
ifp->if_ierrors += 256;
r |= 1;
  825         }
  827         if (why & QE_CR_STAT_MCOFLOW) {
ifp->if_ierrors += 256;
r |= 1;
  830         }
  832         if (why & QE_CR_STAT_RXFOFLOW) {
printf("%s: rx fifo overflow\n", sc->sc_dev.dv_xname);
ifp->if_ierrors++;
r |= 1;
  836         }
  838         if (why & QE_CR_STAT_RLCOLL) {
printf("%s: rx late collision\n", sc->sc_dev.dv_xname);
ifp->if_ierrors++;
ifp->if_collisions++;
r |= 1;
  843         }
  845         if (why & QE_CR_STAT_FCOFLOW) {
ifp->if_ierrors += 256;
r |= 1;
  848         }
  850         if (why & QE_CR_STAT_CECOFLOW) {
ifp->if_ierrors += 256;
r |= 1;
  853         }
  855         if (why & QE_CR_STAT_RXDROP) {
printf("%s: rx packet dropped\n", sc->sc_dev.dv_xname);
ifp->if_ierrors++;
r |= 1;
  859         }
  861         if (why & QE_CR_STAT_RXSMALL) {
printf("%s: rx buffer too small\n", sc->sc_dev.dv_xname);
ifp->if_ierrors++;
r |= 1;
rst = 1;
  866         }
  868         if (why & QE_CR_STAT_RXLERR) {
printf("%s: rx late error\n", sc->sc_dev.dv_xname);
ifp->if_ierrors++;
r |= 1;
rst = 1;
  873         }
  875         if (why & QE_CR_STAT_RXPERR) {
printf("%s: rx dma parity error\n", sc->sc_dev.dv_xname);
ifp->if_ierrors++;
r |= 1;
rst = 1;
  880         }
  882         if (why & QE_CR_STAT_RXSERR) {
printf("%s: rx dma sbus error ack\n", sc->sc_dev.dv_xname);
ifp->if_ierrors++;
r |= 1;
rst = 1;
  887         }
  889         if (r == 0)
printf("%s: unexpected interrupt error: %08x\n",
sc->sc_dev.dv_xname, why);
  893         if (rst) {
printf("%s: resetting...\n", sc->sc_dev.dv_xname);
qereset(sc);
  896                 return (-1);
  897         }
  899         return (r);
  900 }
  902 int
qeioctl(ifp, cmd, data)
  904         struct ifnet *ifp;
u_long cmd;
caddr_t data;
  907 {
  908         struct qe_softc *sc = ifp->if_softc;
  909         struct ifaddr *ifa = (struct ifaddr *)data;
  910         struct ifreq *ifr = (struct ifreq *)data;
  911         int s, error = 0;
s = splnet();
  915         if ((error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data)) > 0) {
splx(s);
  917                 return (error);
  918         }
  920         switch (cmd) {
  921         case SIOCSIFADDR:
ifp->if_flags |= IFF_UP;
  923                 switch (ifa->ifa_addr->sa_family) {
  924 #ifdef INET
  925                 case AF_INET:
qeinit(sc);
arp_ifinit(&sc->sc_arpcom, ifa);
  928                         break;
  929 #endif /* INET */
  930                 default:
qeinit(sc);
  932                         break;
  933                 }
  934                 break;
  936         case SIOCSIFFLAGS:
  937                 if ((ifp->if_flags & IFF_UP) == 0 &&
  938                     (ifp->if_flags & IFF_RUNNING) != 0) {
  939                         /*
  940                          * If interface is marked down and it is running, then
  941                          * stop it.
  942                          */
qestop(sc);
ifp->if_flags &= ~IFF_RUNNING;
  945                 } else if ((ifp->if_flags & IFF_UP) != 0 &&
  946                            (ifp->if_flags & IFF_RUNNING) == 0) {
  947                         /*
  948                          * If interface is marked up and it is stopped, then
  949                          * start it.
  950                          */
qeinit(sc);
  952                 } else {
  953                         /*
  954                          * Reset the interface to pick up changes in any other
  955                          * flags that affect hardware registers.
  956                          */
qestop(sc);
qeinit(sc);
  959                 }
  960 #ifdef QEDEBUG
sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0;
  962 #endif
  963                 break;
  965         case SIOCADDMULTI:
  966         case SIOCDELMULTI:
error = (cmd == SIOCADDMULTI) ?
ether_addmulti(ifr, &sc->sc_arpcom):
ether_delmulti(ifr, &sc->sc_arpcom);
  971                 if (error == ENETRESET) {
  972                         /*
  973                          * Multicast list has changed; set the hardware filter
  974                          * accordingly.
  975                          */
  976                         if (ifp->if_flags & IFF_RUNNING)
qe_mcreset(sc);
error = 0;
  979                 }
  980                 break;
  982         case SIOCGIFMEDIA:
  983         case SIOCSIFMEDIA:
error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, cmd);
  985                 break;
  987         default:
error = EINVAL;
  989                 break;
  990         }
splx(s);
  993         return (error);
  994 }
  997 void
qeinit(sc)
  999         struct qe_softc *sc;
 1000 {
 1001         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t cr = sc->sc_cr;
bus_space_handle_t mr = sc->sc_mr;
 1005         struct qec_softc *qec = sc->sc_qec;
u_int32_t qecaddr;
u_int8_t *ea;
 1008         int s;
s = splnet();
qestop(sc);
 1014         /*
 1015          * Allocate descriptor ring and buffers
 1016          */
qec_meminit(&sc->sc_rb, QE_PKT_BUF_SZ);
 1019         /* Channel registers: */
bus_space_write_4(t, cr, QE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma);
bus_space_write_4(t, cr, QE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma);
bus_space_write_4(t, cr, QE_CRI_RIMASK, 0);
bus_space_write_4(t, cr, QE_CRI_TIMASK, 0);
bus_space_write_4(t, cr, QE_CRI_QMASK, 0);
bus_space_write_4(t, cr, QE_CRI_MMASK, QE_CR_MMASK_RXCOLL);
bus_space_write_4(t, cr, QE_CRI_CCNT, 0);
bus_space_write_4(t, cr, QE_CRI_PIPG, 0);
qecaddr = sc->sc_channel * qec->sc_msize;
bus_space_write_4(t, cr, QE_CRI_RXWBUF, qecaddr);
bus_space_write_4(t, cr, QE_CRI_RXRBUF, qecaddr);
bus_space_write_4(t, cr, QE_CRI_TXWBUF, qecaddr + qec->sc_rsize);
bus_space_write_4(t, cr, QE_CRI_TXRBUF, qecaddr + qec->sc_rsize);
 1036         /*
 1037          * When switching from mace<->qec always guarantee an sbus
 1038          * turnaround (if last op was read, perform a dummy write, and
 1039          * vice versa).
 1040          */
bus_space_read_4(t, cr, QE_CRI_QMASK);
 1043         /* MACE registers: */
bus_space_write_1(t, mr, QE_MRI_PHYCC, QE_MR_PHYCC_ASEL);
bus_space_write_1(t, mr, QE_MRI_XMTFC, QE_MR_XMTFC_APADXMT);
bus_space_write_1(t, mr, QE_MRI_RCVFC, 0);
 1048         /*
 1049          * Mask MACE's receive interrupt, since we're being notified
 1050          * by the QEC after DMA completes.
 1051          */
bus_space_write_1(t, mr, QE_MRI_IMR,
QE_MR_IMR_CERRM | QE_MR_IMR_RCVINTM);
bus_space_write_1(t, mr, QE_MRI_BIUCC,
QE_MR_BIUCC_BSWAP | QE_MR_BIUCC_64TS);
bus_space_write_1(t, mr, QE_MRI_FIFOFC,
QE_MR_FIFOCC_TXF16 | QE_MR_FIFOCC_RXF32 |
QE_MR_FIFOCC_RFWU | QE_MR_FIFOCC_TFWU);
bus_space_write_1(t, mr, QE_MRI_PLSCC, QE_MR_PLSCC_TP);
 1064         /*
 1065          * Station address
 1066          */
ea = sc->sc_arpcom.ac_enaddr;
bus_space_write_1(t, mr, QE_MRI_IAC,
QE_MR_IAC_ADDRCHG | QE_MR_IAC_PHYADDR);
bus_space_write_multi_1(t, mr, QE_MRI_PADR, ea, 6);
 1072         /* Apply media settings */
qe_ifmedia_upd(ifp);
 1075         /*
 1076          * Clear Logical address filter
 1077          */
bus_space_write_1(t, mr, QE_MRI_IAC,
QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR);
bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0, 8);
bus_space_write_1(t, mr, QE_MRI_IAC, 0);
 1083         /* Clear missed packet count (register cleared on read) */
 1084         (void)bus_space_read_1(t, mr, QE_MRI_MPC);
 1086 #if 0
 1087         /* test register: */
bus_space_write_1(t, mr, QE_MRI_UTR, 0);
 1089 #endif
 1091         /* Reset multicast filter */
qe_mcreset(sc);
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
splx(s);
 1097 }
 1099 /*
 1100  * Reset multicast filter.
 1101  */
 1102 void
qe_mcreset(sc)
 1104         struct qe_softc *sc;
 1105 {
 1106         struct arpcom *ac = &sc->sc_arpcom;
 1107         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
bus_space_tag_t t = sc->sc_bustag;
bus_space_handle_t mr = sc->sc_mr;
 1110         struct ether_multi *enm;
 1111         struct ether_multistep step;
u_int32_t crc;
u_int16_t hash[4];
u_int8_t octet, maccc, *ladrp = (u_int8_t *)&hash[0];
 1115         int i, j;
 1117         /* We also enable transmitter & receiver here */
maccc = QE_MR_MACCC_ENXMT | QE_MR_MACCC_ENRCV;
 1120         if (ifp->if_flags & IFF_PROMISC) {
maccc |= QE_MR_MACCC_PROM;
bus_space_write_1(t, mr, QE_MRI_MACCC, maccc);
 1123                 return;
 1124         }
 1126         if (ifp->if_flags & IFF_ALLMULTI) {
bus_space_write_1(t, mr, QE_MRI_IAC,
QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR);
bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8);
bus_space_write_1(t, mr, QE_MRI_IAC, 0);
bus_space_write_1(t, mr, QE_MRI_MACCC, maccc);
 1132                 return;
 1133         }
hash[3] = hash[2] = hash[1] = hash[0] = 0;
ETHER_FIRST_MULTI(step, ac, enm);
 1138         while (enm != NULL) {
 1139                 if (bcmp(enm->enm_addrlo, enm->enm_addrhi,
ETHER_ADDR_LEN) != 0) {
 1141                         /*
 1142                          * We must listen to a range of multicast
 1143                          * addresses. For now, just accept all
 1144                          * multicasts, rather than trying to set only
 1145                          * those filter bits needed to match the range.
 1146                          * (At this time, the only use of address
 1147                          * ranges is for IP multicast routing, for
 1148                          * which the range is big enough to require
 1149                          * all bits set.)
 1150                          */
bus_space_write_1(t, mr, QE_MRI_IAC,
QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR);
bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8);
bus_space_write_1(t, mr, QE_MRI_IAC, 0);
ifp->if_flags |= IFF_ALLMULTI;
 1156                         break;
 1157                 }
crc = 0xffffffff;
 1161                 for (i = 0; i < ETHER_ADDR_LEN; i++) {
octet = enm->enm_addrlo[i];
 1164                         for (j = 0; j < 8; j++) {
 1165                                 if ((crc & 1) ^ (octet & 1)) {
crc >>= 1;
crc ^= MC_POLY_LE;
 1168                                 }
 1169                                 else
crc >>= 1;
octet >>= 1;
 1172                         }
 1173                 }
crc >>= 26;
hash[crc >> 4] |= 1 << (crc & 0xf);
ETHER_NEXT_MULTI(step, enm);
 1178         }
bus_space_write_1(t, mr, QE_MRI_IAC,
QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR);
bus_space_write_multi_1(t, mr, QE_MRI_LADRF, ladrp, 8);
bus_space_write_1(t, mr, QE_MRI_IAC, 0);
bus_space_write_1(t, mr, QE_MRI_MACCC, maccc);
 1185 }
 1187 /*
 1188  * Get current media settings.
 1189  */
 1190 void
qe_ifmedia_sts(ifp, ifmr)
 1192         struct ifnet *ifp;
 1193         struct ifmediareq *ifmr;
 1194 {
 1195         struct qe_softc *sc = ifp->if_softc;
u_int8_t phycc;
ifmr->ifm_active = IFM_ETHER | IFM_10_T;
phycc = bus_space_read_1(sc->sc_bustag, sc->sc_mr, QE_MRI_PHYCC);
 1200         if ((phycc & QE_MR_PHYCC_DLNKTST) == 0) {
ifmr->ifm_status |= IFM_AVALID;
 1202                 if (phycc & QE_MR_PHYCC_LNKFL)
ifmr->ifm_status &= ~IFM_ACTIVE;
 1204                 else
ifmr->ifm_status |= IFM_ACTIVE;
 1206         }
 1207 }
 1209 /*
 1210  * Set media options.
 1211  */
 1212 int
qe_ifmedia_upd(ifp)
 1214         struct ifnet *ifp;
 1215 {
 1216         struct qe_softc *sc = ifp->if_softc;
 1217         int media = sc->sc_ifmedia.ifm_media;
 1219         if (IFM_TYPE(media) != IFM_ETHER)
 1220                 return (EINVAL);
 1222         if (IFM_SUBTYPE(media) != IFM_10_T)
 1223                 return (EINVAL);
 1225         return (0);
 1226 }