sbr_offset        126 dev/sbus/apio.c 	    sa->sa_reg[0].sbr_offset, sa->sa_reg[0].sbr_size,
sbr_offset        133 dev/sbus/apio.c 	    sa->sa_reg[1].sbr_offset, sa->sa_reg[1].sbr_size,
sbr_offset        140 dev/sbus/apio.c 	    sa->sa_reg[2].sbr_offset, sa->sa_reg[2].sbr_size,
sbr_offset        135 dev/sbus/asio.c 	    sa->sa_reg[0].sbr_offset, sa->sa_reg[0].sbr_size,
sbr_offset        143 dev/sbus/asio.c 		    sa->sa_reg[i + 1].sbr_offset, sa->sa_reg[i + 1].sbr_size,
sbr_offset        241 dev/sbus/be.c  	    (bus_addr_t)sa->sa_reg[0].sbr_offset,
sbr_offset        248 dev/sbus/be.c  	    (bus_addr_t)sa->sa_reg[1].sbr_offset,
sbr_offset        255 dev/sbus/be.c  	    (bus_addr_t)sa->sa_reg[2].sbr_offset,
sbr_offset        175 dev/sbus/bwtwo.c 	    sa->sa_reg[0].sbr_offset + BWTWO_CTRL_OFFSET,
sbr_offset        182 dev/sbus/bwtwo.c 	    sa->sa_reg[0].sbr_offset + BWTWO_VID_OFFSET,
sbr_offset        137 dev/sbus/cgsix.c 	    sa->sa_reg[0].sbr_offset + CGSIX_BT_OFFSET,
sbr_offset        144 dev/sbus/cgsix.c 	    sa->sa_reg[0].sbr_offset + CGSIX_FHC_OFFSET,
sbr_offset        151 dev/sbus/cgsix.c 	    sa->sa_reg[0].sbr_offset + CGSIX_THC_OFFSET,
sbr_offset        158 dev/sbus/cgsix.c 	    sa->sa_reg[0].sbr_offset + CGSIX_VID_OFFSET,
sbr_offset        166 dev/sbus/cgsix.c 	    sa->sa_reg[0].sbr_offset + CGSIX_TEC_OFFSET,
sbr_offset        173 dev/sbus/cgsix.c 	    sa->sa_reg[0].sbr_offset + CGSIX_FBC_OFFSET,
sbr_offset        229 dev/sbus/cgthree.c 	    sa->sa_reg[0].sbr_offset + CGTHREE_CTRL_OFFSET,
sbr_offset        236 dev/sbus/cgthree.c 	    sa->sa_reg[0].sbr_offset + CGTHREE_VID_OFFSET,
sbr_offset        242 dev/sbus/cs4231.c 	    (bus_addr_t)sa->sa_reg[0].sbr_offset,
sbr_offset        223 dev/sbus/esp_sbus.c 		    sa->sa_reg[0].sbr_offset, sa->sa_reg[0].sbr_size,
sbr_offset        265 dev/sbus/esp_sbus.c 		    sa->sa_reg[1].sbr_offset, sa->sa_reg[1].sbr_size,
sbr_offset        128 dev/sbus/if_gem_sbus.c 			 (bus_addr_t)sa->sa_reg[0].sbr_offset,
sbr_offset        135 dev/sbus/if_gem_sbus.c 			 (bus_addr_t)sa->sa_reg[1].sbr_offset,
sbr_offset        130 dev/sbus/if_hme_sbus.c 	    (bus_addr_t)sa->sa_reg[0].sbr_offset,
sbr_offset        136 dev/sbus/if_hme_sbus.c 	    (bus_addr_t)sa->sa_reg[1].sbr_offset,
sbr_offset        142 dev/sbus/if_hme_sbus.c 	    (bus_addr_t)sa->sa_reg[2].sbr_offset,
sbr_offset        148 dev/sbus/if_hme_sbus.c 	    (bus_addr_t)sa->sa_reg[3].sbr_offset,
sbr_offset        154 dev/sbus/if_hme_sbus.c 	    (bus_addr_t)sa->sa_reg[4].sbr_offset,
sbr_offset        160 dev/sbus/if_le.c 	    sa->sa_reg[0].sbr_offset, sa->sa_reg[0].sbr_size,
sbr_offset        325 dev/sbus/magma.c 	    sa->sa_reg[0].sbr_offset, sa->sa_reg[0].sbr_size,
sbr_offset        181 dev/sbus/mgx.c 	    sa->sa_reg[MGX_REG_CRTC].sbr_offset, PAGE_SIZE,
sbr_offset        204 dev/sbus/mgx.c 	    sa->sa_reg[MGX_REG_VRAM8].sbr_offset);
sbr_offset        206 dev/sbus/mgx.c 	    sa->sa_reg[MGX_REG_VRAM8].sbr_offset,
sbr_offset        213 dev/sbus/qe.c  	    (bus_addr_t)sa->sa_reg[0].sbr_offset,
sbr_offset        220 dev/sbus/qe.c  	    (bus_addr_t)sa->sa_reg[1].sbr_offset,
sbr_offset        140 dev/sbus/qec.c 	    sa->sa_reg[0].sbr_offset, sa->sa_reg[0].sbr_size,
sbr_offset        152 dev/sbus/qec.c 	    sa->sa_reg[1].sbr_offset, sa->sa_reg[1].sbr_size, 0, 0, &bh) != 0) {
sbr_offset         52 dev/sbus/sbusvar.h 	u_int32_t	sbr_offset;
sbr_offset         83 dev/sbus/sbusvar.h #define sa_offset	sa_reg[0].sbr_offset
sbr_offset        181 dev/sbus/spif.c 	    sa->sa_reg[0].sbr_offset, sa->sa_reg[0].sbr_size,
sbr_offset        130 dev/sbus/uperf_sbus.c 	    sa->sa_reg[0].sbr_offset, sa->sa_reg[0].sbr_size, 0, 0,
sbr_offset        278 dev/sbus/vigra.c 	    sa->sa_reg[VIGRA_REG_CSR].sbr_offset,
sbr_offset        286 dev/sbus/vigra.c 	    sa->sa_reg[VIGRA_REG_RAMDAC].sbr_offset,
sbr_offset        299 dev/sbus/vigra.c 	    sa->sa_reg[VIGRA_REG_VRAM].sbr_offset,
sbr_offset        308 dev/sbus/vigra.c 	    sa->sa_reg[VIGRA_REG_VRAM].sbr_offset);
sbr_offset        101 dev/sbus/xbox.c 	    sa->sa_reg[0].sbr_offset, sa->sa_reg[0].sbr_size, 0, 0,