sa_reg 125 dev/sbus/apio.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot,
sa_reg 126 dev/sbus/apio.c sa->sa_reg[0].sbr_offset, sa->sa_reg[0].sbr_size,
sa_reg 132 dev/sbus/apio.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[1].sbr_slot,
sa_reg 133 dev/sbus/apio.c sa->sa_reg[1].sbr_offset, sa->sa_reg[1].sbr_size,
sa_reg 139 dev/sbus/apio.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[2].sbr_slot,
sa_reg 140 dev/sbus/apio.c sa->sa_reg[2].sbr_offset, sa->sa_reg[2].sbr_size,
sa_reg 134 dev/sbus/asio.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot,
sa_reg 135 dev/sbus/asio.c sa->sa_reg[0].sbr_offset, sa->sa_reg[0].sbr_size,
sa_reg 142 dev/sbus/asio.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[i + 1].sbr_slot,
sa_reg 143 dev/sbus/asio.c sa->sa_reg[i + 1].sbr_offset, sa->sa_reg[i + 1].sbr_size,
sa_reg 240 dev/sbus/be.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot,
sa_reg 241 dev/sbus/be.c (bus_addr_t)sa->sa_reg[0].sbr_offset,
sa_reg 242 dev/sbus/be.c (bus_size_t)sa->sa_reg[0].sbr_size, 0, 0, &sc->sc_cr) != 0) {
sa_reg 247 dev/sbus/be.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[1].sbr_slot,
sa_reg 248 dev/sbus/be.c (bus_addr_t)sa->sa_reg[1].sbr_offset,
sa_reg 249 dev/sbus/be.c (bus_size_t)sa->sa_reg[1].sbr_size, 0, 0, &sc->sc_br) != 0) {
sa_reg 254 dev/sbus/be.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[2].sbr_slot,
sa_reg 255 dev/sbus/be.c (bus_addr_t)sa->sa_reg[2].sbr_offset,
sa_reg 256 dev/sbus/be.c (bus_size_t)sa->sa_reg[2].sbr_size, 0, 0, &sc->sc_tr) != 0) {
sa_reg 174 dev/sbus/bwtwo.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot,
sa_reg 175 dev/sbus/bwtwo.c sa->sa_reg[0].sbr_offset + BWTWO_CTRL_OFFSET,
sa_reg 181 dev/sbus/bwtwo.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot,
sa_reg 182 dev/sbus/bwtwo.c sa->sa_reg[0].sbr_offset + BWTWO_VID_OFFSET,
sa_reg 136 dev/sbus/cgsix.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot,
sa_reg 137 dev/sbus/cgsix.c sa->sa_reg[0].sbr_offset + CGSIX_BT_OFFSET,
sa_reg 143 dev/sbus/cgsix.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot,
sa_reg 144 dev/sbus/cgsix.c sa->sa_reg[0].sbr_offset + CGSIX_FHC_OFFSET,
sa_reg 150 dev/sbus/cgsix.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot,
sa_reg 151 dev/sbus/cgsix.c sa->sa_reg[0].sbr_offset + CGSIX_THC_OFFSET,
sa_reg 157 dev/sbus/cgsix.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot,
sa_reg 158 dev/sbus/cgsix.c sa->sa_reg[0].sbr_offset + CGSIX_VID_OFFSET,
sa_reg 165 dev/sbus/cgsix.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot,
sa_reg 166 dev/sbus/cgsix.c sa->sa_reg[0].sbr_offset + CGSIX_TEC_OFFSET,
sa_reg 172 dev/sbus/cgsix.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot,
sa_reg 173 dev/sbus/cgsix.c sa->sa_reg[0].sbr_offset + CGSIX_FBC_OFFSET,
sa_reg 228 dev/sbus/cgthree.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot,
sa_reg 229 dev/sbus/cgthree.c sa->sa_reg[0].sbr_offset + CGTHREE_CTRL_OFFSET,
sa_reg 235 dev/sbus/cgthree.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot,
sa_reg 236 dev/sbus/cgthree.c sa->sa_reg[0].sbr_offset + CGTHREE_VID_OFFSET,
sa_reg 241 dev/sbus/cs4231.c sa->sa_reg[0].sbr_slot,
sa_reg 242 dev/sbus/cs4231.c (bus_addr_t)sa->sa_reg[0].sbr_offset,
sa_reg 243 dev/sbus/cs4231.c (bus_size_t)sa->sa_reg[0].sbr_size,
sa_reg 222 dev/sbus/esp_sbus.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot,
sa_reg 223 dev/sbus/esp_sbus.c sa->sa_reg[0].sbr_offset, sa->sa_reg[0].sbr_size,
sa_reg 264 dev/sbus/esp_sbus.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[1].sbr_slot,
sa_reg 265 dev/sbus/esp_sbus.c sa->sa_reg[1].sbr_offset, sa->sa_reg[1].sbr_size,
sa_reg 127 dev/sbus/if_gem_sbus.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot,
sa_reg 128 dev/sbus/if_gem_sbus.c (bus_addr_t)sa->sa_reg[0].sbr_offset,
sa_reg 129 dev/sbus/if_gem_sbus.c (bus_size_t)sa->sa_reg[0].sbr_size, 0, 0,
sa_reg 134 dev/sbus/if_gem_sbus.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot,
sa_reg 135 dev/sbus/if_gem_sbus.c (bus_addr_t)sa->sa_reg[1].sbr_offset,
sa_reg 136 dev/sbus/if_gem_sbus.c (bus_size_t)sa->sa_reg[1].sbr_size, 0, 0,
sa_reg 129 dev/sbus/if_hme_sbus.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot,
sa_reg 130 dev/sbus/if_hme_sbus.c (bus_addr_t)sa->sa_reg[0].sbr_offset,
sa_reg 131 dev/sbus/if_hme_sbus.c (bus_size_t)sa->sa_reg[0].sbr_size, 0, 0, &sc->sc_seb) != 0) {
sa_reg 135 dev/sbus/if_hme_sbus.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[1].sbr_slot,
sa_reg 136 dev/sbus/if_hme_sbus.c (bus_addr_t)sa->sa_reg[1].sbr_offset,
sa_reg 137 dev/sbus/if_hme_sbus.c (bus_size_t)sa->sa_reg[1].sbr_size, 0, 0, &sc->sc_etx) != 0) {
sa_reg 141 dev/sbus/if_hme_sbus.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[2].sbr_slot,
sa_reg 142 dev/sbus/if_hme_sbus.c (bus_addr_t)sa->sa_reg[2].sbr_offset,
sa_reg 143 dev/sbus/if_hme_sbus.c (bus_size_t)sa->sa_reg[2].sbr_size, 0, 0, &sc->sc_erx) != 0) {
sa_reg 147 dev/sbus/if_hme_sbus.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[3].sbr_slot,
sa_reg 148 dev/sbus/if_hme_sbus.c (bus_addr_t)sa->sa_reg[3].sbr_offset,
sa_reg 149 dev/sbus/if_hme_sbus.c (bus_size_t)sa->sa_reg[3].sbr_size, 0, 0, &sc->sc_mac) != 0) {
sa_reg 153 dev/sbus/if_hme_sbus.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[4].sbr_slot,
sa_reg 154 dev/sbus/if_hme_sbus.c (bus_addr_t)sa->sa_reg[4].sbr_offset,
sa_reg 155 dev/sbus/if_hme_sbus.c (bus_size_t)sa->sa_reg[4].sbr_size, 0, 0, &sc->sc_mif) != 0) {
sa_reg 159 dev/sbus/if_le.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot,
sa_reg 160 dev/sbus/if_le.c sa->sa_reg[0].sbr_offset, sa->sa_reg[0].sbr_size,
sa_reg 324 dev/sbus/magma.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot,
sa_reg 325 dev/sbus/magma.c sa->sa_reg[0].sbr_offset, sa->sa_reg[0].sbr_size,
sa_reg 341 dev/sbus/magma.c sa->sa_reg[0].sbr_size);
sa_reg 349 dev/sbus/magma.c sa->sa_reg[0].sbr_size);
sa_reg 180 dev/sbus/mgx.c if (sbus_bus_map(bt, sa->sa_reg[MGX_REG_CRTC].sbr_slot,
sa_reg 181 dev/sbus/mgx.c sa->sa_reg[MGX_REG_CRTC].sbr_offset, PAGE_SIZE,
sa_reg 203 dev/sbus/mgx.c sc->sc_paddr = sbus_bus_addr(bt, sa->sa_reg[MGX_REG_VRAM8].sbr_slot,
sa_reg 204 dev/sbus/mgx.c sa->sa_reg[MGX_REG_VRAM8].sbr_offset);
sa_reg 205 dev/sbus/mgx.c if (sbus_bus_map(bt, sa->sa_reg[MGX_REG_VRAM8].sbr_slot,
sa_reg 206 dev/sbus/mgx.c sa->sa_reg[MGX_REG_VRAM8].sbr_offset,
sa_reg 212 dev/sbus/qe.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot,
sa_reg 213 dev/sbus/qe.c (bus_addr_t)sa->sa_reg[0].sbr_offset,
sa_reg 214 dev/sbus/qe.c (bus_size_t)sa->sa_reg[0].sbr_size, 0, 0, &sc->sc_cr) != 0) {
sa_reg 219 dev/sbus/qe.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[1].sbr_slot,
sa_reg 220 dev/sbus/qe.c (bus_addr_t)sa->sa_reg[1].sbr_offset,
sa_reg 221 dev/sbus/qe.c (bus_size_t)sa->sa_reg[1].sbr_size, 0, 0, &sc->sc_mr) != 0) {
sa_reg 139 dev/sbus/qec.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot,
sa_reg 140 dev/sbus/qec.c sa->sa_reg[0].sbr_offset, sa->sa_reg[0].sbr_size,
sa_reg 151 dev/sbus/qec.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[1].sbr_slot,
sa_reg 152 dev/sbus/qec.c sa->sa_reg[1].sbr_offset, sa->sa_reg[1].sbr_size, 0, 0, &bh) != 0) {
sa_reg 157 dev/sbus/qec.c sc->sc_bufsiz = (bus_size_t)sa->sa_reg[1].sbr_size;
sa_reg 80 dev/sbus/sbusvar.h struct sbus_reg *sa_reg; /* SBus register space for device */
sa_reg 82 dev/sbus/sbusvar.h #define sa_slot sa_reg[0].sbr_slot
sa_reg 83 dev/sbus/sbusvar.h #define sa_offset sa_reg[0].sbr_offset
sa_reg 84 dev/sbus/sbusvar.h #define sa_size sa_reg[0].sbr_size
sa_reg 180 dev/sbus/spif.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot,
sa_reg 181 dev/sbus/spif.c sa->sa_reg[0].sbr_offset, sa->sa_reg[0].sbr_size,
sa_reg 277 dev/sbus/spif.c bus_space_unmap(sa->sa_bustag, sc->sc_regh, sa->sa_reg[0].sbr_size);
sa_reg 129 dev/sbus/uperf_sbus.c if (sbus_bus_map(sc->sc_bus_t, sa->sa_reg[0].sbr_slot,
sa_reg 130 dev/sbus/uperf_sbus.c sa->sa_reg[0].sbr_offset, sa->sa_reg[0].sbr_size, 0, 0,
sa_reg 277 dev/sbus/vigra.c if (sbus_bus_map(bt, sa->sa_reg[VIGRA_REG_CSR].sbr_slot,
sa_reg 278 dev/sbus/vigra.c sa->sa_reg[VIGRA_REG_CSR].sbr_offset,
sa_reg 279 dev/sbus/vigra.c sa->sa_reg[VIGRA_REG_CSR].sbr_size, BUS_SPACE_MAP_LINEAR, 0,
sa_reg 285 dev/sbus/vigra.c if (sbus_bus_map(bt, sa->sa_reg[VIGRA_REG_RAMDAC].sbr_slot,
sa_reg 286 dev/sbus/vigra.c sa->sa_reg[VIGRA_REG_RAMDAC].sbr_offset,
sa_reg 287 dev/sbus/vigra.c sa->sa_reg[VIGRA_REG_RAMDAC].sbr_size, BUS_SPACE_MAP_LINEAR, 0,
sa_reg 298 dev/sbus/vigra.c if (sbus_bus_map(bt, sa->sa_reg[VIGRA_REG_VRAM].sbr_slot,
sa_reg 299 dev/sbus/vigra.c sa->sa_reg[VIGRA_REG_VRAM].sbr_offset,
sa_reg 307 dev/sbus/vigra.c sc->sc_paddr = sbus_bus_addr(bt, sa->sa_reg[VIGRA_REG_VRAM].sbr_slot,
sa_reg 308 dev/sbus/vigra.c sa->sa_reg[VIGRA_REG_VRAM].sbr_offset);
sa_reg 100 dev/sbus/xbox.c if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot,
sa_reg 101 dev/sbus/xbox.c sa->sa_reg[0].sbr_offset, sa->sa_reg[0].sbr_size, 0, 0,
sa_reg 115 dev/sbus/xbox.c bus_space_unmap(sa->sa_bustag, write0, sa->sa_reg[0].sbr_size);