mr 50 arch/i386/i386/i686_mem.c #define mrwithin(mr, a) \
mr 51 arch/i386/i386/i686_mem.c (((a) >= (mr)->mr_base) && ((a) < ((mr)->mr_base + (mr)->mr_len)))
mr 555 dev/pci/if_myx.c struct myx_response *mr;
mr 601 dev/pci/if_myx.c mr = (struct myx_response *)sc->sc_cmddma.mxm_kva;
mr 602 dev/pci/if_myx.c mr->mr_result = 0xffffffff;
mr 610 dev/pci/if_myx.c result = betoh32(mr->mr_result);
mr 611 dev/pci/if_myx.c data = betoh32(mr->mr_data);
mr 6989 dev/pci/pciide.c u_int8_t rv, mr;
mr 6995 dev/pci/pciide.c mr = opti_read_config(chp, OPTI_REG_MISC) & ~OPTI_MISC_INDEX_MASK;
mr 6996 dev/pci/pciide.c mr &= ~(OPTI_MISC_DELAY_MASK |
mr 7060 dev/pci/pciide.c opti_write_config(chp, OPTI_REG_MISC, mr | rv);
mr 394 dev/pci/pcireg.h #define PCI_MAPREG_TYPE(mr) \
mr 395 dev/pci/pcireg.h ((mr) & PCI_MAPREG_TYPE_MASK)
mr 401 dev/pci/pcireg.h #define PCI_MAPREG_MEM_TYPE(mr) \
mr 402 dev/pci/pcireg.h ((mr) & PCI_MAPREG_MEM_TYPE_MASK)
mr 414 dev/pci/pcireg.h #define PCI_MAPREG_MEM_PREFETCHABLE(mr) \
mr 415 dev/pci/pcireg.h (((mr) & PCI_MAPREG_MEM_PREFETCHABLE_MASK) != 0)
mr 418 dev/pci/pcireg.h #define PCI_MAPREG_MEM_ADDR(mr) \
mr 419 dev/pci/pcireg.h ((mr) & PCI_MAPREG_MEM_ADDR_MASK)
mr 420 dev/pci/pcireg.h #define PCI_MAPREG_MEM_SIZE(mr) \
mr 421 dev/pci/pcireg.h (PCI_MAPREG_MEM_ADDR(mr) & -PCI_MAPREG_MEM_ADDR(mr))
mr 424 dev/pci/pcireg.h #define PCI_MAPREG_MEM64_ADDR(mr) \
mr 425 dev/pci/pcireg.h ((mr) & PCI_MAPREG_MEM64_ADDR_MASK)
mr 426 dev/pci/pcireg.h #define PCI_MAPREG_MEM64_SIZE(mr) \
mr 427 dev/pci/pcireg.h (PCI_MAPREG_MEM64_ADDR(mr) & -PCI_MAPREG_MEM64_ADDR(mr))
mr 430 dev/pci/pcireg.h #define PCI_MAPREG_IO_ADDR(mr) \
mr 431 dev/pci/pcireg.h ((mr) & PCI_MAPREG_IO_ADDR_MASK)
mr 432 dev/pci/pcireg.h #define PCI_MAPREG_IO_SIZE(mr) \
mr 433 dev/pci/pcireg.h (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr))
mr 456 dev/pci/pcireg.h #define PCI_ROM_ADDR(mr) \
mr 457 dev/pci/pcireg.h ((mr) & PCI_ROM_ADDR_MASK)
mr 458 dev/pci/pcireg.h #define PCI_ROM_SIZE(mr) \
mr 459 dev/pci/pcireg.h (PCI_ROM_ADDR(mr) & -PCI_ROM_ADDR(mr))
mr 520 dev/sbus/qe.c bus_space_handle_t mr = sc->sc_mr;
mr 525 dev/sbus/qe.c bus_space_write_1(t, mr, QE_MRI_BIUCC, QE_MR_BIUCC_SWRST);
mr 527 dev/sbus/qe.c if ((bus_space_read_1(t, mr, QE_MRI_BIUCC) &
mr 601 dev/sbus/qe.c bus_space_handle_t mr = sc->sc_mr;
mr 608 dev/sbus/qe.c printf(" m[%d]=%x,", i, bus_space_read_1(t, mr, i));
mr 1004 dev/sbus/qe.c bus_space_handle_t mr = sc->sc_mr;
mr 1044 dev/sbus/qe.c bus_space_write_1(t, mr, QE_MRI_PHYCC, QE_MR_PHYCC_ASEL);
mr 1045 dev/sbus/qe.c bus_space_write_1(t, mr, QE_MRI_XMTFC, QE_MR_XMTFC_APADXMT);
mr 1046 dev/sbus/qe.c bus_space_write_1(t, mr, QE_MRI_RCVFC, 0);
mr 1052 dev/sbus/qe.c bus_space_write_1(t, mr, QE_MRI_IMR,
mr 1055 dev/sbus/qe.c bus_space_write_1(t, mr, QE_MRI_BIUCC,
mr 1058 dev/sbus/qe.c bus_space_write_1(t, mr, QE_MRI_FIFOFC,
mr 1062 dev/sbus/qe.c bus_space_write_1(t, mr, QE_MRI_PLSCC, QE_MR_PLSCC_TP);
mr 1068 dev/sbus/qe.c bus_space_write_1(t, mr, QE_MRI_IAC,
mr 1070 dev/sbus/qe.c bus_space_write_multi_1(t, mr, QE_MRI_PADR, ea, 6);
mr 1078 dev/sbus/qe.c bus_space_write_1(t, mr, QE_MRI_IAC,
mr 1080 dev/sbus/qe.c bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0, 8);
mr 1081 dev/sbus/qe.c bus_space_write_1(t, mr, QE_MRI_IAC, 0);
mr 1084 dev/sbus/qe.c (void)bus_space_read_1(t, mr, QE_MRI_MPC);
mr 1088 dev/sbus/qe.c bus_space_write_1(t, mr, QE_MRI_UTR, 0);
mr 1109 dev/sbus/qe.c bus_space_handle_t mr = sc->sc_mr;
mr 1122 dev/sbus/qe.c bus_space_write_1(t, mr, QE_MRI_MACCC, maccc);
mr 1127 dev/sbus/qe.c bus_space_write_1(t, mr, QE_MRI_IAC,
mr 1129 dev/sbus/qe.c bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8);
mr 1130 dev/sbus/qe.c bus_space_write_1(t, mr, QE_MRI_IAC, 0);
mr 1131 dev/sbus/qe.c bus_space_write_1(t, mr, QE_MRI_MACCC, maccc);
mr 1151 dev/sbus/qe.c bus_space_write_1(t, mr, QE_MRI_IAC,
mr 1153 dev/sbus/qe.c bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8);
mr 1154 dev/sbus/qe.c bus_space_write_1(t, mr, QE_MRI_IAC, 0);
mr 1180 dev/sbus/qe.c bus_space_write_1(t, mr, QE_MRI_IAC,
mr 1182 dev/sbus/qe.c bus_space_write_multi_1(t, mr, QE_MRI_LADRF, ladrp, 8);
mr 1183 dev/sbus/qe.c bus_space_write_1(t, mr, QE_MRI_IAC, 0);
mr 1184 dev/sbus/qe.c bus_space_write_1(t, mr, QE_MRI_MACCC, maccc);