BITS 2057 dev/ic/atw.c (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & BITS(5, 0))
BITS 192 dev/ic/atwreg.h #define ATW_PAR_RAP_MASK BITS(17, 18) /* receive auto-polling in
BITS 195 dev/ic/atwreg.h #define ATW_PAR_CAL_MASK BITS(14, 15) /* cache alignment */
BITS 203 dev/ic/atwreg.h #define ATW_PAR_PBL_MASK BITS(8, 13) /* programmable burst length */
BITS 212 dev/ic/atwreg.h #define ATW_PAR_DSL_MASK BITS(2, 6) /* descriptor skip length */
BITS 217 dev/ic/atwreg.h #define ATW_FRCTL_VER_MASK BITS(29, 30) /* protocol version */
BITS 246 dev/ic/atwreg.h #define ATW_FRCTL_AID_MASK BITS(0, 15) /* STA Association ID */
BITS 320 dev/ic/atwreg.h #define ATW_NAR_TR_MASK BITS(14, 15) /* TX threshold */
BITS 328 dev/ic/atwreg.h #define ATW_NAR_OM_MASK BITS(10, 11) /* operating mode */
BITS 380 dev/ic/atwreg.h #define ATW_LPC_LPC_MASK BITS(0, 15) /* lost packet counter */
BITS 385 dev/ic/atwreg.h #define ATW_TEST1_DBGREAD_MASK BITS(30,28) /* "control of read data,
BITS 388 dev/ic/atwreg.h #define ATW_TEST1_TXWP_MASK BITS(27,25) /* select ATW_WTDP content? */
BITS 393 dev/ic/atwreg.h #define ATW_TEST1_RSVD0_MASK BITS(24,6) /* reserved */
BITS 394 dev/ic/atwreg.h #define ATW_TEST1_TESTMODE_MASK BITS(5,4)
BITS 404 dev/ic/atwreg.h #define ATW_TEST1_DUMP_MASK BITS(3,0) /* select dump signal
BITS 414 dev/ic/atwreg.h #define ATW_TEST0_BE_MASK BITS(31, 29) /* Bus error state */
BITS 415 dev/ic/atwreg.h #define ATW_TEST0_TS_MASK BITS(28, 26) /* Transmit process state */
BITS 442 dev/ic/atwreg.h #define ATW_TEST0_RS_MASK BITS(25, 23) /* Receive process state */
BITS 477 dev/ic/atwreg.h #define ATW_WCSR_BLN_MASK BITS(21, 23) /* lose link after BLN lost
BITS 499 dev/ic/atwreg.h #define ATW_GPTMR_GTV_MASK BITS(0, 15) /* set countdown in 204us ticks */
BITS 501 dev/ic/atwreg.h #define ATW_GPIO_EC1_MASK BITS(25, 24) /* GPIO1 event configuration */
BITS 502 dev/ic/atwreg.h #define ATW_GPIO_LAT_MASK BITS(21, 20) /* input latch */
BITS 503 dev/ic/atwreg.h #define ATW_GPIO_INTEN_MASK BITS(19, 18) /* interrupt enable */
BITS 504 dev/ic/atwreg.h #define ATW_GPIO_EN_MASK BITS(17, 12) /* output enable */
BITS 505 dev/ic/atwreg.h #define ATW_GPIO_O_MASK BITS(11, 6) /* output value */
BITS 506 dev/ic/atwreg.h #define ATW_GPIO_I_MASK BITS(5, 0) /* pin static input */
BITS 509 dev/ic/atwreg.h #define ATW_BBPCTL_RF3KADDR_MASK BITS(30, 24) /* Address for RF3000 */
BITS 514 dev/ic/atwreg.h #define ATW_BBPCTL_TYPE_MASK BITS(20, 18) /* BBP type */
BITS 521 dev/ic/atwreg.h #define ATW_BBPCTL_ADDR_MASK BITS(15, 8) /* BBP address */
BITS 522 dev/ic/atwreg.h #define ATW_BBPCTL_DATA_MASK BITS(7, 0) /* BBP data */
BITS 544 dev/ic/atwreg.h #define ATW_SYNCTL_RFTYPE_MASK BITS(24, 22) /* RF type */
BITS 545 dev/ic/atwreg.h #define ATW_SYNCTL_DATA_MASK BITS(21, 0) /* synthesizer setting */
BITS 547 dev/ic/atwreg.h #define ATW_PLCPHD_SIGNAL_MASK BITS(31, 24) /* signal field in PLCP header,
BITS 551 dev/ic/atwreg.h #define ATW_PLCPHD_SERVICE_MASK BITS(23, 16) /* service field in PLCP
BITS 558 dev/ic/atwreg.h #define ATW_MMIWADDR_LENLO_MASK BITS(31,24) /* tx: written 4th */
BITS 559 dev/ic/atwreg.h #define ATW_MMIWADDR_LENHI_MASK BITS(23,16) /* tx: written 3rd */
BITS 560 dev/ic/atwreg.h #define ATW_MMIWADDR_GAIN_MASK BITS(15,8) /* tx: written 2nd */
BITS 561 dev/ic/atwreg.h #define ATW_MMIWADDR_RATE_MASK BITS(7,0) /* tx: written 1st */
BITS 580 dev/ic/atwreg.h #define ATW_MMIRADDR1_RSVD_MASK BITS(31, 24)
BITS 581 dev/ic/atwreg.h #define ATW_MMIRADDR1_PWRLVL_MASK BITS(23, 16)
BITS 582 dev/ic/atwreg.h #define ATW_MMIRADDR1_RSSI_MASK BITS(15, 8)
BITS 583 dev/ic/atwreg.h #define ATW_MMIRADDR1_RXSTAT_MASK BITS(7, 0)
BITS 608 dev/ic/atwreg.h #define ATW_MMIRADDR2_ID_MASK BITS(31, 24) /* 1st element ID in WEP table
BITS 612 dev/ic/atwreg.h #define ATW_MMIRADDR2_RXPECNT_MASK BITS(23, 16)
BITS 617 dev/ic/atwreg.h #define ATW_MMIRADDR2_PRORLEN_MASK BITS(14, 0) /* Probe Response
BITS 622 dev/ic/atwreg.h #define ATW_TXBR_TBCNT_MASK BITS(16, 20) /* transmit burst count */
BITS 623 dev/ic/atwreg.h #define ATW_TXBR_ALCSET_MASK BITS(8, 15) /* TX power level set point */
BITS 624 dev/ic/atwreg.h #define ATW_TXBR_ALCREF_MASK BITS(0, 7) /* TX power level reference point */
BITS 628 dev/ic/atwreg.h #define ATW_ALCSTAT_MCNT_MASK BITS(16, 25) /* MPDU count, unsigned integer */
BITS 629 dev/ic/atwreg.h #define ATW_ALCSTAT_ERSUM_MASK BITS(0, 15) /* power error sum,
BITS 633 dev/ic/atwreg.h #define ATW_TOFS2_PWR1UP_MASK BITS(31, 28) /* delay of Tx/Rx from PE1,
BITS 637 dev/ic/atwreg.h #define ATW_TOFS2_PWR0PAPE_MASK BITS(27, 24) /* delay of PAPE going low
BITS 641 dev/ic/atwreg.h #define ATW_TOFS2_PWR1PAPE_MASK BITS(23, 20) /* delay of PAPE going high
BITS 644 dev/ic/atwreg.h #define ATW_TOFS2_PWR0TRSW_MASK BITS(19, 16) /* delay of TRSW going low
BITS 648 dev/ic/atwreg.h #define ATW_TOFS2_PWR1TRSW_MASK BITS(15, 12) /* delay of TRSW going high
BITS 651 dev/ic/atwreg.h #define ATW_TOFS2_PWR0PE2_MASK BITS(11, 8) /* delay of PE2 going low
BITS 655 dev/ic/atwreg.h #define ATW_TOFS2_PWR1PE2_MASK BITS(7, 4) /* delay of PE2 going high
BITS 658 dev/ic/atwreg.h #define ATW_TOFS2_PWR0TXPE_MASK BITS(3, 0) /* delay of TXPE going low
BITS 670 dev/ic/atwreg.h #define ATW_CMDR_DRT_MASK BITS(3, 2) /* drain Rx FIFO threshold */
BITS 686 dev/ic/atwreg.h #define ATW_PAR0_PAB0_MASK BITS(0, 7) /* MAC address byte 0 */
BITS 687 dev/ic/atwreg.h #define ATW_PAR0_PAB1_MASK BITS(8, 15) /* MAC address byte 1 */
BITS 688 dev/ic/atwreg.h #define ATW_PAR0_PAB2_MASK BITS(16, 23) /* MAC address byte 2 */
BITS 689 dev/ic/atwreg.h #define ATW_PAR0_PAB3_MASK BITS(24, 31) /* MAC address byte 3 */
BITS 691 dev/ic/atwreg.h #define ATW_C_PAR1_CTD BITS(16,31) /* Continuous Tx pattern */
BITS 692 dev/ic/atwreg.h #define ATW_PAR1_PAB5_MASK BITS(8, 15) /* MAC address byte 5 */
BITS 693 dev/ic/atwreg.h #define ATW_PAR1_PAB4_MASK BITS(0, 7) /* MAC address byte 4 */
BITS 695 dev/ic/atwreg.h #define ATW_MAR0_MAB3_MASK BITS(31, 24) /* multicast table bits 31:24 */
BITS 696 dev/ic/atwreg.h #define ATW_MAR0_MAB2_MASK BITS(23, 16) /* multicast table bits 23:16 */
BITS 697 dev/ic/atwreg.h #define ATW_MAR0_MAB1_MASK BITS(15, 8) /* multicast table bits 15:8 */
BITS 698 dev/ic/atwreg.h #define ATW_MAR0_MAB0_MASK BITS(7, 0) /* multicast table bits 7:0 */
BITS 700 dev/ic/atwreg.h #define ATW_MAR1_MAB7_MASK BITS(31, 24) /* multicast table bits 63:56 */
BITS 701 dev/ic/atwreg.h #define ATW_MAR1_MAB6_MASK BITS(23, 16) /* multicast table bits 55:48 */
BITS 702 dev/ic/atwreg.h #define ATW_MAR1_MAB5_MASK BITS(15, 8) /* multicast table bits 47:40 */
BITS 703 dev/ic/atwreg.h #define ATW_MAR1_MAB4_MASK BITS(7, 0) /* multicast table bits 39:32 */
BITS 706 dev/ic/atwreg.h #define ATW_ATIMDA0_ATIMB3_MASK BITS(31,24)
BITS 707 dev/ic/atwreg.h #define ATW_ATIMDA0_ATIMB2_MASK BITS(23,16)
BITS 708 dev/ic/atwreg.h #define ATW_ATIMDA0_ATIMB1_MASK BITS(15,8)
BITS 709 dev/ic/atwreg.h #define ATW_ATIMDA0_ATIMB0_MASK BITS(7,0)
BITS 712 dev/ic/atwreg.h #define ATW_ABDA1_BSSIDB5_MASK BITS(31,24)
BITS 713 dev/ic/atwreg.h #define ATW_ABDA1_BSSIDB4_MASK BITS(23,16)
BITS 714 dev/ic/atwreg.h #define ATW_ABDA1_ATIMB5_MASK BITS(15,8)
BITS 715 dev/ic/atwreg.h #define ATW_ABDA1_ATIMB4_MASK BITS(7,0)
BITS 718 dev/ic/atwreg.h #define ATW_BSSID0_BSSIDB3_MASK BITS(31,24)
BITS 719 dev/ic/atwreg.h #define ATW_BSSID0_BSSIDB2_MASK BITS(23,16)
BITS 720 dev/ic/atwreg.h #define ATW_BSSID0_BSSIDB1_MASK BITS(15,8)
BITS 721 dev/ic/atwreg.h #define ATW_BSSID0_BSSIDB0_MASK BITS(7,0)
BITS 723 dev/ic/atwreg.h #define ATW_TXLMT_MTMLT_MASK BITS(31,16) /* max TX MSDU lifetime in TU */
BITS 724 dev/ic/atwreg.h #define ATW_TXLMT_SRTYLIM_MASK BITS(7,0) /* short retry limit */
BITS 726 dev/ic/atwreg.h #define ATW_MIBCNT_FFCNT_MASK BITS(31,24) /* FCS failure count */
BITS 727 dev/ic/atwreg.h #define ATW_MIBCNT_AFCNT_MASK BITS(23,16) /* ACK failure count */
BITS 728 dev/ic/atwreg.h #define ATW_MIBCNT_RSCNT_MASK BITS(15,8) /* RTS success count */
BITS 729 dev/ic/atwreg.h #define ATW_MIBCNT_RFCNT_MASK BITS(7,0) /* RTS failure count */
BITS 731 dev/ic/atwreg.h #define ATW_BCNT_PLCPH_MASK BITS(23,16) /* 11M PLCP length (us) */
BITS 732 dev/ic/atwreg.h #define ATW_BCNT_PLCPL_MASK BITS(15,8) /* 5.5M PLCP length (us) */
BITS 733 dev/ic/atwreg.h #define ATW_BCNT_BCNT_MASK BITS(7,0) /* byte count of beacon frame */
BITS 738 dev/ic/atwreg.h #define ATW_C_BCNT_BEANLEN1 BITS(30,16) /* beacon length in us */
BITS 743 dev/ic/atwreg.h #define ATW_C_TSC_TIMOFS BITS(31,24) /* I think this is the
BITS 746 dev/ic/atwreg.h #define ATW_C_TSC_TIMLEN BITS(21,12) /* length of TIM */
BITS 748 dev/ic/atwreg.h #define ATW_TSC_TSC_MASK BITS(3,0) /* TSFT countdown value, 0
BITS 796 dev/ic/atwreg.h #define ATW_BPLI_BP_MASK BITS(31,16) /* beacon interval in TU */
BITS 797 dev/ic/atwreg.h #define ATW_BPLI_LI_MASK BITS(15,0) /* STA listen interval in
BITS 801 dev/ic/atwreg.h #define ATW_C_CAP0_TIMLEN1 BITS(31,24) /* TIM table 1 len in bytes
BITS 804 dev/ic/atwreg.h #define ATW_C_CAP0_TIMLEN0 BITS(23,16) /* TIM table 0 len in bytes,
BITS 807 dev/ic/atwreg.h #define ATW_C_CAP0_CWMAX BITS(11,8) /* 1 <= CWMAX <= 5 fixes CW?
BITS 813 dev/ic/atwreg.h #define ATW_CAP0_CHN_MASK BITS(3,0) /* current DSSS channel */
BITS 815 dev/ic/atwreg.h #define ATW_CAP1_CAPI_MASK BITS(31,16) /* capability information */
BITS 816 dev/ic/atwreg.h #define ATW_CAP1_ATIMW_MASK BITS(15,0) /* ATIM window in TU */
BITS 820 dev/ic/atwreg.h #define ATW_RMD_PCNT BITS(27,16) /* idle time between
BITS 823 dev/ic/atwreg.h #define ATW_RMD_RMRD_MASK BITS(15,0) /* max RX reception duration
BITS 827 dev/ic/atwreg.h #define ATW_CFPP_CFPP BITS(31,24) /* CFP unit DTIM */
BITS 828 dev/ic/atwreg.h #define ATW_CFPP_CFPMD BITS(23,8) /* CFP max duration in TU */
BITS 829 dev/ic/atwreg.h #define ATW_CFPP_DTIMP BITS(7,0) /* DTIM period in beacon
BITS 832 dev/ic/atwreg.h #define ATW_TOFS0_USCNT_MASK BITS(29,24) /* number of system clocks
BITS 836 dev/ic/atwreg.h #define ATW_C_TOFS0_TUCNT_MASK BITS(14,10) /* PIFS (microseconds) */
BITS 837 dev/ic/atwreg.h #define ATW_TOFS0_TUCNT_MASK BITS(9,0) /* TU counter in microseconds */
BITS 840 dev/ic/atwreg.h #define ATW_TOFS1_TSFTOFSR_MASK BITS(31,24) /* RX TSFT offset in
BITS 844 dev/ic/atwreg.h #define ATW_TOFS1_TBTTPRE_MASK BITS(23,8) /* prediction time, (next
BITS 849 dev/ic/atwreg.h #define ATW_TBTTPRE_MASK BITS(25, 10)
BITS 850 dev/ic/atwreg.h #define ATW_TOFS1_TBTTOFS_MASK BITS(7,0) /* wake-up time offset before
BITS 853 dev/ic/atwreg.h #define ATW_IFST_SLOT_MASK BITS(27,23) /* SLOT time in us */
BITS 854 dev/ic/atwreg.h #define ATW_IFST_SIFS_MASK BITS(22,15) /* SIFS time in us */
BITS 855 dev/ic/atwreg.h #define ATW_IFST_DIFS_MASK BITS(14,9) /* DIFS time in us */
BITS 856 dev/ic/atwreg.h #define ATW_IFST_EIFS_MASK BITS(8,0) /* EIFS time in us */
BITS 858 dev/ic/atwreg.h #define ATW_RSPT_MART_MASK BITS(31,16) /* max response time in us */
BITS 859 dev/ic/atwreg.h #define ATW_RSPT_MIRT_MASK BITS(15,8) /* min response time in us */
BITS 860 dev/ic/atwreg.h #define ATW_RSPT_TSFTOFST_MASK BITS(7,0) /* TX TSFT offset in us */
BITS 877 dev/ic/atwreg.h #define ATW_WEPCTL_TBLADD_MASK BITS(8,0) /* add to table */
BITS 885 dev/ic/atwreg.h #define ATW_WESK_DATA_MASK BITS(15,0) /* data */
BITS 886 dev/ic/atwreg.h #define ATW_WEPCNT_WIEC_MASK BITS(15,0) /* WEP ICV error count */
BITS 890 dev/ic/atwreg.h #define ATW_MACTEST_KEYID_MASK BITS(21,20)
BITS 910 dev/ic/atwreg.h #define ATW_SR_MAJOR_MASK BITS(7, 0)
BITS 911 dev/ic/atwreg.h #define ATW_SR_MINOR_MASK BITS(15,8)
BITS 916 dev/ic/atwreg.h #define ATW_SR_ANT_MASK BITS(12, 10)
BITS 917 dev/ic/atwreg.h #define ATW_SR_PWRSCALE_MASK BITS(9, 8)
BITS 918 dev/ic/atwreg.h #define ATW_SR_CLKSAVE_MASK BITS(7, 6)
BITS 919 dev/ic/atwreg.h #define ATW_SR_RFTYPE_MASK BITS(5, 3)
BITS 920 dev/ic/atwreg.h #define ATW_SR_BBPTYPE_MASK BITS(2, 0)
BITS 922 dev/ic/atwreg.h #define ATW_SR_CR28_MASK BITS(15,8)
BITS 923 dev/ic/atwreg.h #define ATW_SR_CR03_MASK BITS(7, 0)
BITS 925 dev/ic/atwreg.h #define ATW_SR_CTRY_MASK BITS(15,8) /* country code */
BITS 933 dev/ic/atwreg.h #define ATW_SR_CR29_MASK BITS(7, 0)
BITS 965 dev/ic/atwreg.h #define ATW_TXCTL_TXDR_MASK BITS(27,20) /* TX data rate (?) */
BITS 966 dev/ic/atwreg.h #define ATW_TXCTL_TL_MASK BITS(19,0) /* retry limit, 0 - 255 */
BITS 978 dev/ic/atwreg.h #define ATW_TXSTAT_ARC_MASK BITS(11,0) /* accumulated retry count */
BITS 985 dev/ic/atwreg.h #define ATW_TXFLAG_TBS2_MASK BITS(23,12) /* at_buf2 byte count */
BITS 986 dev/ic/atwreg.h #define ATW_TXFLAG_TBS1_MASK BITS(11,0) /* at_buf1 byte count */
BITS 1000 dev/ic/atwreg.h #define ATW_RXCTL_RBS2_MASK BITS(23,12) /* ar_buf2 byte count */
BITS 1001 dev/ic/atwreg.h #define ATW_RXCTL_RBS1_MASK BITS(11,0) /* ar_buf1 byte count */
BITS 1025 dev/ic/atwreg.h #define ATW_RXSTAT_RXDR_MASK BITS(15,12) /* RX data rate */
BITS 1026 dev/ic/atwreg.h #define ATW_RXSTAT_FL_MASK BITS(11,0) /* RX frame length, last
BITS 364 dev/ic/atwvar.h #define ATW_FRAGTHR_FRAGTHR_MASK BITS(0, 11)
BITS 365 dev/ic/atwvar.h #define ATW_FRAGNUM_FRAGNUM_MASK BITS(4, 7)
BITS 42 dev/ic/max2820reg.h #define MAX2820_TWI_ADDR_MASK BITS(15,12)
BITS 43 dev/ic/max2820reg.h #define MAX2820_TWI_DATA_MASK BITS(11,0)
BITS 50 dev/ic/max2820reg.h #define MAX2820_TEST_DEFAULT BITS(2,0) /* Always set to this value. */
BITS 110 dev/ic/max2820reg.h #define MAX2820_SYNTH_RSVD0 BITS(11,7) /* reserved */
BITS 115 dev/ic/max2820reg.h #define MAX2820_SYNTH_R_MASK BITS(5,0) /* Reference Frequency Divider
BITS 125 dev/ic/max2820reg.h #define MAX2820_CHANNEL_RSVD BITS(11,7) /* reserved */
BITS 126 dev/ic/max2820reg.h #define MAX2820_CHANNEL_CF_MASK BITS(6,0) /* Channel Frequency Select
BITS 135 dev/ic/max2820reg.h #define MAX2820_RECEIVE_2C_MASK BITS(11,9) /* VGA DC Offset Nulling
BITS 138 dev/ic/max2820reg.h #define MAX2820_RECEIVE_1C_MASK BITS(8,6) /* VGA DC Offset Nulling
BITS 141 dev/ic/max2820reg.h #define MAX2820_RECEIVE_DL_MASK BITS(5,4) /* Rx Level Detector Midpoint
BITS 151 dev/ic/max2820reg.h #define MAX2820_RECEIVE_BW_MASK BITS(2,0) /* Receive Filter -3dB Frequency
BITS 172 dev/ic/max2820reg.h #define MAX2820A_RECEIVE_2C_MASK BITS(11,9)
BITS 175 dev/ic/max2820reg.h #define MAX2820A_RECEIVE_1C_MASK BITS(8,6)
BITS 177 dev/ic/max2820reg.h #define MAX2820A_RECEIVE_RSVD0_MASK BITS(5,3)
BITS 179 dev/ic/max2820reg.h #define MAX2820A_RECEIVE_RSVD1_MASK BITS(2,0)
BITS 183 dev/ic/max2820reg.h #define MAX2820_TRANSMIT_RSVD_MASK BITS(11,4) /* reserved */
BITS 184 dev/ic/max2820reg.h #define MAX2820_TRANSMIT_PA_MASK BITS(3,0) /* PA Bias Select
BITS 50 dev/ic/rf3000reg.h #define RF3000_CTL_MODE_MASK BITS(7, 4)
BITS 70 dev/ic/rf3000reg.h #define RF3000_CCACTL_MODE_MASK BITS(7, 6)
BITS 75 dev/ic/rf3000reg.h #define RF3000_CCACTL_RSSIT_MASK BITS(5, 0)
BITS 82 dev/ic/rf3000reg.h #define RF3000_RSSI_MASK BITS(5, 0)
BITS 84 dev/ic/rf3000reg.h #define RF3000_GAINCTL_TXVGC_MASK BITS(7, 2)
BITS 87 dev/ic/rf3000reg.h #define RF3000_LOGAINCAL_CAL_MASK BITS(5, 0)
BITS 89 dev/ic/rf3000reg.h #define RF3000_HIGAINCAL_CAL_MASK BITS(5, 0)
BITS 98 dev/ic/rf3000reg.h #define RF3000_OPTIONS1_SAT_THRESH BITS(6,5)
BITS 107 dev/ic/rf3000reg.h #define RF3000_OPTIONS1_RESERVED0_MASK BITS(2,0)/* 0 */
BITS 112 dev/ic/rf3000reg.h #define RF3000_OPTIONS2_RESERVED0_MASK BITS(6,3) /* 0 */
BITS 115 dev/ic/rf3000reg.h #define RF3000_OPTIONS2_RESERVED1_MASK BITS(1,0) /* 0 */
BITS 26 dev/ic/rtl8225reg.h #define RTL8225_TWI_DATA_MASK BITS(31, 4)
BITS 27 dev/ic/rtl8225reg.h #define RTL8225_TWI_ADDR_MASK BITS(4, 0)
BITS 837 dev/ic/rtw.c (*addr)[0] = MASK_AND_RSHIFT(idr0, BITS(0, 7));
BITS 838 dev/ic/rtw.c (*addr)[1] = MASK_AND_RSHIFT(idr0, BITS(8, 15));
BITS 839 dev/ic/rtw.c (*addr)[2] = MASK_AND_RSHIFT(idr0, BITS(16, 23));
BITS 840 dev/ic/rtw.c (*addr)[3] = MASK_AND_RSHIFT(idr0, BITS(24 ,31));
BITS 842 dev/ic/rtw.c (*addr)[4] = MASK_AND_RSHIFT(idr1, BITS(0, 7));
BITS 843 dev/ic/rtw.c (*addr)[5] = MASK_AND_RSHIFT(idr1, BITS(8, 15));
BITS 109 dev/ic/rtwreg.h #define RTW8180_BRSR_MBR_MASK BITS(1,0) /* Basic Service Rate */
BITS 114 dev/ic/rtwreg.h #define RTW8185_BRSR_MBR_MASK BITS(11, 0) /* Basic Service Rate */
BITS 244 dev/ic/rtwreg.h #define RTW_TCR_HWVERID_MASK BITS(27, 25)
BITS 246 dev/ic/rtwreg.h #define RTW_TCR_HWVERID_RTL8180F BITS(26, 25)
BITS 258 dev/ic/rtwreg.h #define RTW_TCR_MXDMA_MASK BITS(23,21)
BITS 275 dev/ic/rtwreg.h #define RTW_TCR_LBK_MASK BITS(18,17)
BITS 289 dev/ic/rtwreg.h #define RTW_TCR_SRL_MASK BITS(15,8) /* Short Retry Limit */
BITS 290 dev/ic/rtwreg.h #define RTW_TCR_LRL_MASK BITS(7,0) /* Long Retry Limit */
BITS 317 dev/ic/rtwreg.h #define RTW8180_RCR_RXFTH_MASK BITS(15,13)
BITS 328 dev/ic/rtwreg.h #define RTW_RCR_MXDMA_MASK BITS(10,8)
BITS 384 dev/ic/rtwreg.h #define RTW_9346CR_EEM_MASK BITS(7,6) /* Operating Mode */
BITS 420 dev/ic/rtwreg.h #define RTW8180_CONFIG0_GL_MASK BITS(1,0)
BITS 438 dev/ic/rtwreg.h #define RTW_CONFIG1_LEDS_MASK BITS(7,6)
BITS 472 dev/ic/rtwreg.h #define RTW_CONFIG2_PAPETIME_MASK BITS(1,0) /* TBD, from EEPROM */
BITS 477 dev/ic/rtwreg.h #define RTW_ANAPARM_RFPOW0_MASK BITS(30,28) /* undocumented bits
BITS 489 dev/ic/rtwreg.h #define RTW_ANAPARM_RFPOW1_MASK BITS(26,20) /* undocumented bits
BITS 536 dev/ic/rtwreg.h #define RTW_ANAPARM_CARDSP_MASK BITS(19,0) /* undocumented
BITS 544 dev/ic/rtwreg.h #define RTW_MSR_NETYPE_MASK BITS(3,2)
BITS 610 dev/ic/rtwreg.h #define RTW_CONFIG4_RFTYPE_MASK BITS(1,0)
BITS 630 dev/ic/rtwreg.h #define RTW8180_SCR_KM_MASK BITS(5,4) /* Key Mode */
BITS 645 dev/ic/rtwreg.h #define RTW_BCNITV_BCNITV_MASK BITS(9,0) /* TU between TBTT, written
BITS 649 dev/ic/rtwreg.h #define RTW_ATIMWND_ATIMWND BITS(9,0) /* ATIM Window length in TU,
BITS 654 dev/ic/rtwreg.h #define RTW_BINTRITV_BINTRITV BITS(9,0) /* RTL8180 wakes host with
BITS 659 dev/ic/rtwreg.h #define RTW_ATIMTRITV_ATIMTRITV BITS(9,0) /* RTL8180 wakes host with
BITS 669 dev/ic/rtwreg.h #define RTW_PHYDELAY_PHYDELAY BITS(2,0) /* microsecond Tx delay between
BITS 679 dev/ic/rtwreg.h #define RTW_BB_RD_MASK BITS(23,16) /* data to read */
BITS 680 dev/ic/rtwreg.h #define RTW_BB_WR_MASK BITS(15,8) /* data to write */
BITS 682 dev/ic/rtwreg.h #define RTW_BB_ADDR_MASK BITS(6,0) /* address */
BITS 696 dev/ic/rtwreg.h #define RTW8180_PHYCFG_MAC_RFTYPE_MASK BITS(29,28)
BITS 705 dev/ic/rtwreg.h #define RTW8180_PHYCFG_MAC_PHILIPS_ADDR_MASK BITS(27,24)
BITS 706 dev/ic/rtwreg.h #define RTW8180_PHYCFG_MAC_PHILIPS_DATA_MASK BITS(23,0)
BITS 707 dev/ic/rtwreg.h #define RTW8180_PHYCFG_MAC_MAXIM_LODATA_MASK BITS(27,24)
BITS 708 dev/ic/rtwreg.h #define RTW8180_PHYCFG_MAC_MAXIM_ADDR_MASK BITS(11,8)
BITS 709 dev/ic/rtwreg.h #define RTW8180_PHYCFG_MAC_MAXIM_HIDATA_MASK BITS(7,0)
BITS 723 dev/ic/rtwreg.h #define RTW_MAXIM_HIDATA_MASK BITS(11,4)
BITS 724 dev/ic/rtwreg.h #define RTW_MAXIM_LODATA_MASK BITS(3,0)
BITS 791 dev/ic/rtwreg.h #define RTW8185_CAMRW_ADDRESS BITS(6, 0) /* CAM address */
BITS 799 dev/ic/rtwreg.h #define RTW8185_CAMDEBUG_WPACONFIG BITS(29, 24)
BITS 800 dev/ic/rtwreg.h #define RTW8185_CAMDEBUG_CAMKEY BITS(23, 0)
BITS 820 dev/ic/rtwreg.h #define RTW8185_CWVALUES_CWMAX BITS(7, 4) /* Max Contention Window */
BITS 821 dev/ic/rtwreg.h #define RTW8185_CWVALUES_CWMIN BITS(3, 0) /* Min Contention Window */
BITS 825 dev/ic/rtwreg.h #define RTW8185_RATEFALLBACKCTL_STEP BITS(1, 0)
BITS 895 dev/ic/rtwreg.h #define RTW_CWR_CW BITS(9,0)
BITS 900 dev/ic/rtwreg.h #define RTW_RETRYCTR_RETRYCT BITS(7,0)
BITS 973 dev/ic/rtwreg.h #define RTW_SR_RFPARM_CS_MASK BITS(2,3) /* carrier-sense type */
BITS 1003 dev/ic/rtwreg.h #define RTW_TXCTL0_RATE_MASK BITS(27,24) /* Tx rate */
BITS 1011 dev/ic/rtwreg.h #define RTW_TXCTL0_RTSRATE_MASK BITS(22,19) /* Tx rate */
BITS 1022 dev/ic/rtwreg.h #define RTW_TXCTL0_KEYID_MASK BITS(15,14) /* default key id */
BITS 1023 dev/ic/rtwreg.h #define RTW_TXCTL0_RSVD1_MASK BITS(13,12) /* reserved */
BITS 1024 dev/ic/rtwreg.h #define RTW_TXCTL0_TPKTSIZE_MASK BITS(11,0) /* Tx packet size
BITS 1032 dev/ic/rtwreg.h #define RTW_TXSTAT_RSVD1_MASK BITS(27,16)
BITS 1034 dev/ic/rtwreg.h #define RTW_TXSTAT_RTSRETRY_MASK BITS(14,8) /* RTS retry count */
BITS 1035 dev/ic/rtwreg.h #define RTW_TXSTAT_DRC_MASK BITS(7,0) /* Data retry count */
BITS 1041 dev/ic/rtwreg.h #define RTW_TXCTL1_LENGTH_MASK BITS(30,16) /* PLCP length (microseconds) */
BITS 1042 dev/ic/rtwreg.h #define RTW_TXCTL1_RTSDUR_MASK BITS(15,0) /* RTS Duration
BITS 1046 dev/ic/rtwreg.h #define RTW_TXLEN_LENGTH_MASK BITS(11,0) /* Tx buffer length in bytes */
BITS 1065 dev/ic/rtwreg.h #define RTW_RXCTL_RSVD0_MASK BITS(29,12) /* reserved */
BITS 1066 dev/ic/rtwreg.h #define RTW_RXCTL_LENGTH_MASK BITS(11,0) /* Rx buffer length */
BITS 1080 dev/ic/rtwreg.h #define RTW_RXSTAT_RATE_MASK BITS(23,20) /* Rx rate */
BITS 1100 dev/ic/rtwreg.h #define RTW_RXSTAT_LENGTH_MASK BITS(11,0) /* frame length, including
BITS 1114 dev/ic/rtwreg.h #define RTW_RXRSSI_VLAN BITS(32,16) /* XXX from reference driver */
BITS 1116 dev/ic/rtwreg.h #define RTW_RXRSSI_RSSI BITS(15,8) /* RF energy at the PHY */
BITS 1118 dev/ic/rtwreg.h #define RTW_RXRSSI_IMR_RSSI BITS(15,9) /* RF energy at the PHY */
BITS 1120 dev/ic/rtwreg.h #define RTW_RXRSSI_SQ BITS(7,0) /* Barker code-lock quality */
BITS 1235 dev/ic/rtwreg.h #define RTW_BBP_SYS2_RATE_MASK BITS(5,4) /* loopback rate?
BITS 1243 dev/ic/rtwreg.h #define RTW_BBP_SYS3_CSTHRESH_MASK BITS(0,3)
BITS 41 dev/ic/sa2400reg.h #define SA2400_TWI_DATA_MASK BITS(31,8)
BITS 43 dev/ic/sa2400reg.h #define SA2400_TWI_ADDR_MASK BITS(6,0)
BITS 53 dev/ic/sa2400reg.h #define SA2400_SYNA_NF_MASK BITS(20,18) /* fractional increment value,
BITS 56 dev/ic/sa2400reg.h #define SA2400_SYNA_N_MASK BITS(17,2) /* main divider division ratio,
BITS 61 dev/ic/sa2400reg.h #define SA2400_SYNB_R_MASK BITS(21,12) /* reference divider ratio,
BITS 64 dev/ic/sa2400reg.h #define SA2400_SYNB_L_MASK BITS(11,10) /* lock detect mode */
BITS 76 dev/ic/sa2400reg.h #define SA2400_SYNB_FC_MASK BITS(7,0) /* fractional compensation
BITS 82 dev/ic/sa2400reg.h #define SA2400_SYNC_CP_MASK BITS(7,6) /* charge pump current
BITS 90 dev/ic/sa2400reg.h #define SA2400_SYNC_SM_MASK BITS(5,3) /* comparison divider select,
BITS 97 dev/ic/sa2400reg.h #define SA2400_SYND_ZERO1_MASK BITS(21,17) /* always 0 */
BITS 105 dev/ic/sa2400reg.h #define SA2400_SYND_ZERO2_MASK BITS(14,3) /* always 0 */
BITS 119 dev/ic/sa2400reg.h #define SA2400_OPMODE_FILTTUNE_MASK BITS(17,15)
BITS 142 dev/ic/sa2400reg.h #define SA2400_OPMODE_MODE_MASK BITS(3,0)
BITS 160 dev/ic/sa2400reg.h #define SA2400_AGC_TARGET_MASK BITS(22,20) /* ... plus 0dB - 7dB */
BITS 161 dev/ic/sa2400reg.h #define SA2400_AGC_MAXGAIN_MASK BITS(19,15) /* maximum AGC gain, 0 to 31,
BITS 168 dev/ic/sa2400reg.h #define SA2400_AGC_BBPDELAY_MASK BITS(14,10)
BITS 175 dev/ic/sa2400reg.h #define SA2400_AGC_LNADELAY_MASK BITS(9,5)
BITS 182 dev/ic/sa2400reg.h #define SA2400_AGC_RXONDELAY_MASK BITS(4,0)
BITS 199 dev/ic/sa2400reg.h #define SA2400_MANRX_RXOSQ_MASK BITS(20,18)
BITS 203 dev/ic/sa2400reg.h #define SA2400_MANRX_RXOSI_MASK BITS(15,13)
BITS 213 dev/ic/sa2400reg.h #define SA2400_MANRX_CORNERFREQ_MASK BITS(11,10)
BITS 218 dev/ic/sa2400reg.h #define SA2400_MANRX_RXGAIN_MASK BITS(9,0)
BITS 228 dev/ic/sa2400reg.h #define SA2400_TX_TXOSQ_MASK BITS(17,15)
BITS 231 dev/ic/sa2400reg.h #define SA2400_TX_TXOSI_MASK BITS(12,10)
BITS 233 dev/ic/sa2400reg.h #define SA2400_TX_RAMP_MASK BITS(9,8) /* Ramp-up delay,
BITS 241 dev/ic/sa2400reg.h #define SA2400_TX_HIGAIN_MASK BITS(7,4) /* Transmitter gain settings
BITS 244 dev/ic/sa2400reg.h #define SA2400_TX_LOGAIN_MASK BITS(3,0) /* Transmitter gain settings
BITS 249 dev/ic/sa2400reg.h #define SA2400_VCO_ZERO BITS(6,5) /* always zero */
BITS 254 dev/ic/sa2400reg.h #define SA2400_VCO_VCOBAND_MASK BITS(3,0) /* VCO band,
BITS 41 dev/ic/si4136reg.h #define SI4126_TWI_DATA_MASK BITS(21, 4)
BITS 42 dev/ic/si4136reg.h #define SI4126_TWI_ADDR_MASK BITS(3, 0)
BITS 48 dev/ic/si4136reg.h #define SI4126_MAIN_AUXSEL_MASK BITS(13, 12) /* aux. output pin function */
BITS 56 dev/ic/si4136reg.h #define SI4126_MAIN_IFDIV_MASK BITS(11, 10) /* IFOUT = IFVCO
BITS 72 dev/ic/si4136reg.h #define SI4126_GAIN_KPI_MASK BITS(5, 4) /* IF phase detector gain */
BITS 73 dev/ic/si4136reg.h #define SI4126_GAIN_KP2_MASK BITS(3, 2) /* RF2 phase detector gain */
BITS 74 dev/ic/si4136reg.h #define SI4126_GAIN_KP1_MASK BITS(1, 0) /* RF1 phase detector gain */
BITS 291 lib/libz/infback.c state->last = BITS(1);
BITS 293 lib/libz/infback.c switch (BITS(2)) {
BITS 360 lib/libz/infback.c state->nlen = BITS(5) + 257;
BITS 362 lib/libz/infback.c state->ndist = BITS(5) + 1;
BITS 364 lib/libz/infback.c state->ncode = BITS(4) + 4;
BITS 383 lib/libz/infback.c state->lens[order[state->have++]] = (unsigned short)BITS(3);
BITS 404 lib/libz/infback.c this = state->lencode[BITS(state->lenbits)];
BITS 423 lib/libz/infback.c copy = 3 + BITS(2);
BITS 430 lib/libz/infback.c copy = 3 + BITS(3);
BITS 437 lib/libz/infback.c copy = 11 + BITS(7);
BITS 491 lib/libz/infback.c this = state->lencode[BITS(state->lenbits)];
BITS 499 lib/libz/infback.c (BITS(last.bits + last.op) >> last.bits)];
BITS 538 lib/libz/infback.c state->length += BITS(state->extra);
BITS 545 lib/libz/infback.c this = state->distcode[BITS(state->distbits)];
BITS 553 lib/libz/infback.c (BITS(last.bits + last.op) >> last.bits)];
BITS 571 lib/libz/infback.c state->offset += BITS(state->extra);
BITS 614 lib/libz/inflate.c ((BITS(8) << 8) + (hold >> 8)) % 31) {
BITS 623 lib/libz/inflate.c if (BITS(4) != Z_DEFLATED) {
BITS 633 lib/libz/inflate.c len = BITS(4) + 8;
BITS 810 lib/libz/inflate.c state->last = BITS(1);
BITS 812 lib/libz/inflate.c switch (BITS(2)) {
BITS 875 lib/libz/inflate.c state->nlen = BITS(5) + 257;
BITS 877 lib/libz/inflate.c state->ndist = BITS(5) + 1;
BITS 879 lib/libz/inflate.c state->ncode = BITS(4) + 4;
BITS 898 lib/libz/inflate.c state->lens[order[state->have++]] = (unsigned short)BITS(3);
BITS 923 lib/libz/inflate.c this = state->lencode[BITS(state->lenbits)];
BITS 946 lib/libz/inflate.c copy = 3 + BITS(2);
BITS 953 lib/libz/inflate.c copy = 3 + BITS(3);
BITS 960 lib/libz/inflate.c copy = 11 + BITS(7);
BITS 1020 lib/libz/inflate.c this = state->lencode[BITS(state->lenbits)];
BITS 1028 lib/libz/inflate.c (BITS(last.bits + last.op) >> last.bits)];
BITS 1062 lib/libz/inflate.c state->length += BITS(state->extra);
BITS 1069 lib/libz/inflate.c this = state->distcode[BITS(state->distbits)];
BITS 1077 lib/libz/inflate.c (BITS(last.bits + last.op) >> last.bits)];
BITS 1099 lib/libz/inflate.c state->offset += BITS(state->extra);