root/dev/pci/bt8370.c

DEFINITIONS

1. bt8370_reset
2. bt8370_set_frame_mode
3. bt8370_set_sbi_clock_mode
4. bt8370_set_bus_mode
5. bt8370_set_line_buildout
6. bt8370_set_loopback_mode
7. bt8370_set_bop_mode
8. bt8370_set_dl_1_mode
9. bt8370_set_dl_2_mode
10. bt8370_intr_enable
11. bt8370_intr
12. bt8370_link_status
13. bt8370_print_status
14. bt8370_print_counters
15. bt8370_dump_registers

    1 /*      $OpenBSD: bt8370.c,v 1.7 2006/01/31 16:51:13 claudio Exp $ */
    3 /*
    4  * Copyright (c) 2004,2005  Internet Business Solutions AG, Zurich, Switzerland
    5  * Written by: Andre Oppermann <oppermann@accoom.net>
    6  *
    7  * Permission to use, copy, modify, and distribute this software for any
    8  * purpose with or without fee is hereby granted, provided that the above
    9  * copyright notice and this permission notice appear in all copies.
   10  *
   11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
   14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
   15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
   16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
   17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
   18  */
   19 #include <sys/param.h>
   20 #include <sys/types.h>
   22 #include <sys/device.h>
   23 #include <sys/systm.h>
   24 #include <sys/socket.h>
   25 #include <sys/sockio.h>
   26 #include <sys/syslog.h>
   28 #include <net/if.h>
   29 #include <net/if_media.h>
   30 #include <net/if_types.h>
   31 #include <net/if_sppp.h>
   33 #include <netinet/in.h>
   34 #include <netinet/if_ether.h>
   36 #include <machine/cpu.h>
   37 #include <machine/bus.h>
   39 #include "musyccreg.h"
   40 #include "musyccvar.h"
   41 #include "if_art.h"
   42 #include "bt8370reg.h"
   44 #define FRAMER_LIU_E1_120       1
   45 #define FRAMER_LIU_T1_133       2
   47 void    bt8370_set_sbi_clock_mode(struct art_softc *, enum art_sbi_type,
u_int, int);
   49 void    bt8370_set_bus_mode(struct art_softc *, enum art_sbi_mode, int);
   50 void    bt8370_set_line_buildout(struct art_softc *, int);
   51 void    bt8370_set_loopback_mode(struct art_softc *, enum art_loopback);
   52 void    bt8370_set_bop_mode(struct art_softc *ac, int);
   53 void    bt8370_set_dl_1_mode(struct art_softc *, int);
   54 void    bt8370_set_dl_2_mode(struct art_softc *, int);
   55 void    bt8370_intr_enable(struct art_softc *ac, int);
   57 #ifndef ACCOOM_DEBUG
   58 #define bt8370_print_status(x)
   59 #define bt8370_print_counters(x)
   60 #define bt8370_dump_registers(x)
   61 #else
   62 void    bt8370_print_status(struct art_softc *);
   63 void    bt8370_print_counters(struct art_softc *);
   64 void    bt8370_dump_registers(struct art_softc *);
   65 #endif
   67 int
bt8370_reset(struct art_softc *ac)
   69 {
u_int8_t cr0;
ebus_write(&ac->art_ebus, Bt8370_CR0, 0x00);
DELAY(10);      /* 10 microseconds */
ebus_write(&ac->art_ebus, Bt8370_CR0, CR0_RESET);
DELAY(20);      /* 20 microseconds */
ebus_write(&ac->art_ebus, Bt8370_CR0, 0x00);
cr0 = ebus_read(&ac->art_ebus, Bt8370_CR0);
   78         if (cr0 != 0x0) {
log(LOG_ERR, "%s: reset not successful\n",
ac->art_dev.dv_xname);
   81                 return (-1);
   82         }
   83         return (0);
   84 }
   86 int
bt8370_set_frame_mode(struct art_softc *ac, enum art_sbi_type type, u_int mode,
u_int clockmode)
   89 {
   90         int channels;
   92         /* Get into a clean state */
bt8370_reset(ac);
   95         /* Disable all interrupts to be sure */
bt8370_intr_enable(ac, 0);
   98         switch (mode) {
   99         case IFM_TDM_E1:        /* 32 payload channels, bit transparent */
channels = 32;
  102                 /* Global Config */
ebus_write(&ac->art_ebus, Bt8370_CR0, CR0_E1_FAS);
  105                 /* Primary Config */
bt8370_set_loopback_mode(ac, ART_NOLOOP);
ebus_write(&ac->art_ebus, Bt8370_DL3_TS, 0x00);
  109                 /* Timing and Clock Config */
bt8370_set_sbi_clock_mode(ac, type, clockmode, channels);
  112                 /* Receiver RLIU, RCVR */
bt8370_set_line_buildout(ac, FRAMER_LIU_E1_120);
  114                 /* This one is critical */
ebus_write(&ac->art_ebus, Bt8370_RCR0, RCR0_HDB3 |
RCR0_RABORT | RCR0_LFA_FAS | RCR0_RZCS_NBPV);
ebus_write(&ac->art_ebus, Bt8370_RALM, 0x00);
ebus_write(&ac->art_ebus, Bt8370_LATCH, LATCH_STOPCNT);
  120                 /* Transmitter TLIU, XMTR */
ebus_write(&ac->art_ebus, Bt8370_TCR0, TCR0_FAS);
ebus_write(&ac->art_ebus, Bt8370_TCR1, TCR1_TABORT |
TCR1_HDB3);
ebus_write(&ac->art_ebus, Bt8370_TFRM, 0x00);
ebus_write(&ac->art_ebus, Bt8370_TMAN, 0x00);
ebus_write(&ac->art_ebus, Bt8370_TALM, 0x00);
ebus_write(&ac->art_ebus, Bt8370_TPATT, 0x00);
ebus_write(&ac->art_ebus, Bt8370_TLB, 0x00);
ebus_write(&ac->art_ebus, Bt8370_TSA4, 0xFF);
ebus_write(&ac->art_ebus, Bt8370_TSA5, 0xFF);
ebus_write(&ac->art_ebus, Bt8370_TSA6, 0xFF);
ebus_write(&ac->art_ebus, Bt8370_TSA7, 0xFF);
ebus_write(&ac->art_ebus, Bt8370_TSA8, 0xFF);
  135                 /* Bit Oriented Protocol Transceiver BOP disabled */
bt8370_set_bop_mode(ac, 0);
  138                 /* Data Link #1 disabled */
bt8370_set_dl_1_mode(ac, 0);
  141                 /* Data Link #2 disabled */
bt8370_set_dl_2_mode(ac, 0);
ACCOOM_PRINTF(1, ("%s: set to E1 G.703 unframed, HDB3\n",
ac->art_dev.dv_xname));
  146                 break;
  147         case IFM_TDM_E1_G704:   /* 31 payload channels, byte aligned */
channels = 32;
  150                 /* Global Config */
ebus_write(&ac->art_ebus, Bt8370_CR0, CR0_E1_FAS);
  153                 /* Primary Config */
bt8370_set_loopback_mode(ac, ART_NOLOOP);
ebus_write(&ac->art_ebus, Bt8370_DL3_TS, 0x00);
  157                 /* Timing and Clock Config */
bt8370_set_sbi_clock_mode(ac, type, clockmode, channels);
  160                 /* Receiver RLIU, RCVR */
bt8370_set_line_buildout(ac, FRAMER_LIU_E1_120);
  162                 /* This one is critical */
ebus_write(&ac->art_ebus, Bt8370_RCR0, RCR0_RFORCE |
RCR0_HDB3 | RCR0_LFA_FAS | RCR0_RZCS_NBPV);
ebus_write(&ac->art_ebus, Bt8370_RALM, RALM_FSNFAS);
ebus_write(&ac->art_ebus, Bt8370_LATCH, LATCH_STOPCNT);
  168                 /* Transmitter TLIU, XMTR */
ebus_write(&ac->art_ebus, Bt8370_TCR0, TCR0_FAS);
  170                 /* This one is critical */
ebus_write(&ac->art_ebus, Bt8370_TCR1, TCR1_TABORT |
TCR1_3FAS | TCR1_HDB3);
ebus_write(&ac->art_ebus, Bt8370_TFRM, TFRM_YEL |
TFRM_FBIT);
ebus_write(&ac->art_ebus, Bt8370_TMAN, TMAN_MALL);
ebus_write(&ac->art_ebus, Bt8370_TALM, TALM_AYEL);
ebus_write(&ac->art_ebus, Bt8370_TPATT, 0x00);
ebus_write(&ac->art_ebus, Bt8370_TLB, 0x00);
ebus_write(&ac->art_ebus, Bt8370_TSA4, 0xFF);
ebus_write(&ac->art_ebus, Bt8370_TSA5, 0xFF);
ebus_write(&ac->art_ebus, Bt8370_TSA6, 0xFF);
ebus_write(&ac->art_ebus, Bt8370_TSA7, 0xFF);
ebus_write(&ac->art_ebus, Bt8370_TSA8, 0xFF);
  185                 /* Bit Oriented Protocol Transceiver BOP disabled */
bt8370_set_bop_mode(ac, 0);
  188                 /* Data Link #1 disabled */
bt8370_set_dl_1_mode(ac, 0);
  191                 /* Data Link #2 disabled */
bt8370_set_dl_2_mode(ac, 0);
ACCOOM_PRINTF(1, ("%s: set to E1 G.704, HDB3\n",
ac->art_dev.dv_xname));
  196                 break;
  197         case IFM_TDM_E1_G704_CRC4:  /* 31 payload channels, byte aligned */
channels = 32;
  200                 /*
  201                  * Over normal G.704 the following registers need changes:
  202                  * CR0 = +CRC
  203                  * TFRM = +INS_CRC
  204                  */
  206                 /* Global Config */
ebus_write(&ac->art_ebus, Bt8370_CR0, CR0_E1_FAS_CRC);
  209                 /* Primary Config */
bt8370_set_loopback_mode(ac, ART_NOLOOP);
ebus_write(&ac->art_ebus, Bt8370_DL3_TS, 0x00);
  213                 /* Timing and Clock Config */
bt8370_set_sbi_clock_mode(ac, type, clockmode, channels);
  216                 /* Receiver RLIU, RCVR */
bt8370_set_line_buildout(ac, FRAMER_LIU_E1_120);
  218                 /* This one is critical */
ebus_write(&ac->art_ebus, Bt8370_RCR0, RCR0_RFORCE |
RCR0_HDB3 | RCR0_LFA_FASCRC | RCR0_RZCS_NBPV);
ebus_write(&ac->art_ebus, Bt8370_RALM, RALM_FSNFAS);
ebus_write(&ac->art_ebus, Bt8370_LATCH, LATCH_STOPCNT);
  224                 /* Transmitter TLIU, XMTR */
ebus_write(&ac->art_ebus, Bt8370_TCR0, TCR0_MFAS);
  226                 /* This one is critical */
ebus_write(&ac->art_ebus, Bt8370_TCR1, TCR1_TABORT |
TCR1_3FAS | TCR1_HDB3);
ebus_write(&ac->art_ebus, Bt8370_TFRM, TFRM_YEL |
TFRM_MF | TFRM_FE | TFRM_CRC | TFRM_FBIT);
ebus_write(&ac->art_ebus, Bt8370_TMAN, TMAN_MALL);
ebus_write(&ac->art_ebus, Bt8370_TALM, TALM_AYEL | TALM_AAIS);
ebus_write(&ac->art_ebus, Bt8370_TPATT, 0x00);
ebus_write(&ac->art_ebus, Bt8370_TLB, 0x00);
ebus_write(&ac->art_ebus, Bt8370_TSA4, 0xFF);
ebus_write(&ac->art_ebus, Bt8370_TSA5, 0xFF);
ebus_write(&ac->art_ebus, Bt8370_TSA6, 0xFF);
ebus_write(&ac->art_ebus, Bt8370_TSA7, 0xFF);
ebus_write(&ac->art_ebus, Bt8370_TSA8, 0xFF);
  241                 /* Bit Oriented Protocol Transceiver BOP disabled */
bt8370_set_bop_mode(ac, 0);
  244                 /* Data Link #1 disabled */
bt8370_set_dl_1_mode(ac, 0);
  247                 /* Data Link #2 disabled */
bt8370_set_dl_2_mode(ac, 0);
ACCOOM_PRINTF(1, ("%s: set to E1 G.704 CRC4, HDB3\n",
ac->art_dev.dv_xname));
  252                 break;
  253         case IFM_TDM_T1_AMI:    /* 24 payload channels, byte aligned */
channels = 25;  /* zero is ignored for T1 */
  256                 /* Global Config */
ebus_write(&ac->art_ebus, Bt8370_CR0, CR0_T1_SF);
  259                 /* Primary Config */
bt8370_set_loopback_mode(ac, ART_NOLOOP);
ebus_write(&ac->art_ebus, Bt8370_DL3_TS, 0x00);
  263                 /* Timing and Clock Config */
bt8370_set_sbi_clock_mode(ac, type, clockmode, channels);
  266                 /* Receiver RLIU, RCVR */
bt8370_set_line_buildout(ac, FRAMER_LIU_T1_133);
  268                 /* This one is critical */
ebus_write(&ac->art_ebus, Bt8370_RCR0, RCR0_RFORCE |
RCR0_AMI | RCR0_LFA_26F | RCR0_RZCS_NBPV);
ebus_write(&ac->art_ebus, Bt8370_RALM, RALM_FSNFAS);
ebus_write(&ac->art_ebus, Bt8370_LATCH, LATCH_STOPCNT);
  274                 /* Transmitter TLIU, XMTR */
ebus_write(&ac->art_ebus, Bt8370_TCR0, TCR0_SF);
  276                 /* This one is critical */
ebus_write(&ac->art_ebus, Bt8370_TCR1, TCR1_TABORT |
TCR1_26F | TCR1_AMI);
ebus_write(&ac->art_ebus, Bt8370_TFRM, TFRM_YEL |
TFRM_MF | TFRM_FBIT);
ebus_write(&ac->art_ebus, Bt8370_TMAN, 0x00);
ebus_write(&ac->art_ebus, Bt8370_TALM, TALM_AYEL);
ebus_write(&ac->art_ebus, Bt8370_TPATT, 0x00);
ebus_write(&ac->art_ebus, Bt8370_TLB, 0x00);
ebus_write(&ac->art_ebus, Bt8370_TSA4, 0xFF);
ebus_write(&ac->art_ebus, Bt8370_TSA5, 0xFF);
ebus_write(&ac->art_ebus, Bt8370_TSA6, 0xFF);
ebus_write(&ac->art_ebus, Bt8370_TSA7, 0xFF);
ebus_write(&ac->art_ebus, Bt8370_TSA8, 0xFF);
  291                 /* Bit Oriented Protocol Transceiver BOP disabled */
bt8370_set_bop_mode(ac, 0);
  294                 /* Data Link #1 disabled */
bt8370_set_dl_1_mode(ac, 0);
  297                 /* Data Link #2 disabled */
bt8370_set_dl_2_mode(ac, 0);
ACCOOM_PRINTF(1, ("%s: set to T1 SF, AMI\n",
ac->art_dev.dv_xname));
  302                 break;
  303         case IFM_TDM_T1:        /* 24 payload channels, byte aligned */
channels = 25;  /* zero is ignored for T1 */
  306                 /* Global Config */
ebus_write(&ac->art_ebus, Bt8370_CR0, CR0_T1_ESF);
  309                 /* Primary Config */
bt8370_set_loopback_mode(ac, ART_NOLOOP);
ebus_write(&ac->art_ebus, Bt8370_DL3_TS, 0x00);
  313                 /* Timing and Clock Config */
bt8370_set_sbi_clock_mode(ac, type, clockmode, channels);
  316                 /* Receiver RLIU, RCVR */
bt8370_set_line_buildout(ac, FRAMER_LIU_T1_133);
  318                 /* This one is critical */
ebus_write(&ac->art_ebus, Bt8370_RCR0, RCR0_RFORCE |
RCR0_B8ZS | RCR0_LFA_26F | RCR0_RZCS_NBPV);
ebus_write(&ac->art_ebus, Bt8370_RLB, 0x09);
ebus_write(&ac->art_ebus, Bt8370_LBA, 0x08);
ebus_write(&ac->art_ebus, Bt8370_LBD, 0x24);
ebus_write(&ac->art_ebus, Bt8370_RALM, 0x00);
ebus_write(&ac->art_ebus, Bt8370_LATCH, LATCH_STOPCNT);
  327                 /* Transmitter TLIU, XMTR */
ebus_write(&ac->art_ebus, Bt8370_TCR0, TCR0_ESFCRC);
  329                 /* This one is critical */
ebus_write(&ac->art_ebus, Bt8370_TCR1, TCR1_TABORT |
TCR1_26F | TCR1_B8ZS);
ebus_write(&ac->art_ebus, Bt8370_TFRM, TFRM_CRC |
TFRM_FBIT);
ebus_write(&ac->art_ebus, Bt8370_TMAN, 0x00);
ebus_write(&ac->art_ebus, Bt8370_TALM, TALM_AYEL);
ebus_write(&ac->art_ebus, Bt8370_TPATT, 0x00);
ebus_write(&ac->art_ebus, Bt8370_TLB, 0x00);
ebus_write(&ac->art_ebus, Bt8370_TSA4, 0xFF);
ebus_write(&ac->art_ebus, Bt8370_TSA5, 0xFF);
ebus_write(&ac->art_ebus, Bt8370_TSA6, 0xFF);
ebus_write(&ac->art_ebus, Bt8370_TSA7, 0xFF);
ebus_write(&ac->art_ebus, Bt8370_TSA8, 0xFF);
  344                 /* Bit Oriented Protocol Transceiver BOP setup */
bt8370_set_bop_mode(ac, ART_BOP_ESF);
  347                 /* Data Link #1 set to BOP mode for FDL */
bt8370_set_dl_1_mode(ac, ART_DL1_BOP);
  350                 /* Data Link #2 disabled */
bt8370_set_dl_2_mode(ac, 0);
ACCOOM_PRINTF(1, ("%s: set to T1 ESF CRC6, B8ZS\n",
ac->art_dev.dv_xname));
  355                 break;
  356         /*
  357          * case FAS_BSLIP:
  358          * case FAS_CRC_BSLIP:
  359          * case FAS_CAS:
  360          * case FAS_CAS_BSLIP:
  361          * case FAS_CRC_CAS:
  362          * case FAS_CRC_CAS_BSLIP:
  363          * case FT:
  364          * case ESF_NOCRC:
  365          * case SF_JYEL:
  366          * case SF_T1DM:
  367          * case SLC_FSLOF:
  368          * case SLC:
  369          * case ESF_xx (MimicCRC, ForceCRC?)
  370          *
  371          * are not yet implemented.
  372          * If you need one of them please contact us.
  373          */
  374         default:
  375                 return (-1);
  376         }
  377         return (0);
  378 }
  380 void
bt8370_set_sbi_clock_mode(struct art_softc *ac, enum art_sbi_type mode,
u_int linemode, int channels)
  383 {
u_int8_t cmux, jatcr;
  386         /*
  387          * mode is either master or slave.
  388          * linemode is either T1 (1544) or E1 (2048) external or internal.
  389          */
  390         switch (mode) {
  391         case ART_SBI_MASTER:
ACCOOM_PRINTF(1, ("%s: set to MASTER\n",
ac->art_dev.dv_xname));
  394                 /*
  395                  * ONESEC pulse output,
  396                  * RDL/TDL/INDY ignored,
  397                  * RFSYNC Receive Frame Sync output,
  398                  * RMSYNC Reveice MultiFrame Sync output,
  399                  * TFYNC Transmit Frame Sync output,
  400                  * TMSYNC Transmit MultiFrame Sync output.
  401                  */
ebus_write(&ac->art_ebus, Bt8370_PIO, PIO_ONESEC_IO |
PIO_TDL_IO | PIO_RFSYNC_IO | PIO_RMSYNC_IO |
PIO_TFSYNC_IO | PIO_TMSYNC_IO);
  405                 /*
  406                  * TDL/RDL/INDY/TCKO three-stated.
  407                  * CLADO enabled, drives SBI bus RCLK, TCLK and
  408                  *  is connected to own TSBCKI and TSBCKI on slave.
  409                  * RCKO enabled, is connected to TCKI on slave.
  410                  */
ebus_write(&ac->art_ebus, Bt8370_POE, POE_TDL_OE |
POE_RDL_OE | POE_INDY_OE | POE_TCKO_OE);
  413                 /*
  414                  * We are the SBI bus master and take clock from our own
  415                  * CLADO. The TCKI source depends on line or internal
  416                  * clocking.
  417                  */
cmux = CMUX_RSBCKI_CLADO | CMUX_TSBCKI_CLADO |
CMUX_CLADI_CLADI;
  420                 break;
  421         case ART_SBI_SLAVE:
ACCOOM_PRINTF(1, ("%s: set to SLAVE\n",
ac->art_dev.dv_xname));
  424                 /*
  425                  * ONESEC pulse input,
  426                  * RDL/TDL/INDY ignored,
  427                  * RFSYNC Receive Frame Sync input,
  428                  * RMSYNC Reveice MultiFrame Sync input,
  429                  * TFYNC Transmit Frame Sync input,
  430                  * TMSYNC Transmit MultiFrame Sync input.
  431                  */
ebus_write(&ac->art_ebus, Bt8370_PIO, PIO_TDL_IO);
  433                 /*
  434                  * TDL/RDL/INDY/TCKO three-stated.
  435                  * CLADO enabled, is connected to own ACKI and
  436                  * RSBCKI, ACKI on master.
  437                  * RCKO enabled, is connected to TCKI on master.
  438                  */
ebus_write(&ac->art_ebus, Bt8370_POE, POE_TDL_OE |
POE_RDL_OE | POE_INDY_OE | POE_TCKO_OE);
  441                 /*
  442                  * We are the SBI bus slave and take clock from TSBCKI.
  443                  * The TCKI source depends on line or internal clocking.
  444                  */
cmux = CMUX_RSBCKI_TSBCKI | CMUX_TSBCKI_TSBCKI |
CMUX_CLADI_CLADI;
  447                 break;
  448         case ART_SBI_SINGLE:
ACCOOM_PRINTF(1, ("%s: set to SINGLE\n",
ac->art_dev.dv_xname));
  451                 /*
  452                  * ONESEC pulse output,
  453                  * RDL/TDL/INDY ignored,
  454                  * RFSYNC Receive Frame Sync output,
  455                  * RMSYNC Reveice MultiFrame Sync output,
  456                  * TFSYNC Transmit Frame Sync output,
  457                  * TMSYNC Transmit MultiFrame Sync output.
  458                  */
ebus_write(&ac->art_ebus, Bt8370_PIO, PIO_ONESEC_IO |
PIO_TDL_IO | PIO_RFSYNC_IO | PIO_RMSYNC_IO |
PIO_TFSYNC_IO | PIO_TMSYNC_IO);
  462                 /*
  463                  * TDL/RDL/INDY/TCKO three-stated, CLADO/RCKO enabled.
  464                  */
ebus_write(&ac->art_ebus, Bt8370_POE, POE_TDL_OE |
POE_RDL_OE | POE_INDY_OE | POE_RCKO_OE);
  467                 /*
  468                  * We are the SBI bus master and take clock from our own
  469                  * CLADO. The TCKI source is always CLADO (jitter attenuated
  470                  * if receive clock).
  471                  */
cmux = CMUX_RSBCKI_CLADO | CMUX_TSBCKI_CLADO |
CMUX_CLADI_RCKO;
  474                 break;
  475         }
  477         /* Transmit clock from where? */
  478         switch (linemode) {
  479         case IFM_TDM_MASTER:
ACCOOM_PRINTF(1, ("%s: clock MASTER\n",
ac->art_dev.dv_xname));
  482                 if (mode == ART_SBI_MASTER)
cmux |= CMUX_TCKI_RSBCKI;
  484                 else
cmux |= CMUX_TCKI_CLADO;
jatcr = JAT_CR_JFREE;
  487                 break;
  488         /* case ART_CLOCK_EXTREF: */
  489         default:
ACCOOM_PRINTF(1, ("%s: clock LINE\n",
ac->art_dev.dv_xname));
cmux |= CMUX_TCKI_RCKO;
jatcr = JAT_CR_JEN | JAT_CR_JDIR_RX | JAT_CR_JSIZE32;
  494                 break;
  495         }
ebus_write(&ac->art_ebus, Bt8370_CMUX, cmux);
ebus_write(&ac->art_ebus, Bt8370_JAT_CR, jatcr);
  500         /* Set up the SBI (System Bus Interface) and clock source. */
  501         switch (mode) {
  502         case ART_SBI_MASTER:
ebus_write(&ac->art_ebus, Bt8370_CSEL, CSEL_VSEL_4096 |
CSEL_OSEL_4096);
bt8370_set_bus_mode(ac, SBI_MODE_4096_A, channels);
  506                 /* no need to set musycc port mode */
  507                 break;
  508         case ART_SBI_SLAVE:
  509                 /*
  510                  * On the slave the CLADO depends on the line type
  511                  * of the master.
  512                  */
bt8370_set_bus_mode(ac, SBI_MODE_4096_B, channels);
  514                 /* no need to set musycc port mode */
  515                 break;
  516         case ART_SBI_SINGLE:
  517                 if (channels == 25) {
ACCOOM_PRINTF(1, ("%s: SINGLE T1\n",
ac->art_dev.dv_xname));
ebus_write(&ac->art_ebus, Bt8370_CSEL, CSEL_VSEL_1544 |
CSEL_OSEL_1544);
bt8370_set_bus_mode(ac, SBI_MODE_1544, channels);
musycc_set_port(ac->art_channel->cc_group,
MUSYCC_PORT_MODE_T1);
  525                 } else {
ACCOOM_PRINTF(1, ("%s: SINGLE E1\n",
ac->art_dev.dv_xname));
ebus_write(&ac->art_ebus, Bt8370_CSEL, CSEL_VSEL_2048 |
CSEL_OSEL_2048);
bt8370_set_bus_mode(ac, SBI_MODE_2048, channels);
musycc_set_port(ac->art_channel->cc_group,
MUSYCC_PORT_MODE_E1);
  533                 }
  534                 break;
  535         }
ebus_write(&ac->art_ebus, Bt8370_CLAD_CR, CLAD_CR_LFGAIN);
  537 }
  539 void
bt8370_set_bus_mode(struct art_softc *ac, enum art_sbi_mode mode, int nchannels)
  541 {
bus_size_t channel;
  544         /*
  545          * Be aware that on the CN847x 'TSYNC_EDGE' has to be set to
  546          * 'raising edge' in the port config for this to work correctly.
  547          * All others (including RSYNC) are on 'falling edge'.
  548          */
ebus_write(&ac->art_ebus, Bt8370_RSB_CR, RSB_CR_BUS_RSB |
RSB_CR_SIG_OFF | RSB_CR_RPCM_NEG | RSB_CR_RSYN_NEG |
RSB_CR_RSB_CTR | TSB_CR_TSB_NORMAL);
ebus_write(&ac->art_ebus, Bt8370_RSYNC_BIT, 0x00);
ebus_write(&ac->art_ebus, Bt8370_RSYNC_TS, 0x00);
ebus_write(&ac->art_ebus, Bt8370_TSB_CR, TSB_CR_BUS_TSB |
TSB_CR_TPCM_NEG | TSB_CR_TSYN_NEG | TSB_CR_TSB_CTR |
TSB_CR_TSB_NORMAL);
ebus_write(&ac->art_ebus, Bt8370_TSYNC_BIT, 0x00);
ebus_write(&ac->art_ebus, Bt8370_TSYNC_TS, 0x00);
ebus_write(&ac->art_ebus, Bt8370_RSIG_CR, 0x00);
ebus_write(&ac->art_ebus, Bt8370_RSYNC_FRM, 0x00);
  562         /* Mode dependent */
  563         switch (mode) {
  564         case SBI_MODE_1536:
ebus_write(&ac->art_ebus, Bt8370_SBI_CR, SBI_CR_SBI_OE |
SBI_CR_1536);
  567                 break;
  568         case SBI_MODE_1544:
ebus_write(&ac->art_ebus, Bt8370_SBI_CR, SBI_CR_SBI_OE |
SBI_CR_1544);
  571                 break;
  572         case SBI_MODE_2048:
ebus_write(&ac->art_ebus, Bt8370_SBI_CR, SBI_CR_SBI_OE |
SBI_CR_2048);
  575                 break;
  576         case SBI_MODE_4096_A:
ebus_write(&ac->art_ebus, Bt8370_SBI_CR, SBI_CR_SBI_OE |
SBI_CR_4096_A);
  579                 break;
  580         case SBI_MODE_4096_B:
ebus_write(&ac->art_ebus, Bt8370_SBI_CR, SBI_CR_SBI_OE |
SBI_CR_4096_B);
  583                 break;
  584         case SBI_MODE_8192_A:
ebus_write(&ac->art_ebus, Bt8370_SBI_CR, SBI_CR_SBI_OE |
SBI_CR_8192_A);
  587                 break;
  588         case SBI_MODE_8192_B:
ebus_write(&ac->art_ebus, Bt8370_SBI_CR, SBI_CR_SBI_OE |
SBI_CR_8192_B);
  591                 break;
  592         case SBI_MODE_8192_C:
ebus_write(&ac->art_ebus, Bt8370_SBI_CR, SBI_CR_SBI_OE |
SBI_CR_8192_C);
  595                 break;
  596         case SBI_MODE_8192_D:
ebus_write(&ac->art_ebus, Bt8370_SBI_CR, SBI_CR_SBI_OE |
SBI_CR_8192_D);
  599                 break;
  600         }
  602         /* Initialize and reset all channels */
  603         for (channel = 0; channel < 32; channel++) {
ebus_write(&ac->art_ebus, Bt8370_SBCn + channel, 0x00);
ebus_write(&ac->art_ebus, Bt8370_TPCn + channel, 0x00);
ebus_write(&ac->art_ebus, Bt8370_TSIGn + channel, 0x00);
ebus_write(&ac->art_ebus, Bt8370_TSLIP_LOn + channel, 0x7e);
ebus_write(&ac->art_ebus, Bt8370_RSLIP_LOn + channel, 0x7e);
ebus_write(&ac->art_ebus, Bt8370_RPCn + channel, 0x00);
  610         }
  612         /* Configure used channels */
  613         for (channel = Bt8370_SBCn; channel < Bt8370_SBCn +
nchannels; channel++) {
ebus_write(&ac->art_ebus, channel, SBCn_RINDO |
SBCn_TINDO | SBCn_ASSIGN);
  617                 /* In T1 mode timeslot 0 must not be used. */
  618                 if (nchannels == 25 && channel == Bt8370_SBCn)
ebus_write(&ac->art_ebus, channel, 0x00);
  620         }
  621         for (channel = Bt8370_TPCn; channel < Bt8370_TPCn +
nchannels; channel++) {
ebus_write(&ac->art_ebus, channel, TPCn_CLEAR);
  624         }
  625         for (channel = Bt8370_RPCn; channel < Bt8370_RPCn +
nchannels; channel++) {
ebus_write(&ac->art_ebus, channel, RPCn_CLEAR);
  628         }
  629 }
  631 void
bt8370_set_line_buildout(struct art_softc *ac, int mode)
  633 {
  634         /*
  635          * LIU Stuff: Send and Reveive side
  636          * T1: 0-133, 133-266, 266-399, 399-533, 533-655,
  637          *     Long-Haul FCC Part 68.
  638          * E1: ITU-T G.703 120 Ohm Twisted Pair.
  639          */
ebus_write(&ac->art_ebus, Bt8370_RLIU_CR, RLIU_CR_FRZ_SHORT |
RLIU_CR_AGC2048 | RLIU_CR_LONG_EYE);
  644         switch (mode) {
  645         case FRAMER_LIU_T1_133:
  646                 /* Short haul */
ebus_write(&ac->art_ebus, Bt8370_VGA_MAX, 0x1F);
  648                 /* Force EQ off */
ebus_write(&ac->art_ebus, Bt8370_PRE_EQ, 0xA6);
ebus_write(&ac->art_ebus, Bt8370_TLIU_CR, TLIU_CR_100);
  652                 break;
  653 #if 0
  654         case FRAMER_LIU_T1_266:
  655         case FRAMER_LIU_T1_399:
  656         case FRAMER_LIU_T1_533:
  657         case FRAMER_LIU_T1_655:
  658         case FRAMER_LIU_T1_LH68:
  659 #endif
  660         case FRAMER_LIU_E1_120:
  661                 /* Short haul */
ebus_write(&ac->art_ebus, Bt8370_VGA_MAX, 0x1F);
  663                 /* Force EQ off */
ebus_write(&ac->art_ebus, Bt8370_PRE_EQ, 0xA6);
ebus_write(&ac->art_ebus, Bt8370_TLIU_CR, TLIU_CR_120);
  667                 break;
  668         }
  670         /*
  671          * Run this last.  The RLIU reset causes the values written above
  672          * to be activated.
  673          */
ebus_write(&ac->art_ebus, Bt8370_LIU_CR, LIU_CR_MAGIC |
LIU_CR_SQUELCH | LIU_CR_RST_LIU);
  676 }
  678 void
bt8370_set_loopback_mode(struct art_softc *ac, enum art_loopback mode)
  680 {
  681         switch (mode) {
  682         case ART_RLOOP_PAYLOAD: /* Remote digital payload loopback */
ebus_write(&ac->art_ebus, Bt8370_LOOP, LOOP_PLOOP);
  684                 break;
  685         case ART_RLOOP_LINE:    /* Remote analog line signal loopback */
ebus_write(&ac->art_ebus, Bt8370_LOOP, LOOP_LLOOP);
  687                 break;
  688         case ART_LLOOP_PAYLOAD: /* Local digital payload loopback */
ebus_write(&ac->art_ebus, Bt8370_LOOP, LOOP_FLOOP);
  690                 break;
  691         case ART_LLOOP_LINE:    /* Local analog line signal loopback */
ebus_write(&ac->art_ebus, Bt8370_LOOP, LOOP_ALOOP);
  693                 break;
  694         case ART_NOLOOP:        /* Disable all loopbacks */
ebus_write(&ac->art_ebus, Bt8370_LOOP, 0x00);
  696                 break;
  697         }
  698 }
  700 void
bt8370_set_bop_mode(struct art_softc *ac, int mode)
  702 {
  703         /* disabled or ESF mode */
  704         switch (mode) {
  705         case ART_BOP_ESF:
ebus_write(&ac->art_ebus, Bt8370_BOP, 0x9A);
  707                 break;
  708         default:
ebus_write(&ac->art_ebus, Bt8370_BOP, 0x00);
  710                 break;
  711         }
  712 }
  714 void
bt8370_set_dl_1_mode(struct art_softc *ac, int mode)
  716 {
  717         /*
  718          * We don't support the builtin HDLC controllers,
  719          * however some DL1 registers are used for the BOP
  720          * in ESF mode.
  721          */
  722         switch (mode) {
  723         case ART_DL1_BOP:
ebus_write(&ac->art_ebus, Bt8370_DL1_TS, 0x40);
ebus_write(&ac->art_ebus, Bt8370_DL1_CTL, 0x03);
ebus_write(&ac->art_ebus, Bt8370_RDL1_FFC, 0x0A);
ebus_write(&ac->art_ebus, Bt8370_PRM1, 0x80);
ebus_write(&ac->art_ebus, Bt8370_TDL1_FEC, 0x0A);
  729                 break;
  730         default:
ebus_write(&ac->art_ebus, Bt8370_RDL1_FFC, 0x0A);
ebus_write(&ac->art_ebus, Bt8370_TDL1, 0x00);
  733                 break;
  734         }
  735 }
  737 void
bt8370_set_dl_2_mode(struct art_softc *ac, int mode)
  739 {
  740         /* We don't support the builtin HDLC controllers. */
ebus_write(&ac->art_ebus, Bt8370_RDL2_FFC, 0x0A);
ebus_write(&ac->art_ebus, Bt8370_TDL2, 0x00);
  743 }
  745 void
bt8370_intr_enable(struct art_softc *ac, int intr)
  747 {
  748         switch (intr) {
  749         default:
  750                 /* Disable all interrupts */
ebus_write(&ac->art_ebus, Bt8370_IER7, 0x00);
ebus_write(&ac->art_ebus, Bt8370_IER6, 0x00);
ebus_write(&ac->art_ebus, Bt8370_IER5, 0x00);
ebus_write(&ac->art_ebus, Bt8370_IER4, 0x00);
ebus_write(&ac->art_ebus, Bt8370_IER3, 0x00);
ebus_write(&ac->art_ebus, Bt8370_IER2, 0x00);
ebus_write(&ac->art_ebus, Bt8370_IER1, 0x00);
ebus_write(&ac->art_ebus, Bt8370_IER0, 0x00);
  759                 break;
  760         }
  761         return;
  762 }
  764 void
bt8370_intr(struct art_softc *ac)
  766 {
u_int8_t irr, alrm;
  769         /* IRR tells us which interrupt class fired. */
irr = ebus_read(&ac->art_ebus, Bt8370_IRR);
  771         /* If it wasn't us don't waste time. */
  772         if (irr == 0x00)
  773                 return;
  775         /* Reding the interrupt service registers clears them. */
alrm = ebus_read(&ac->art_ebus, Bt8370_ISR7);
alrm = ebus_read(&ac->art_ebus, Bt8370_ISR6);
alrm = ebus_read(&ac->art_ebus, Bt8370_ISR5);
alrm = ebus_read(&ac->art_ebus, Bt8370_ISR4);
alrm = ebus_read(&ac->art_ebus, Bt8370_ISR3);
alrm = ebus_read(&ac->art_ebus, Bt8370_ISR2);
alrm = ebus_read(&ac->art_ebus, Bt8370_ISR1);
alrm = ebus_read(&ac->art_ebus, Bt8370_ISR0);
  785         /* IRR should be zero now or something went wrong. */
irr = ebus_read(&ac->art_ebus, Bt8370_IRR);
  787         if (irr != 0x00)
ACCOOM_PRINTF(0, ("%s: Interrupts did not clear properly\n",
ac->art_dev.dv_xname));
  790         return;
  791 }
  793 int
bt8370_link_status(struct art_softc *ac)
  795 {
u_int8_t rstat, alm1, alm2, alm3, alm1mask;
  797         int status = 1;
  799         /*
  800          *  1 everything fine
  801          *  0 framing problems but link detected
  802          * -1 no link detected
  803          */
alm1mask = ALM1_RYEL | ALM1_RAIS | ALM1_RALOS | ALM1_RLOF;
  806         /*
  807          * XXX don't check RYEL in T1 mode it toggles more or less
  808          * regular.
  809          */
  810         if (IFM_SUBTYPE(ac->art_media) == IFM_TDM_T1)
alm1mask &= ~ALM1_RYEL;
rstat = ebus_read(&ac->art_ebus, Bt8370_RSTAT);
alm1 = ebus_read(&ac->art_ebus, Bt8370_ALM1);
alm2 = ebus_read(&ac->art_ebus, Bt8370_ALM2);
alm3 = ebus_read(&ac->art_ebus, Bt8370_ALM3);
  818         if ((rstat & (RSTAT_EXZ | RSTAT_BPV)) ||
  819             (alm1 & alm1mask) || (alm3 & (ALM3_SEF)))
status = 0;
  822         if ((alm1 & (ALM1_RLOS)) ||
  823             (alm2 & (ALM2_TSHORT)))
status = -1;
  826         return (status);
  827 }
  829 #ifdef ACCOOM_DEBUG
  830 void
bt8370_print_status(struct art_softc *ac)
  832 {
u_int8_t        fstat, rstat, vga, alm1, alm2, alm3, sstat, loop;
  835         /* FSTAT Register. */
fstat = ebus_read(&ac->art_ebus, Bt8370_FSTAT);
printf("%s: Current FSTAT:\n", ac->art_dev.dv_xname);
  838         if (fstat & FSTAT_ACTIVE) {
printf("\tOffline Framer active ");
  840                 if (fstat & FSTAT_RXTXN)
printf("in Receive direction\n");
  842                 else
printf("in Transmit direction\n");
  844                 if (fstat & FSTAT_INVALID)
printf("\tNo Candidate found\n");
  846                 if (fstat & FSTAT_FOUND)
printf("\tFrame Alignment found\n");
  848                 if (fstat & FSTAT_TIMEOUT)
printf("\tFramer Search timeout\n");
  850         } else
printf("\tOffline inactive\n");
  853         /* RSTAT and VGA Register. */
rstat = ebus_read(&ac->art_ebus, Bt8370_RSTAT);
printf("%s: Current RSTAT:\n", ac->art_dev.dv_xname);
  856         if (rstat & RSTAT_CPDERR)
printf("\tCLAD phase detector lost lock to CLADI reference\n");
  858         if (rstat & RSTAT_ZCSUB)
printf("\tHDB3/B8ZS pattern detected\n");
  860         if (rstat & RSTAT_EXZ)
printf("\tExcessive zeros detected\n");
  862         if (rstat & RSTAT_BPV)
printf("\tBipolar violations\n");
  864         if (rstat & RSTAT_EYEOPEN)
printf("\tReceived signal valid and RPLL locked\n");
  866         else
printf("\tReceived signal invalid\n");
  868         if (rstat & RSTAT_PRE_EQ)
printf("\tPre-Equalizer is ON\n");
  870         else
printf("\tPre-Equalizer is OFF\n");
  872         /* Need to write something to cause internal update. */
ebus_write(&ac->art_ebus, Bt8370_VGA, 0x00);
vga = ebus_read(&ac->art_ebus, Bt8370_VGA);
printf("\t%i dB Gain\n", vga);
  877         /* Alarm 1 Status. */
alm1 = ebus_read(&ac->art_ebus, Bt8370_ALM1);
printf("%s: Current ALM1:\n", ac->art_dev.dv_xname);
  880         if (alm1 & ALM1_RMYEL)
printf("\tMultiframe Yellow Alarm [MYEL]\n");
  882         if (alm1 & ALM1_RYEL)
printf("\tYellow Alarm [YEL]\n");
  884         if (alm1 & ALM1_RAIS)
printf("\tRemote Alarm Indication [RAIS]\n");
  886         if (alm1 & ALM1_RALOS)
printf("\tAnalog Loss of Signal or RCKI Loss of Clock [RALOS]\n");
  888         if (alm1 & ALM1_RLOS)
printf("\tLoss of Signal [RLOS]\n");
  890         if (alm1 & ALM1_RLOF)
printf("\tLoss of Frame Alignment [RLOF]\n");
  892         if (alm1 & ALM1_SIGFRZ)
printf("\tSignalling Freeze\n");
  895         /* Alarm 2 Status. */
alm2 = ebus_read(&ac->art_ebus, Bt8370_ALM2);
printf("%s: Current ALM2:\n", ac->art_dev.dv_xname);
  898         if (alm2 & ALM2_LOOPDN)
printf("\tLOOPDN code detected\n");
  900         if (alm2 & ALM2_LOOPUP)
printf("\tLOOPUP code detected\n");
  902         if (alm2 & ALM2_TSHORT)
printf("\tTransmitter short circuit\n");
  904         if (alm2 & ALM2_TLOC)
printf("\tTransmit loss of clock (relative to ACKI)\n");
  906         if (alm2 & ALM2_TLOF)
printf("\tTransmit loss of frame alignment (ignored)\n");
  909         /* Alarm 3 Status. */
alm3 = ebus_read(&ac->art_ebus, Bt8370_ALM3);
printf("%s: Current ALM3:\n", ac->art_dev.dv_xname);
  912         if (alm3 & ALM3_RMAIS)
printf("\tRMAIS TS16 Alarm Indication Signal\n");
  914         if (alm3 & ALM3_SEF)
printf("\tSeverely Errored Frame encountered\n");
  916         if (alm3 & ALM3_SRED)
printf("\tLoss of CAS Alignment\n");
  918         if (alm3 & ALM3_MRED)
printf("\tLoss of MFAS Alignment\n");
  920         if (alm3 & ALM3_FRED)
printf("\tLoss of T1/FAS Alignment\n");
  922         /* LOF omitted */
  924         /* Slip Buffer Status. */
sstat = ebus_read(&ac->art_ebus, Bt8370_SSTAT);
printf("%s: Current SSTAT:\n", ac->art_dev.dv_xname);
  927         if (sstat & SSTAT_TFSLIP) {
  928                 if (sstat & SSTAT_TUSLIP)
printf("\tControlled Transmit Slip, ");
  930                 else
printf("\tUncontrolled Transmit Slip, ");
  932                 if (sstat & SSTAT_TSDIR)
printf("repeated one frame\n");
  934                 else
printf("deleted one frame\n");
  936         } else if (sstat & SSTAT_RFSLIP) {
  937                 if (sstat & SSTAT_RUSLIP)
printf("\tControlled Receive Slip, ");
  939                 else
printf("\tUncontrolled Receive Slip, ");
  941                 if (sstat & SSTAT_RSDIR)
printf("repeated one frame\n");
  943                 else
printf("deleted one frame\n");
  945         }
  947         /* Loopback Status. */
loop = ebus_read(&ac->art_ebus, Bt8370_LOOP);
printf("%s: Current LOOP:\n", ac->art_dev.dv_xname);
  950         if (loop & LOOP_PLOOP)
printf("\tRemote Payload Loopback\n");
  952         if (loop & LOOP_LLOOP)
printf("\tRemote Line Loopback\n");
  954         if (loop & LOOP_FLOOP)
printf("\tLocal Payload Loopback\n");
  956         if (loop & LOOP_ALOOP)
printf("\tLocal Line Loopback\n");
  958         if (loop & 0x00)
printf("\tNo active Loopbacks\n");
  960 }
  962 void
bt8370_print_counters(struct art_softc *ac)
  964 {
u_int16_t       counters[5];
u_int16_t       hi, lo;
  967         int             i;
  969         for (i = 0; i < 5; i++) {
lo = ebus_read(&ac->art_ebus, Bt8370_FERR_LSB + i);
hi = ebus_read(&ac->art_ebus, Bt8370_FERR_LSB + i + 1);
counters[i] = lo | (hi << 8);
  974         }
printf("%s: %hu framing bit errors, %hu CRC errors, ",
ac->art_dev.dv_xname, counters[0], counters[1]);
printf("%hu line code violations\n", counters[2]);
printf("%s: %hu Far End Errors %hu PRBS bit errors\n",
ac->art_dev.dv_xname, counters[3], counters[4]);
  981 }
  982 void
bt8370_dump_registers(struct art_softc *ac)
  984 {
  985         int     i;
printf("%s: dummping registers", ac->art_dev.dv_xname);
  988         for (i = 0; i < 0x200; i++) {
  989                 if (i % 16 == 0)
printf("\n%03x:", i);
printf("%s%02x%s", i % 2 ? "" : " ",
ebus_read(&ac->art_ebus, i),
i % 8 == 7 ? " " : "");
  994         }
printf("\n");
  996 }
  998 #endif