1 /* $OpenBSD: atavar.h,v 1.18 2004/09/24 07:05:44 grange Exp $ */
2 /* $NetBSD: atavar.h,v 1.13 1999/03/10 13:11:43 bouyer Exp $ */
3
4 /*
5 * Copyright (c) 1998, 2001 Manuel Bouyer.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Manuel Bouyer.
18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35 #ifndef _DEV_ATA_ATAVAR_H_
36 #define _DEV_ATA_ATAVAR_H_
37
38 /* High-level functions and structures used by both ATA and ATAPI devices */
39 #include <dev/ata/atareg.h>
40
41 /* Datas common to drives and controller drivers */
42 struct ata_drive_datas {
43 u_int8_t drive; /* drive number */
44 int8_t ata_vers; /* ATA version supported */
45 u_int16_t drive_flags; /* bitmask for drives present/absent and cap */
46 #define DRIVE_ATA 0x0001
47 #define DRIVE_ATAPI 0x0002
48 #define DRIVE_OLD 0x0004
49 #define DRIVE (DRIVE_ATA|DRIVE_ATAPI|DRIVE_OLD)
50 #define DRIVE_CAP32 0x0008
51 #define DRIVE_DMA 0x0010
52 #define DRIVE_UDMA 0x0020
53 #define DRIVE_MODE 0x0040 /* the drive reported its mode */
54 #define DRIVE_RESET 0x0080 /* reset the drive state at next xfer */
55 #define DRIVE_DMAERR 0x0100 /* Udma transfer had crc error, don't try DMA */
56 #define DRIVE_DSCBA 0x0200 /* DSC in buffer availability mode */
57 #define DRIVE_DSCWAIT 0x0400 /* In wait for DSC to be asserted */
58 #define DRIVE_DEVICE_RESET 0x0800 /* Drive supports DEVICE RESET command */
59 #define DRIVE_SATA 0x1000 /* SATA drive */
60 /*
61 * Current setting of drive's PIO, DMA and UDMA modes.
62 * Is initialised by the disks drivers at attach time, and may be
63 * changed later by the controller's code if needed
64 */
65 u_int8_t PIO_mode; /* Current setting of drive's PIO mode */
66 u_int8_t DMA_mode; /* Current setting of drive's DMA mode */
67 u_int8_t UDMA_mode; /* Current setting of drive's UDMA mode */
68 /* Supported modes for this drive */
69 u_int8_t PIO_cap; /* supported drive's PIO mode */
70 u_int8_t DMA_cap; /* supported drive's DMA mode */
71 u_int8_t UDMA_cap; /* supported drive's UDMA mode */
72 /*
73 * Drive state. This is drive-type (ATA or ATAPI) dependant
74 * This is reset to 0 after a channel reset.
75 */
76 u_int8_t state;
77
78 #define ACAP_LEN 0x01 /* 16 byte commands */
79 #define ACAP_DSC 0x02 /* use DSC signalling */
80 /* 0x20-0x40 reserved for ATAPI_CFG_DRQ_MASK */
81 u_int8_t atapi_cap;
82
83 /* Keeps track of the number of resets that have occurred in a row
84 without a successful command completion. */
85 u_int8_t n_resets;
86 u_int8_t n_dmaerrs;
87 u_int32_t n_xfers;
88 #define NERRS_MAX 4
89 #define NXFER 1000
90
91 char drive_name[31];
92 int cf_flags;
93 void *chnl_softc; /* channel softc */
94
95 struct ataparams id;
96 };
97
98 /* ATA/ATAPI common attachement datas */
99 struct ata_atapi_attach {
100 u_int8_t aa_type; /* Type of device */
101 #define T_ATA 0
102 #define T_ATAPI 1
103 u_int8_t aa_channel; /* controller's channel */
104 u_int8_t aa_openings; /* Number of simultaneous commands possible */
105 struct ata_drive_datas *aa_drv_data;
106 void *aa_bus_private; /* infos specifics to this bus */
107 };
108
109 /* User config flags that force (or disable) the use of a mode */
110 #define ATA_CONFIG_PIO_MODES 0x0007
111 #define ATA_CONFIG_PIO_SET 0x0008
112 #define ATA_CONFIG_PIO_OFF 0
113 #define ATA_CONFIG_DMA_MODES 0x0070
114 #define ATA_CONFIG_DMA_SET 0x0080
115 #define ATA_CONFIG_DMA_DISABLE 0x0070
116 #define ATA_CONFIG_DMA_OFF 4
117 #define ATA_CONFIG_UDMA_MODES 0x0700
118 #define ATA_CONFIG_UDMA_SET 0x0800
119 #define ATA_CONFIG_UDMA_DISABLE 0x0700
120 #define ATA_CONFIG_UDMA_OFF 8
121
122 /*
123 * ATA/ATAPI commands description
124 *
125 * This structure defines the interface between the ATA/ATAPI device driver
126 * and the controller for short commands. It contains the command's parameter,
127 * the len of data's to read/write (if any), and a function to call upon
128 * completion.
129 * If no sleep is allowed, the driver can poll for command completion.
130 * Once the command completed, if the error registed is valid, the flag
131 * AT_ERROR is set and the error register value is copied to r_error .
132 * A separate interface is needed for read/write or ATAPI packet commands
133 * (which need multiple interrupts per commands).
134 */
135 struct wdc_command {
136 u_int8_t r_command; /* Parameters to upload to registers */
137 u_int8_t r_head;
138 u_int16_t r_cyl;
139 u_int8_t r_sector;
140 u_int8_t r_count;
141 u_int8_t r_precomp;
142 u_int8_t r_st_bmask; /* status register mask to wait for before command */
143 u_int8_t r_st_pmask; /* status register mask to wait for after command */
144 u_int8_t r_error; /* error register after command done */
145 volatile u_int16_t flags;
146 #define AT_READ 0x0001 /* There is data to read */
147 #define AT_WRITE 0x0002 /* There is data to write (excl. with AT_READ) */
148 #define AT_WAIT 0x0008 /* wait in controller code for command completion */
149 #define AT_POLL 0x0010 /* poll for command completion (no interrupts) */
150 #define AT_DONE 0x0020 /* command is done */
151 #define AT_ERROR 0x0040 /* command is done with error */
152 #define AT_TIMEOU 0x0080 /* command timed out */
153 #define AT_DF 0x0100 /* Drive fault */
154 #define AT_READREG 0x0200 /* Read registers on completion */
155 int timeout; /* timeout (in ms) */
156 void *data; /* Data buffer address */
157 int bcount; /* number of bytes to transfer */
158 void (*callback)(void *); /* command to call once command completed */
159 void *callback_arg; /* argument passed to *callback() */
160 };
161
162 extern int at_poll;
163
164 int wdc_exec_command(struct ata_drive_datas *, struct wdc_command*);
165 #define WDC_COMPLETE 0x01
166 #define WDC_QUEUED 0x02
167 #define WDC_TRY_AGAIN 0x03
168
169 void wdc_probe_caps(struct ata_drive_datas*, struct ataparams *);
170 void wdc_print_caps(struct ata_drive_datas*);
171 int wdc_downgrade_mode(struct ata_drive_datas*);
172
173 void wdc_reset_channel(struct ata_drive_datas *);
174
175 int wdc_ata_addref(struct ata_drive_datas *);
176 void wdc_ata_delref(struct ata_drive_datas *);
177 void wdc_ata_kill_pending(struct ata_drive_datas *);
178
179 int ata_get_params(struct ata_drive_datas*, u_int8_t,
180 struct ataparams *);
181 int ata_set_mode(struct ata_drive_datas*, u_int8_t, u_int8_t);
182 /* return code for these cmds */
183 #define CMD_OK 0
184 #define CMD_ERR 1
185 #define CMD_AGAIN 2
186
187 void ata_dmaerr(struct ata_drive_datas *);
188 void ata_perror(struct ata_drive_datas *, int, char *, size_t);
189
190 #endif /* !_DEV_ATA_ATAVAR_H_ */