1 /* $OpenBSD: pciidereg.h,v 1.7 2004/10/17 08:44:41 grange Exp $ */
2 /* $NetBSD: pciidereg.h,v 1.6 2000/11/14 18:42:58 thorpej Exp $ */
3
4 /*
5 * Copyright (c) 1998 Christopher G. Demetriou. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Christopher G. Demetriou
18 * for the NetBSD Project.
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef _DEV_PCI_PCIIDEREG_H_
35 #define _DEV_PCI_PCIIDEREG_H_
36
37 /*
38 * PCI IDE controller register definitions.
39 *
40 * Author: Christopher G. Demetriou, March 2, 1998.
41 *
42 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and
43 * "Programming Interface for Bus Master IDE Controller, Revision 1.0
44 * 5/16/94" from the PCI SIG.
45 */
46
47 /*
48 * Number of channels per chip. MUST NOT CHANGE (macros in pciide.c and
49 * this file depend on its value).
50 */
51 #define PCIIDE_NUM_CHANNELS 2
52
53 /*
54 * PCI base address register locations (some are per-channel).
55 */
56 #define PCIIDE_REG_CMD_BASE(chan) (0x10 + (8 * (chan)))
57 #define PCIIDE_REG_CTL_BASE(chan) (0x14 + (8 * (chan)))
58 #define PCIIDE_REG_BUS_MASTER_DMA 0x20
59
60 /*
61 * Bits in the PCI Programming Interface register (some are per-channel).
62 * Bits 6-4 are defined as read-only in PCI 2.1 specification.
63 * Microsoft proposed to use these bits for independent channels
64 * enable/disable. This feature is enabled based on the value of bit 6.
65 */
66 #define PCIIDE_CHANSTATUS_EN 0x40
67 #define PCIIDE_CHAN_EN(chan) (0x20 >> (chan))
68 #define PCIIDE_INTERFACE_PCI(chan) (0x01 << (2 * (chan)))
69 #define PCIIDE_INTERFACE_SETTABLE(chan) (0x02 << (2 * (chan)))
70 #define PCIIDE_INTERFACE_BUS_MASTER_DMA 0x80
71
72 /*
73 * Compatibility address/IRQ definitions (some are per-channel).
74 */
75 #define PCIIDE_COMPAT_CMD_BASE(chan) ((chan) == 0 ? 0x1f0 : 0x170)
76 #define PCIIDE_COMPAT_CMD_SIZE 8
77 #define PCIIDE_COMPAT_CTL_BASE(chan) ((chan) == 0 ? 0x3f6 : 0x376)
78 #define PCIIDE_COMPAT_CTL_SIZE 1
79 #define PCIIDE_COMPAT_IRQ(chan) ((chan) == 0 ? 14 : 15)
80
81 #define PCIIDE_CHANNEL_NAME(chan) ((chan) == 0 ? "channel 0" : "channel 1")
82
83 /*
84 * definitions for IDE DMA
85 * XXX maybe this should go elsewhere
86 */
87
88 /* secondary channel registers offset */
89 #define IDEDMA_SCH_OFFSET 0x08
90 #define IDEDMA_NREGS 8
91
92 /* Bus master command register (per channel) */
93 #define IDEDMA_CMD(chan) (0x00 + IDEDMA_SCH_OFFSET * (chan))
94 #define IDEDMA_CMD_WRITE 0x08
95 #define IDEDMA_CMD_START 0x01
96
97 /* Bus master status register (per channel) */
98 #define IDEDMA_CTL(chan) (0x02 + IDEDMA_SCH_OFFSET * (chan))
99 #define IDEDMA_CTL_DRV_DMA(d) (0x20 << (d))
100 #define IDEDMA_CTL_INTR 0x04
101 #define IDEDMA_CTL_ERR 0x02
102 #define IDEDMA_CTL_ACT 0x01
103
104 /* Bus master table pointer register (per channel) */
105 #define IDEDMA_TBL(chan) (0x04 + IDEDMA_SCH_OFFSET * (chan))
106 #define IDEDMA_TBL_MASK 0xfffffffc
107 #define IDEDMA_TBL_ALIGN 0x00010000
108
109 /* bus master table descriptor */
110 struct idedma_table {
111 u_int32_t base_addr; /* physical base addr of memory region */
112 u_int32_t byte_count; /* memory region length */
113 #define IDEDMA_BYTE_COUNT_MASK 0x0000FFFF
114 #define IDEDMA_BYTE_COUNT_EOT 0x80000000
115 };
116
117 #define IDEDMA_BYTE_COUNT_MAX 0x00010000 /* Max I/O per table */
118 #define IDEDMA_BYTE_COUNT_ALIGN 0x00010000
119
120 /* Number of idedma table needed */
121 #define NIDEDMA_TABLES (MAXPHYS/PAGE_SIZE + 1)
122
123 #endif /* !_DEV_PCI_PCIIDEREG_H_ */