1 /* $OpenBSD: pciidevar.h,v 1.16 2004/10/17 19:00:46 grange Exp $ */
2 /* $NetBSD: pciidevar.h,v 1.6 2001/01/12 16:04:00 bouyer Exp $ */
3
4 /*
5 * Copyright (c) 1998 Christopher G. Demetriou. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Christopher G. Demetriou
18 * for the NetBSD Project.
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef _DEV_PCI_PCIIDEVAR_H_
35 #define _DEV_PCI_PCIIDEVAR_H_
36
37 /*
38 * PCI IDE driver exported software structures.
39 *
40 * Author: Christopher G. Demetriou, March 2, 1998.
41 */
42
43 #include <dev/ata/atavar.h>
44 #include <dev/ic/wdcreg.h>
45 #include <dev/ic/wdcvar.h>
46
47 /*
48 * While standard PCI IDE controllers only have 2 channels, it is
49 * common for PCI SATA controllers to have more. Here we define
50 * the maximum number of channels that any one PCI IDE device can
51 * have.
52 */
53 #define PCIIDE_MAX_CHANNELS 4
54
55 struct pciide_softc {
56 struct wdc_softc sc_wdcdev; /* common wdc definitions */
57 pci_chipset_tag_t sc_pc; /* PCI registers info */
58 pcitag_t sc_tag;
59 void *sc_pci_ih; /* PCI interrupt handle */
60 int sc_dma_ok; /* bus-master DMA info */
61 bus_space_tag_t sc_dma_iot;
62 bus_space_handle_t sc_dma_ioh;
63 bus_dma_tag_t sc_dmat;
64
65 /*
66 * Some controllers might have DMA restrictions other than
67 * the norm.
68 */
69 bus_size_t sc_dma_maxsegsz;
70 bus_size_t sc_dma_boundary;
71
72 /* Chip description */
73 const struct pciide_product_desc *sc_pp;
74 /* Chip revision */
75 int sc_rev;
76 /* common definitions */
77 struct channel_softc *wdc_chanarray[PCIIDE_MAX_CHANNELS];
78 /* internal bookkeeping */
79 struct pciide_channel { /* per-channel data */
80 struct channel_softc wdc_channel; /* generic part */
81 const char *name;
82 int hw_ok; /* hardware mapped & OK? */
83 int compat; /* is it compat? */
84 int dma_in_progress;
85 void *ih; /* compat or pci handle */
86 bus_space_handle_t ctl_baseioh; /* ctrl regs blk, native mode */
87 /* DMA tables and DMA map for xfer, for each drive */
88 struct pciide_dma_maps {
89 bus_dmamap_t dmamap_table;
90 struct idedma_table *dma_table;
91 bus_dmamap_t dmamap_xfer;
92 int dma_flags;
93 } dma_maps[2];
94 /*
95 * Some controllers require certain bits to
96 * always be set for proper operation of the
97 * controller. Set those bits here, if they're
98 * required.
99 */
100 uint8_t idedma_cmd;
101 } pciide_channels[PCIIDE_MAX_CHANNELS];
102
103 /* Chip-specific private data */
104 void *sc_cookie;
105
106 /* DMA registers access functions */
107 u_int8_t (*sc_dmacmd_read)(struct pciide_softc *, int);
108 void (*sc_dmacmd_write)(struct pciide_softc *, int, u_int8_t);
109 u_int8_t (*sc_dmactl_read)(struct pciide_softc *, int);
110 void (*sc_dmactl_write)(struct pciide_softc *, int, u_int8_t);
111 void (*sc_dmatbl_write)(struct pciide_softc *, int, u_int32_t);
112 };
113
114 #define PCIIDE_DMACMD_READ(sc, chan) \
115 (sc)->sc_dmacmd_read((sc), (chan))
116 #define PCIIDE_DMACMD_WRITE(sc, chan, val) \
117 (sc)->sc_dmacmd_write((sc), (chan), (val))
118 #define PCIIDE_DMACTL_READ(sc, chan) \
119 (sc)->sc_dmactl_read((sc), (chan))
120 #define PCIIDE_DMACTL_WRITE(sc, chan, val) \
121 (sc)->sc_dmactl_write((sc), (chan), (val))
122 #define PCIIDE_DMATBL_WRITE(sc, chan, val) \
123 (sc)->sc_dmatbl_write((sc), (chan), (val))
124
125 /*
126 * Functions defined by machine-dependent code.
127 */
128
129 /* Attach compat interrupt handler, returning handle or NULL if failed. */
130 #if !defined(pciide_machdep_compat_intr_establish)
131 void *pciide_machdep_compat_intr_establish(struct device *,
132 struct pci_attach_args *, int, int (*)(void *), void *);
133 void pciide_machdep_compat_intr_disestablish(pci_chipset_tag_t pc,
134 void *);
135 #endif
136
137 #endif /* !_DEV_PCI_PCIIDEVAR_H_ */