sc_wdcdev 65 dev/isa/wdc_isa.c struct wdc_softc sc_wdcdev;
sc_wdcdev 142 dev/isa/wdc_isa.c sc->sc_wdcdev.sc_dev.dv_xname);
sc_wdcdev 148 dev/isa/wdc_isa.c IPL_BIO, wdcintr, &sc->wdc_channel, sc->sc_wdcdev.sc_dev.dv_xname);
sc_wdcdev 154 dev/isa/wdc_isa.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA;
sc_wdcdev 155 dev/isa/wdc_isa.c sc->sc_wdcdev.dma_arg = sc;
sc_wdcdev 156 dev/isa/wdc_isa.c sc->sc_wdcdev.dma_init = wdc_isa_dma_init;
sc_wdcdev 157 dev/isa/wdc_isa.c sc->sc_wdcdev.dma_start = wdc_isa_dma_start;
sc_wdcdev 158 dev/isa/wdc_isa.c sc->sc_wdcdev.dma_finish = wdc_isa_dma_finish;
sc_wdcdev 162 dev/isa/wdc_isa.c sc->sc_wdcdev.sc_dev.dv_xname);
sc_wdcdev 165 dev/isa/wdc_isa.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_PREATA;
sc_wdcdev 166 dev/isa/wdc_isa.c if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & WDC_OPTIONS_32)
sc_wdcdev 167 dev/isa/wdc_isa.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA32;
sc_wdcdev 168 dev/isa/wdc_isa.c sc->sc_wdcdev.PIO_cap = 0;
sc_wdcdev 170 dev/isa/wdc_isa.c sc->sc_wdcdev.channels = &sc->wdc_chanptr;
sc_wdcdev 171 dev/isa/wdc_isa.c sc->sc_wdcdev.nchannels = 1;
sc_wdcdev 173 dev/isa/wdc_isa.c sc->wdc_channel.wdc = &sc->sc_wdcdev;
sc_wdcdev 178 dev/isa/wdc_isa.c sc->sc_wdcdev.sc_dev.dv_xname);
sc_wdcdev 192 dev/isa/wdc_isa.c sc->sc_wdcdev.sc_dev.dv_xname, sc->sc_drq);
sc_wdcdev 193 dev/isa/wdc_isa.c sc->sc_wdcdev.cap &= ~WDC_CAPABILITY_DMA;
sc_wdcdev 57 dev/isa/wdc_isapnp.c struct wdc_softc sc_wdcdev;
sc_wdcdev 126 dev/isa/wdc_isapnp.c sc->sc_wdcdev.sc_dev.dv_xname);
sc_wdcdev 138 dev/isa/wdc_isapnp.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32;
sc_wdcdev 139 dev/isa/wdc_isapnp.c sc->sc_wdcdev.PIO_cap = 0;
sc_wdcdev 141 dev/isa/wdc_isapnp.c sc->sc_wdcdev.channels = &sc->wdc_chanptr;
sc_wdcdev 142 dev/isa/wdc_isapnp.c sc->sc_wdcdev.nchannels = 1;
sc_wdcdev 144 dev/isa/wdc_isapnp.c sc->wdc_channel.wdc = &sc->sc_wdcdev;
sc_wdcdev 166 dev/isa/wdc_isapnp.c sc->sc_wdcdev.sc_dev.dv_xname, sc->sc_drq);
sc_wdcdev 167 dev/isa/wdc_isapnp.c sc->sc_wdcdev.cap &= ~WDC_CAPABILITY_DMA;
sc_wdcdev 1302 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
sc_wdcdev 1311 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
sc_wdcdev 1335 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname);
sc_wdcdev 1341 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname);
sc_wdcdev 1344 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname,
sc_wdcdev 1348 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname);
sc_wdcdev 1360 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cp->name,
sc_wdcdev 1366 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
sc_wdcdev 1373 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cp->name,
sc_wdcdev 1379 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
sc_wdcdev 1391 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
sc_wdcdev 1449 dev/pci/pciide.c sc->sc_wdcdev.dma_arg = sc;
sc_wdcdev 1450 dev/pci/pciide.c sc->sc_wdcdev.dma_init = pciide_dma_init;
sc_wdcdev 1451 dev/pci/pciide.c sc->sc_wdcdev.dma_start = pciide_dma_start;
sc_wdcdev 1452 dev/pci/pciide.c sc->sc_wdcdev.dma_finish = pciide_dma_finish;
sc_wdcdev 1517 dev/pci/pciide.c for (i = 0; i < sc->sc_wdcdev.nchannels; i++) {
sc_wdcdev 1621 dev/pci/pciide.c "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname,
sc_wdcdev 1631 dev/pci/pciide.c "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname,
sc_wdcdev 1645 dev/pci/pciide.c "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname,
sc_wdcdev 1654 dev/pci/pciide.c "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname,
sc_wdcdev 1666 dev/pci/pciide.c "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname,
sc_wdcdev 1691 dev/pci/pciide.c "drive %d, error=%d\n", sc->sc_wdcdev.sc_dev.dv_xname,
sc_wdcdev 1803 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, channel, drive, status);
sc_wdcdev 1809 dev/pci/pciide.c "status=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname, channel,
sc_wdcdev 1843 dev/pci/pciide.c cp->wdc_channel.wdc = &sc->sc_wdcdev;
sc_wdcdev 1849 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
sc_wdcdev 1891 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
sc_wdcdev 1913 dev/pci/pciide.c cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_wdcdev.sc_dev,
sc_wdcdev 1917 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
sc_wdcdev 1975 dev/pci/pciide.c (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags &
sc_wdcdev 1989 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK;
sc_wdcdev 1990 dev/pci/pciide.c sc->sc_wdcdev.irqack = pciide_irqack;
sc_wdcdev 1992 dev/pci/pciide.c sc->sc_wdcdev.PIO_cap = 0;
sc_wdcdev 1993 dev/pci/pciide.c sc->sc_wdcdev.DMA_cap = 0;
sc_wdcdev 1994 dev/pci/pciide.c sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc_wdcdev 1995 dev/pci/pciide.c sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
sc_wdcdev 1996 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16;
sc_wdcdev 1998 dev/pci/pciide.c pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
sc_wdcdev 2000 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
sc_wdcdev 2042 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cp->name,
sc_wdcdev 2066 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
sc_wdcdev 2080 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname,
sc_wdcdev 2085 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname,
sc_wdcdev 2116 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA |
sc_wdcdev 2118 dev/pci/pciide.c sc->sc_wdcdev.irqack = pciide_irqack;
sc_wdcdev 2120 dev/pci/pciide.c sc->sc_wdcdev.PIO_cap = 4;
sc_wdcdev 2121 dev/pci/pciide.c sc->sc_wdcdev.DMA_cap = 2;
sc_wdcdev 2122 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 6;
sc_wdcdev 2124 dev/pci/pciide.c sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc_wdcdev 2125 dev/pci/pciide.c sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
sc_wdcdev 2126 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
sc_wdcdev 2128 dev/pci/pciide.c sc->sc_wdcdev.set_modes = sata_setup_channel;
sc_wdcdev 2130 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
sc_wdcdev 2191 dev/pci/pciide.c if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) {
sc_wdcdev 2232 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
sc_wdcdev 2235 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK;
sc_wdcdev 2236 dev/pci/pciide.c sc->sc_wdcdev.irqack = pciide_irqack;
sc_wdcdev 2257 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
sc_wdcdev 2261 dev/pci/pciide.c sc->sc_wdcdev.PIO_cap = 4;
sc_wdcdev 2262 dev/pci/pciide.c sc->sc_wdcdev.DMA_cap = 2;
sc_wdcdev 2266 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 4;
sc_wdcdev 2281 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 5;
sc_wdcdev 2284 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 2;
sc_wdcdev 2290 dev/pci/pciide.c sc->sc_wdcdev.set_modes = piix_setup_channel;
sc_wdcdev 2292 dev/pci/pciide.c sc->sc_wdcdev.set_modes = piix3_4_setup_channel;
sc_wdcdev 2294 dev/pci/pciide.c sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc_wdcdev 2295 dev/pci/pciide.c sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
sc_wdcdev 2297 dev/pci/pciide.c pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
sc_wdcdev 2301 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
sc_wdcdev 2311 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
sc_wdcdev 2329 dev/pci/pciide.c sc->sc_wdcdev.set_modes(&cp->wdc_channel);
sc_wdcdev 2351 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA |
sc_wdcdev 2353 dev/pci/pciide.c sc->sc_wdcdev.irqack = pciide_irqack;
sc_wdcdev 2354 dev/pci/pciide.c sc->sc_wdcdev.DMA_cap = 2;
sc_wdcdev 2355 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 6;
sc_wdcdev 2357 dev/pci/pciide.c sc->sc_wdcdev.PIO_cap = 4;
sc_wdcdev 2359 dev/pci/pciide.c sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc_wdcdev 2360 dev/pci/pciide.c sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
sc_wdcdev 2361 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
sc_wdcdev 2363 dev/pci/pciide.c sc->sc_wdcdev.set_modes = sata_setup_channel;
sc_wdcdev 2428 dev/pci/pciide.c pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
sc_wdcdev 2430 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
sc_wdcdev 2442 dev/pci/pciide.c sc->sc_wdcdev.set_modes(&cp->wdc_channel);
sc_wdcdev 2799 dev/pci/pciide.c sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
sc_wdcdev 2802 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
sc_wdcdev 2803 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
sc_wdcdev 2804 dev/pci/pciide.c sc->sc_wdcdev.irqack = pciide_irqack;
sc_wdcdev 2806 dev/pci/pciide.c sc->sc_wdcdev.PIO_cap = 4;
sc_wdcdev 2807 dev/pci/pciide.c sc->sc_wdcdev.DMA_cap = 2;
sc_wdcdev 2810 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 6;
sc_wdcdev 2814 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 5;
sc_wdcdev 2817 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 4;
sc_wdcdev 2820 dev/pci/pciide.c sc->sc_wdcdev.set_modes = amd756_setup_channel;
sc_wdcdev 2821 dev/pci/pciide.c sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc_wdcdev 2822 dev/pci/pciide.c sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
sc_wdcdev 2825 dev/pci/pciide.c pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
sc_wdcdev 2827 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
sc_wdcdev 2834 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
sc_wdcdev 2906 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname,
sc_wdcdev 2930 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname,
sc_wdcdev 2995 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 6;
sc_wdcdev 3020 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 2;
sc_wdcdev 3023 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 0;
sc_wdcdev 3029 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 4;
sc_wdcdev 3032 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 2;
sc_wdcdev 3039 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 5;
sc_wdcdev 3042 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 4;
sc_wdcdev 3048 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 5;
sc_wdcdev 3054 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 6;
sc_wdcdev 3058 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 0;
sc_wdcdev 3064 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
sc_wdcdev 3067 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK;
sc_wdcdev 3068 dev/pci/pciide.c sc->sc_wdcdev.irqack = pciide_irqack;
sc_wdcdev 3069 dev/pci/pciide.c if (sc->sc_wdcdev.UDMA_cap > 0)
sc_wdcdev 3070 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
sc_wdcdev 3072 dev/pci/pciide.c sc->sc_wdcdev.PIO_cap = 4;
sc_wdcdev 3073 dev/pci/pciide.c sc->sc_wdcdev.DMA_cap = 2;
sc_wdcdev 3074 dev/pci/pciide.c sc->sc_wdcdev.set_modes = apollo_setup_channel;
sc_wdcdev 3075 dev/pci/pciide.c sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc_wdcdev 3076 dev/pci/pciide.c sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
sc_wdcdev 3078 dev/pci/pciide.c pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
sc_wdcdev 3088 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
sc_wdcdev 3096 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
sc_wdcdev 3180 dev/pci/pciide.c if (sc->sc_wdcdev.UDMA_cap == 6) {
sc_wdcdev 3183 dev/pci/pciide.c } else if (sc->sc_wdcdev.UDMA_cap == 5) {
sc_wdcdev 3187 dev/pci/pciide.c } else if (sc->sc_wdcdev.UDMA_cap == 4) {
sc_wdcdev 3264 dev/pci/pciide.c cp->wdc_channel.wdc = &sc->sc_wdcdev;
sc_wdcdev 3288 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
sc_wdcdev 3299 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
sc_wdcdev 3333 dev/pci/pciide.c for (i = 0; i < sc->sc_wdcdev.nchannels; i++) {
sc_wdcdev 3345 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, i);
sc_wdcdev 3363 dev/pci/pciide.c sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc_wdcdev 3364 dev/pci/pciide.c sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
sc_wdcdev 3365 dev/pci/pciide.c sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16;
sc_wdcdev 3367 dev/pci/pciide.c pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
sc_wdcdev 3369 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
sc_wdcdev 3399 dev/pci/pciide.c sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
sc_wdcdev 3402 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK;
sc_wdcdev 3405 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
sc_wdcdev 3406 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 5;
sc_wdcdev 3407 dev/pci/pciide.c sc->sc_wdcdev.irqack = cmd646_9_irqack;
sc_wdcdev 3410 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
sc_wdcdev 3411 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 4;
sc_wdcdev 3412 dev/pci/pciide.c sc->sc_wdcdev.irqack = cmd646_9_irqack;
sc_wdcdev 3416 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
sc_wdcdev 3417 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 2;
sc_wdcdev 3425 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
sc_wdcdev 3426 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 2;
sc_wdcdev 3434 dev/pci/pciide.c sc->sc_wdcdev.irqack = cmd646_9_irqack;
sc_wdcdev 3437 dev/pci/pciide.c sc->sc_wdcdev.irqack = pciide_irqack;
sc_wdcdev 3441 dev/pci/pciide.c sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc_wdcdev 3442 dev/pci/pciide.c sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
sc_wdcdev 3443 dev/pci/pciide.c sc->sc_wdcdev.PIO_cap = 4;
sc_wdcdev 3444 dev/pci/pciide.c sc->sc_wdcdev.DMA_cap = 2;
sc_wdcdev 3445 dev/pci/pciide.c sc->sc_wdcdev.set_modes = cmd0643_9_setup_channel;
sc_wdcdev 3447 dev/pci/pciide.c pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
sc_wdcdev 3453 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
sc_wdcdev 3505 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname,
sc_wdcdev 3511 dev/pci/pciide.c else if (sc->sc_wdcdev.UDMA_cap > 2)
sc_wdcdev 3528 dev/pci/pciide.c if (sc->sc_wdcdev.cap & WDC_CAPABILITY_UDMA) {
sc_wdcdev 3591 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname);
sc_wdcdev 3594 dev/pci/pciide.c sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
sc_wdcdev 3597 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK;
sc_wdcdev 3598 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
sc_wdcdev 3599 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 6;
sc_wdcdev 3600 dev/pci/pciide.c sc->sc_wdcdev.irqack = pciide_irqack;
sc_wdcdev 3603 dev/pci/pciide.c sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc_wdcdev 3604 dev/pci/pciide.c sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
sc_wdcdev 3605 dev/pci/pciide.c sc->sc_wdcdev.PIO_cap = 4;
sc_wdcdev 3606 dev/pci/pciide.c sc->sc_wdcdev.DMA_cap = 2;
sc_wdcdev 3607 dev/pci/pciide.c sc->sc_wdcdev.set_modes = cmd680_setup_channel;
sc_wdcdev 3613 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
sc_wdcdev 3645 dev/pci/pciide.c cp->wdc_channel.wdc = &sc->sc_wdcdev;
sc_wdcdev 3652 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
sc_wdcdev 3662 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cp->name,
sc_wdcdev 3853 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32;
sc_wdcdev 3854 dev/pci/pciide.c sc->sc_wdcdev.PIO_cap = 4;
sc_wdcdev 3856 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
sc_wdcdev 3857 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
sc_wdcdev 3858 dev/pci/pciide.c sc->sc_wdcdev.irqack = pciide_irqack;
sc_wdcdev 3859 dev/pci/pciide.c sc->sc_wdcdev.DMA_cap = 2;
sc_wdcdev 3860 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 6;
sc_wdcdev 3862 dev/pci/pciide.c sc->sc_wdcdev.set_modes = sii3112_setup_channel;
sc_wdcdev 3865 dev/pci/pciide.c sc->sc_wdcdev.drv_probe = sii3112_drv_probe;
sc_wdcdev 3867 dev/pci/pciide.c sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc_wdcdev 3868 dev/pci/pciide.c sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
sc_wdcdev 3882 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
sc_wdcdev 3890 dev/pci/pciide.c sc->sc_wdcdev.set_modes(&cp->wdc_channel);
sc_wdcdev 3983 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus,
sc_wdcdev 3994 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel);
sc_wdcdev 3999 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel);
sc_wdcdev 4033 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel,
sc_wdcdev 4048 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel);
sc_wdcdev 4062 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus);
sc_wdcdev 4134 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32;
sc_wdcdev 4135 dev/pci/pciide.c sc->sc_wdcdev.PIO_cap = 4;
sc_wdcdev 4137 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
sc_wdcdev 4138 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
sc_wdcdev 4139 dev/pci/pciide.c sc->sc_wdcdev.irqack = pciide_irqack;
sc_wdcdev 4140 dev/pci/pciide.c sc->sc_wdcdev.DMA_cap = 2;
sc_wdcdev 4141 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 6;
sc_wdcdev 4143 dev/pci/pciide.c sc->sc_wdcdev.set_modes = sii3112_setup_channel;
sc_wdcdev 4146 dev/pci/pciide.c sc->sc_wdcdev.drv_probe = sii3112_drv_probe;
sc_wdcdev 4148 dev/pci/pciide.c sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc_wdcdev 4149 dev/pci/pciide.c sc->sc_wdcdev.nchannels = 4;
sc_wdcdev 4154 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname);
sc_wdcdev 4161 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname);
sc_wdcdev 4164 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname,
sc_wdcdev 4168 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname);
sc_wdcdev 4175 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
sc_wdcdev 4182 dev/pci/pciide.c sc->sc_wdcdev.set_modes(&cp->wdc_channel);
sc_wdcdev 4194 dev/pci/pciide.c sc->sc_wdcdev.dma_arg = sc;
sc_wdcdev 4195 dev/pci/pciide.c sc->sc_wdcdev.dma_init = pciide_dma_init;
sc_wdcdev 4196 dev/pci/pciide.c sc->sc_wdcdev.dma_start = pciide_dma_start;
sc_wdcdev 4197 dev/pci/pciide.c sc->sc_wdcdev.dma_finish = pciide_dma_finish;
sc_wdcdev 4259 dev/pci/pciide.c cp->wdc_channel.wdc = &sc->sc_wdcdev;
sc_wdcdev 4265 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
sc_wdcdev 4289 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
sc_wdcdev 4298 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
sc_wdcdev 4310 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
sc_wdcdev 4442 dev/pci/pciide.c sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
sc_wdcdev 4445 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK;
sc_wdcdev 4446 dev/pci/pciide.c sc->sc_wdcdev.irqack = pciide_irqack;
sc_wdcdev 4448 dev/pci/pciide.c sc->sc_wdcdev.PIO_cap = 4;
sc_wdcdev 4449 dev/pci/pciide.c sc->sc_wdcdev.DMA_cap = 2;
sc_wdcdev 4450 dev/pci/pciide.c sc->sc_wdcdev.set_modes = cy693_setup_channel;
sc_wdcdev 4452 dev/pci/pciide.c sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc_wdcdev 4453 dev/pci/pciide.c sc->sc_wdcdev.nchannels = 1;
sc_wdcdev 4460 dev/pci/pciide.c cp->wdc_channel.wdc = &sc->sc_wdcdev;
sc_wdcdev 4685 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap =
sc_wdcdev 4702 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap =
sc_wdcdev 4706 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap =
sc_wdcdev 4712 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap =
sc_wdcdev 4719 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 2;
sc_wdcdev 4722 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 0;
sc_wdcdev 4730 dev/pci/pciide.c sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
sc_wdcdev 4733 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK;
sc_wdcdev 4734 dev/pci/pciide.c sc->sc_wdcdev.irqack = pciide_irqack;
sc_wdcdev 4736 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
sc_wdcdev 4739 dev/pci/pciide.c sc->sc_wdcdev.PIO_cap = 4;
sc_wdcdev 4740 dev/pci/pciide.c sc->sc_wdcdev.DMA_cap = 2;
sc_wdcdev 4742 dev/pci/pciide.c sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc_wdcdev 4743 dev/pci/pciide.c sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
sc_wdcdev 4748 dev/pci/pciide.c sc->sc_wdcdev.set_modes = sis_setup_channel;
sc_wdcdev 4755 dev/pci/pciide.c sc->sc_wdcdev.set_modes = sis_setup_channel;
sc_wdcdev 4760 dev/pci/pciide.c sc->sc_wdcdev.set_modes = sis96x_setup_channel;
sc_wdcdev 4768 dev/pci/pciide.c pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
sc_wdcdev 4770 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
sc_wdcdev 4777 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
sc_wdcdev 4801 dev/pci/pciide.c sc->sc_wdcdev.set_modes(&cp->wdc_channel);
sc_wdcdev 4985 dev/pci/pciide.c sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16;
sc_wdcdev 4988 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK;
sc_wdcdev 4989 dev/pci/pciide.c sc->sc_wdcdev.irqack = natsemi_irqack;
sc_wdcdev 5002 dev/pci/pciide.c sc->sc_wdcdev.PIO_cap = 4;
sc_wdcdev 5003 dev/pci/pciide.c sc->sc_wdcdev.DMA_cap = 2;
sc_wdcdev 5004 dev/pci/pciide.c sc->sc_wdcdev.set_modes = natsemi_setup_channel;
sc_wdcdev 5005 dev/pci/pciide.c sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc_wdcdev 5006 dev/pci/pciide.c sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
sc_wdcdev 5011 dev/pci/pciide.c pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
sc_wdcdev 5021 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
sc_wdcdev 5133 dev/pci/pciide.c for (i = 0; i < sc->sc_wdcdev.nchannels; i++) {
sc_wdcdev 5170 dev/pci/pciide.c sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
sc_wdcdev 5173 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
sc_wdcdev 5174 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
sc_wdcdev 5175 dev/pci/pciide.c sc->sc_wdcdev.irqack = pciide_irqack;
sc_wdcdev 5177 dev/pci/pciide.c sc->sc_wdcdev.PIO_cap = 4;
sc_wdcdev 5178 dev/pci/pciide.c sc->sc_wdcdev.DMA_cap = 2;
sc_wdcdev 5179 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 2;
sc_wdcdev 5181 dev/pci/pciide.c sc->sc_wdcdev.set_modes = ns_scx200_setup_channel;
sc_wdcdev 5182 dev/pci/pciide.c sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc_wdcdev 5183 dev/pci/pciide.c sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
sc_wdcdev 5204 dev/pci/pciide.c sc->sc_wdcdev.quirks = WDC_QUIRK_NOSHORTDMA;
sc_wdcdev 5206 dev/pci/pciide.c pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
sc_wdcdev 5208 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
sc_wdcdev 5221 dev/pci/pciide.c sc->sc_wdcdev.set_modes(&cp->wdc_channel);
sc_wdcdev 5260 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, channel, drive,
sc_wdcdev 5296 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, channel, drive,
sc_wdcdev 5325 dev/pci/pciide.c sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
sc_wdcdev 5329 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA;
sc_wdcdev 5331 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA;
sc_wdcdev 5333 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 5;
sc_wdcdev 5335 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 4;
sc_wdcdev 5337 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 2;
sc_wdcdev 5339 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
sc_wdcdev 5340 dev/pci/pciide.c sc->sc_wdcdev.irqack = pciide_irqack;
sc_wdcdev 5343 dev/pci/pciide.c sc->sc_wdcdev.PIO_cap = 4;
sc_wdcdev 5344 dev/pci/pciide.c sc->sc_wdcdev.DMA_cap = 2;
sc_wdcdev 5345 dev/pci/pciide.c sc->sc_wdcdev.set_modes = acer_setup_channel;
sc_wdcdev 5346 dev/pci/pciide.c sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc_wdcdev 5347 dev/pci/pciide.c sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
sc_wdcdev 5369 dev/pci/pciide.c pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
sc_wdcdev 5377 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
sc_wdcdev 5383 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
sc_wdcdev 5430 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel),
sc_wdcdev 5517 dev/pci/pciide.c for (i = 0; i < sc->sc_wdcdev.nchannels; i++) {
sc_wdcdev 5527 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, i);
sc_wdcdev 5567 dev/pci/pciide.c sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
sc_wdcdev 5570 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
sc_wdcdev 5571 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
sc_wdcdev 5572 dev/pci/pciide.c sc->sc_wdcdev.irqack = pciide_irqack;
sc_wdcdev 5574 dev/pci/pciide.c sc->sc_wdcdev.PIO_cap = 4;
sc_wdcdev 5575 dev/pci/pciide.c sc->sc_wdcdev.DMA_cap = 2;
sc_wdcdev 5577 dev/pci/pciide.c sc->sc_wdcdev.set_modes = hpt_setup_channel;
sc_wdcdev 5578 dev/pci/pciide.c sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc_wdcdev 5581 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 4;
sc_wdcdev 5593 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, pa->pa_function);
sc_wdcdev 5596 dev/pci/pciide.c sc->sc_wdcdev.nchannels = 1;
sc_wdcdev 5598 dev/pci/pciide.c sc->sc_wdcdev.nchannels = 2;
sc_wdcdev 5603 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 6;
sc_wdcdev 5606 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 6;
sc_wdcdev 5608 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 5;
sc_wdcdev 5611 dev/pci/pciide.c for (i = 0; i < sc->sc_wdcdev.nchannels; i++) {
sc_wdcdev 5613 dev/pci/pciide.c if (sc->sc_wdcdev.nchannels > 1) {
sc_wdcdev 5618 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
sc_wdcdev 5728 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname);
sc_wdcdev 5749 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname,
sc_wdcdev 5774 dev/pci/pciide.c "(BIOS 0x%08x)\n", sc->sc_wdcdev.sc_dev.dv_xname,
sc_wdcdev 5795 dev/pci/pciide.c for (i = 0; i < sc->sc_wdcdev.nchannels; i++) {
sc_wdcdev 5806 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, i);
sc_wdcdev 5901 dev/pci/pciide.c sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
sc_wdcdev 5905 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_NO_ATAPI_DMA;
sc_wdcdev 5907 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
sc_wdcdev 5908 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
sc_wdcdev 5909 dev/pci/pciide.c sc->sc_wdcdev.irqack = pciide_irqack;
sc_wdcdev 5911 dev/pci/pciide.c sc->sc_wdcdev.PIO_cap = 4;
sc_wdcdev 5912 dev/pci/pciide.c sc->sc_wdcdev.DMA_cap = 2;
sc_wdcdev 5914 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 6;
sc_wdcdev 5916 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 5;
sc_wdcdev 5918 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 4;
sc_wdcdev 5920 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 2;
sc_wdcdev 5921 dev/pci/pciide.c sc->sc_wdcdev.set_modes = PDC_IS_268(sc) ?
sc_wdcdev 5923 dev/pci/pciide.c sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc_wdcdev 5924 dev/pci/pciide.c sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
sc_wdcdev 5927 dev/pci/pciide.c sc->sc_wdcdev.dma_start = pdc20262_dma_start;
sc_wdcdev 5928 dev/pci/pciide.c sc->sc_wdcdev.dma_finish = pdc20262_dma_finish;
sc_wdcdev 5931 dev/pci/pciide.c pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
sc_wdcdev 5940 dev/pci/pciide.c channel < sc->sc_wdcdev.nchannels;
sc_wdcdev 5989 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
sc_wdcdev 5996 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
sc_wdcdev 6046 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname,
sc_wdcdev 6062 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, channel),
sc_wdcdev 6090 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, channel,
sc_wdcdev 6146 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname,
sc_wdcdev 6189 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname,
sc_wdcdev 6217 dev/pci/pciide.c for (i = 0; i < sc->sc_wdcdev.nchannels; i++) {
sc_wdcdev 6227 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, i, scr);
sc_wdcdev 6245 dev/pci/pciide.c for (i = 0; i < sc->sc_wdcdev.nchannels; i++) {
sc_wdcdev 6277 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, i);
sc_wdcdev 6367 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname);
sc_wdcdev 6382 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname);
sc_wdcdev 6416 dev/pci/pciide.c sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16;
sc_wdcdev 6417 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
sc_wdcdev 6418 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
sc_wdcdev 6419 dev/pci/pciide.c sc->sc_wdcdev.irqack = pdc203xx_irqack;
sc_wdcdev 6420 dev/pci/pciide.c sc->sc_wdcdev.PIO_cap = 4;
sc_wdcdev 6421 dev/pci/pciide.c sc->sc_wdcdev.DMA_cap = 2;
sc_wdcdev 6422 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 6;
sc_wdcdev 6423 dev/pci/pciide.c sc->sc_wdcdev.set_modes = pdc203xx_setup_channel;
sc_wdcdev 6424 dev/pci/pciide.c sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc_wdcdev 6437 dev/pci/pciide.c sc->sc_wdcdev.nchannels =
sc_wdcdev 6449 dev/pci/pciide.c sc->sc_wdcdev.nchannels = PDC40718_NCHANNELS;
sc_wdcdev 6451 dev/pci/pciide.c sc->sc_wdcdev.reset = pdc205xx_do_reset;
sc_wdcdev 6452 dev/pci/pciide.c sc->sc_wdcdev.drv_probe = pdc205xx_drv_probe;
sc_wdcdev 6460 dev/pci/pciide.c sc->sc_wdcdev.nchannels = PDC20575_NCHANNELS;
sc_wdcdev 6462 dev/pci/pciide.c sc->sc_wdcdev.reset = pdc205xx_do_reset;
sc_wdcdev 6463 dev/pci/pciide.c sc->sc_wdcdev.drv_probe = pdc205xx_drv_probe;
sc_wdcdev 6468 dev/pci/pciide.c sc->sc_wdcdev.dma_arg = sc;
sc_wdcdev 6469 dev/pci/pciide.c sc->sc_wdcdev.dma_init = pciide_dma_init;
sc_wdcdev 6470 dev/pci/pciide.c sc->sc_wdcdev.dma_start = pdc203xx_dma_start;
sc_wdcdev 6471 dev/pci/pciide.c sc->sc_wdcdev.dma_finish = pdc203xx_dma_finish;
sc_wdcdev 6473 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels;
sc_wdcdev 6481 dev/pci/pciide.c cp->wdc_channel.wdc = &sc->sc_wdcdev;
sc_wdcdev 6487 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, channel);
sc_wdcdev 6499 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname,
sc_wdcdev 6509 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname,
sc_wdcdev 6535 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, channel);
sc_wdcdev 6543 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, channel);
sc_wdcdev 6560 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname,
sc_wdcdev 6599 dev/pci/pciide.c for (i = 0; i < sc->sc_wdcdev.nchannels; i++) {
sc_wdcdev 6606 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname,
sc_wdcdev 6633 dev/pci/pciide.c for (i = 0; i < sc->sc_wdcdev.nchannels; i++) {
sc_wdcdev 6640 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname,
sc_wdcdev 6804 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel);
sc_wdcdev 6809 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel);
sc_wdcdev 6823 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel,
sc_wdcdev 6838 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel);
sc_wdcdev 6853 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus);
sc_wdcdev 6933 dev/pci/pciide.c sc->sc_wdcdev.cap = 0;
sc_wdcdev 6935 dev/pci/pciide.c sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32;
sc_wdcdev 6939 dev/pci/pciide.c sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_MODE;
sc_wdcdev 6940 dev/pci/pciide.c sc->sc_wdcdev.PIO_cap = 4;
sc_wdcdev 6942 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK;
sc_wdcdev 6943 dev/pci/pciide.c sc->sc_wdcdev.irqack = pciide_irqack;
sc_wdcdev 6944 dev/pci/pciide.c sc->sc_wdcdev.DMA_cap = 2;
sc_wdcdev 6946 dev/pci/pciide.c sc->sc_wdcdev.set_modes = opti_setup_channel;
sc_wdcdev 6948 dev/pci/pciide.c sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc_wdcdev 6949 dev/pci/pciide.c sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
sc_wdcdev 6956 dev/pci/pciide.c pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
sc_wdcdev 6958 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
sc_wdcdev 6965 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
sc_wdcdev 7094 dev/pci/pciide.c sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
sc_wdcdev 7098 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
sc_wdcdev 7099 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
sc_wdcdev 7100 dev/pci/pciide.c sc->sc_wdcdev.irqack = pciide_irqack;
sc_wdcdev 7102 dev/pci/pciide.c sc->sc_wdcdev.PIO_cap = 4;
sc_wdcdev 7103 dev/pci/pciide.c sc->sc_wdcdev.DMA_cap = 2;
sc_wdcdev 7106 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 2;
sc_wdcdev 7110 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 4;
sc_wdcdev 7112 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 5;
sc_wdcdev 7115 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 4;
sc_wdcdev 7118 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 5;
sc_wdcdev 7122 dev/pci/pciide.c sc->sc_wdcdev.set_modes = serverworks_setup_channel;
sc_wdcdev 7123 dev/pci/pciide.c sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc_wdcdev 7124 dev/pci/pciide.c sc->sc_wdcdev.nchannels =
sc_wdcdev 7127 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
sc_wdcdev 7194 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname,
sc_wdcdev 7237 dev/pci/pciide.c for (i = 0; i < sc->sc_wdcdev.nchannels; i++) {
sc_wdcdev 7248 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, i);
sc_wdcdev 7291 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA |
sc_wdcdev 7293 dev/pci/pciide.c sc->sc_wdcdev.irqack = pciide_irqack;
sc_wdcdev 7295 dev/pci/pciide.c sc->sc_wdcdev.PIO_cap = 4;
sc_wdcdev 7296 dev/pci/pciide.c sc->sc_wdcdev.DMA_cap = 2;
sc_wdcdev 7297 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 6;
sc_wdcdev 7299 dev/pci/pciide.c sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc_wdcdev 7300 dev/pci/pciide.c sc->sc_wdcdev.nchannels = 4;
sc_wdcdev 7301 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
sc_wdcdev 7303 dev/pci/pciide.c sc->sc_wdcdev.set_modes = sata_setup_channel;
sc_wdcdev 7306 dev/pci/pciide.c sc->sc_wdcdev.drv_probe = svwsata_drv_probe;
sc_wdcdev 7311 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname);
sc_wdcdev 7316 dev/pci/pciide.c pciide_pci_intr, sc, sc->sc_wdcdev.sc_dev.dv_xname);
sc_wdcdev 7319 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname,
sc_wdcdev 7323 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname);
sc_wdcdev 7330 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
sc_wdcdev 7344 dev/pci/pciide.c sc->sc_wdcdev.dma_arg = sc;
sc_wdcdev 7345 dev/pci/pciide.c sc->sc_wdcdev.dma_init = pciide_dma_init;
sc_wdcdev 7346 dev/pci/pciide.c sc->sc_wdcdev.dma_start = pciide_dma_start;
sc_wdcdev 7347 dev/pci/pciide.c sc->sc_wdcdev.dma_finish = pciide_dma_finish;
sc_wdcdev 7413 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
sc_wdcdev 7420 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
sc_wdcdev 7469 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus,
sc_wdcdev 7481 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel);
sc_wdcdev 7486 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel);
sc_wdcdev 7520 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel,
sc_wdcdev 7535 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel);
sc_wdcdev 7549 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus);
sc_wdcdev 7614 dev/pci/pciide.c sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
sc_wdcdev 7618 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
sc_wdcdev 7619 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
sc_wdcdev 7620 dev/pci/pciide.c sc->sc_wdcdev.irqack = pciide_irqack;
sc_wdcdev 7622 dev/pci/pciide.c sc->sc_wdcdev.PIO_cap = 4;
sc_wdcdev 7623 dev/pci/pciide.c sc->sc_wdcdev.DMA_cap = 2;
sc_wdcdev 7626 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 2;
sc_wdcdev 7630 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 4;
sc_wdcdev 7634 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 6;
sc_wdcdev 7638 dev/pci/pciide.c sc->sc_wdcdev.set_modes = acard_setup_channel;
sc_wdcdev 7639 dev/pci/pciide.c sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc_wdcdev 7640 dev/pci/pciide.c sc->sc_wdcdev.nchannels = 2;
sc_wdcdev 7642 dev/pci/pciide.c for (i = 0; i < sc->sc_wdcdev.nchannels; i++) {
sc_wdcdev 7779 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, conf), DEBUG_PROBE);
sc_wdcdev 7784 dev/pci/pciide.c sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
sc_wdcdev 7787 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
sc_wdcdev 7788 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
sc_wdcdev 7789 dev/pci/pciide.c sc->sc_wdcdev.irqack = pciide_irqack;
sc_wdcdev 7791 dev/pci/pciide.c sc->sc_wdcdev.PIO_cap = 4;
sc_wdcdev 7792 dev/pci/pciide.c sc->sc_wdcdev.DMA_cap = 2;
sc_wdcdev 7795 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 5;
sc_wdcdev 7798 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 6;
sc_wdcdev 7800 dev/pci/pciide.c sc->sc_wdcdev.set_modes = nforce_setup_channel;
sc_wdcdev 7801 dev/pci/pciide.c sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc_wdcdev 7802 dev/pci/pciide.c sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
sc_wdcdev 7804 dev/pci/pciide.c pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
sc_wdcdev 7806 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
sc_wdcdev 7814 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
sc_wdcdev 7834 dev/pci/pciide.c sc->sc_wdcdev.set_modes(&cp->wdc_channel);
sc_wdcdev 7837 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, conf), DEBUG_PROBE);
sc_wdcdev 7857 dev/pci/pciide.c "piotim=0x%x, udmatim=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname,
sc_wdcdev 7924 dev/pci/pciide.c "piotim=0x%x, udmatim=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname,
sc_wdcdev 7942 dev/pci/pciide.c for (i = 0; i < sc->sc_wdcdev.nchannels; i++) {
sc_wdcdev 7958 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, i);
sc_wdcdev 7987 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
sc_wdcdev 7989 dev/pci/pciide.c sc->sc_wdcdev.PIO_cap = 4;
sc_wdcdev 7991 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
sc_wdcdev 7992 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
sc_wdcdev 7993 dev/pci/pciide.c sc->sc_wdcdev.irqack = pciide_irqack;
sc_wdcdev 7994 dev/pci/pciide.c sc->sc_wdcdev.DMA_cap = 2;
sc_wdcdev 7995 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 6;
sc_wdcdev 7997 dev/pci/pciide.c sc->sc_wdcdev.set_modes = sata_setup_channel;
sc_wdcdev 7999 dev/pci/pciide.c sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc_wdcdev 8000 dev/pci/pciide.c sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
sc_wdcdev 8004 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
sc_wdcdev 8035 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cfg & IT_CFG_MASK,
sc_wdcdev 8041 dev/pci/pciide.c sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
sc_wdcdev 8044 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
sc_wdcdev 8045 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
sc_wdcdev 8046 dev/pci/pciide.c sc->sc_wdcdev.irqack = pciide_irqack;
sc_wdcdev 8048 dev/pci/pciide.c sc->sc_wdcdev.PIO_cap = 4;
sc_wdcdev 8049 dev/pci/pciide.c sc->sc_wdcdev.DMA_cap = 2;
sc_wdcdev 8050 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 6;
sc_wdcdev 8052 dev/pci/pciide.c sc->sc_wdcdev.set_modes = ite_setup_channel;
sc_wdcdev 8053 dev/pci/pciide.c sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc_wdcdev 8054 dev/pci/pciide.c sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
sc_wdcdev 8056 dev/pci/pciide.c pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
sc_wdcdev 8065 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
sc_wdcdev 8072 dev/pci/pciide.c sc->sc_wdcdev.set_modes(&cp->wdc_channel);
sc_wdcdev 8079 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cfg & IT_CFG_MASK,
sc_wdcdev 8098 dev/pci/pciide.c WDCDEBUG_PRINT(("%s:%d: tim=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname,
sc_wdcdev 8128 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname,
sc_wdcdev 8172 dev/pci/pciide.c WDCDEBUG_PRINT(("%s: tim=0x%x\n", sc->sc_wdcdev.sc_dev.dv_xname,
sc_wdcdev 8199 dev/pci/pciide.c sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
sc_wdcdev 8202 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
sc_wdcdev 8203 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
sc_wdcdev 8204 dev/pci/pciide.c sc->sc_wdcdev.irqack = pciide_irqack;
sc_wdcdev 8206 dev/pci/pciide.c sc->sc_wdcdev.PIO_cap = 4;
sc_wdcdev 8207 dev/pci/pciide.c sc->sc_wdcdev.DMA_cap = 2;
sc_wdcdev 8208 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 6;
sc_wdcdev 8210 dev/pci/pciide.c sc->sc_wdcdev.set_modes = ixp_setup_channel;
sc_wdcdev 8211 dev/pci/pciide.c sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc_wdcdev 8212 dev/pci/pciide.c sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
sc_wdcdev 8214 dev/pci/pciide.c pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
sc_wdcdev 8216 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
sc_wdcdev 8229 dev/pci/pciide.c sc->sc_wdcdev.set_modes(&cp->wdc_channel);
sc_wdcdev 8330 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, conf), DEBUG_PROBE);
sc_wdcdev 8335 dev/pci/pciide.c sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 |
sc_wdcdev 8338 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA;
sc_wdcdev 8339 dev/pci/pciide.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK;
sc_wdcdev 8340 dev/pci/pciide.c sc->sc_wdcdev.irqack = pciide_irqack;
sc_wdcdev 8342 dev/pci/pciide.c sc->sc_wdcdev.PIO_cap = 4;
sc_wdcdev 8343 dev/pci/pciide.c sc->sc_wdcdev.DMA_cap = 2;
sc_wdcdev 8344 dev/pci/pciide.c sc->sc_wdcdev.UDMA_cap = 6;
sc_wdcdev 8345 dev/pci/pciide.c sc->sc_wdcdev.set_modes = jmicron_setup_channel;
sc_wdcdev 8346 dev/pci/pciide.c sc->sc_wdcdev.channels = sc->wdc_chanarray;
sc_wdcdev 8347 dev/pci/pciide.c sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
sc_wdcdev 8349 dev/pci/pciide.c pciide_print_channels(sc->sc_wdcdev.nchannels, interface);
sc_wdcdev 8351 dev/pci/pciide.c for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
sc_wdcdev 8360 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
sc_wdcdev 8381 dev/pci/pciide.c sc->sc_wdcdev.set_modes(&cp->wdc_channel);
sc_wdcdev 8384 dev/pci/pciide.c sc->sc_wdcdev.sc_dev.dv_xname, conf), DEBUG_PROBE);
sc_wdcdev 56 dev/pci/pciidevar.h struct wdc_softc sc_wdcdev; /* common wdc definitions */
sc_wdcdev 74 dev/pcmcia/wdc_pcmcia.c struct wdc_softc sc_wdcdev;
sc_wdcdev 348 dev/pcmcia/wdc_pcmcia.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32;
sc_wdcdev 349 dev/pcmcia/wdc_pcmcia.c sc->sc_wdcdev.PIO_cap = 0;
sc_wdcdev 351 dev/pcmcia/wdc_pcmcia.c sc->sc_wdcdev.channels = &sc->wdc_chanptr;
sc_wdcdev 352 dev/pcmcia/wdc_pcmcia.c sc->sc_wdcdev.nchannels = 1;
sc_wdcdev 354 dev/pcmcia/wdc_pcmcia.c sc->wdc_channel.wdc = &sc->sc_wdcdev;
sc_wdcdev 362 dev/pcmcia/wdc_pcmcia.c sc->sc_wdcdev.cap |= WDC_CAPABILITY_NO_EXTRA_RESETS;
sc_wdcdev 366 dev/pcmcia/wdc_pcmcia.c sc->sc_wdcdev.sc_atapi_adapter.scsipi_enable = wdc_pcmcia_enable;
sc_wdcdev 376 dev/pcmcia/wdc_pcmcia.c &sc->wdc_channel, sc->sc_wdcdev.sc_dev.dv_xname);
sc_wdcdev 455 dev/pcmcia/wdc_pcmcia.c sc->sc_wdcdev.sc_dev.dv_xname);
sc_wdcdev 461 dev/pcmcia/wdc_pcmcia.c wdcintr, &sc->wdc_channel, sc->sc_wdcdev.sc_dev.dv_xname);
sc_wdcdev 465 dev/pcmcia/wdc_pcmcia.c sc->sc_wdcdev.sc_dev.dv_xname);
sc_wdcdev 497 dev/pcmcia/wdc_pcmcia.c sc->sc_wdcdev.sc_dev.dv_xname);
sc_wdcdev 506 dev/pcmcia/wdc_pcmcia.c sc->sc_wdcdev.sc_dev.dv_xname);