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19 #ifndef _DEV_PCI_PCIIDE_SVWSATA_REG_H_
20 #define _DEV_PCI_PCIIDE_SVWSATA_REG_H_
21
22 struct pciide_svwsata {
23 bus_space_tag_t ba5_st;
24 bus_space_handle_t ba5_sh;
25 };
26
27 #define SVWSATA_TF0 0x00
28 #define SVWSATA_TF8 0x20
29
30 #define SVWSATA_DMA 0x30
31
32 #define SVWSATA_SSTATUS 0x40
33 #define SVWSATA_SERROR 0x44
34 #define SVWSATA_SCONTROL 0x48
35
36 #define SVWSATA_SICR1 0x80
37 #define SVWSATA_SICR2 0x84
38 #define SVWSATA_SIM 0x88
39
40 u_int8_t svwsata_read_reg(struct channel_softc *, enum wdc_regs);
41 void svwsata_write_reg(struct channel_softc *, enum wdc_regs, u_int8_t);
42 void svwsata_lba48_write_reg(struct channel_softc *, enum wdc_regs, u_int16_t);
43
44 struct channel_softc_vtbl wdc_svwsata_vtbl = {
45 svwsata_read_reg,
46 svwsata_write_reg,
47 svwsata_lba48_write_reg,
48 wdc_default_read_raw_multi_2,
49 wdc_default_write_raw_multi_2,
50 wdc_default_read_raw_multi_4,
51 wdc_default_write_raw_multi_4
52 };
53
54 #endif