cls               409 dev/audio.c        mixer_devinfo_t *mi, int cls, char *name, char *mname, struct portname *tbl)
cls               413 dev/audio.c    	if (mi->mixer_class != cls)
cls              3766 dev/pci/pciide.c 	pcireg_t cls, reg40, reg44;
cls              3768 dev/pci/pciide.c 	cls = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
cls              3769 dev/pci/pciide.c 	cls = (cls >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK;
cls              3770 dev/pci/pciide.c 	cls *= 4;
cls              3771 dev/pci/pciide.c 	if (cls > 224) {
cls              3772 dev/pci/pciide.c 		cls = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
cls              3773 dev/pci/pciide.c 		cls &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT);
cls              3774 dev/pci/pciide.c 		cls |= ((224/4) << PCI_CACHELINE_SHIFT);
cls              3775 dev/pci/pciide.c 		pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, cls);
cls              3776 dev/pci/pciide.c 		cls = 224;
cls              3778 dev/pci/pciide.c 	if (cls < 32)
cls              3779 dev/pci/pciide.c 		cls = 32;
cls              3780 dev/pci/pciide.c 	cls = (cls + 31) / 32;
cls              3783 dev/pci/pciide.c 	if ((reg40 & 0x7) < cls)
cls              3784 dev/pci/pciide.c 		ba5_write_4(sc, 0x40, (reg40 & ~0x07) | cls);
cls              3785 dev/pci/pciide.c 	if ((reg44 & 0x7) < cls)
cls              3786 dev/pci/pciide.c 		ba5_write_4(sc, 0x44, (reg44 & ~0x07) | cls);