root/dev/pci/if_bce.c

DEFINITIONS

1. bce_probe
2. bce_attach
3. bce_ioctl
4. bce_start
5. bce_watchdog
6. bce_intr
7. bce_rxintr
8. bce_txintr
9. bce_init
10. bce_add_mac
11. bce_add_rxbuf
12. bce_rxdrain
13. bce_stop
14. bce_reset
15. bce_set_filter
16. bce_mii_read
17. bce_mii_write
18. bce_statchg
19. bce_mediachange
20. bce_mediastatus
21. bce_tick

    1 /* $OpenBSD: if_bce.c,v 1.20 2007/05/21 10:30:10 reyk Exp $ */
    2 /* $NetBSD: if_bce.c,v 1.3 2003/09/29 01:53:02 mrg Exp $         */
    4 /*
    5  * Copyright (c) 2003 Clifford Wright. All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. The name of the author may not be used to endorse or promote products
   16  *    derived from this software without specific prior written permission.
   17  *
   18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   19  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   20  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   21  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   22  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
   23  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
   24  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
   25  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
   26  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   28  * SUCH DAMAGE.
   29  */
   31 /*
   32  * Broadcom BCM440x 10/100 ethernet (broadcom.com)
   33  * SiliconBackplane is technology from Sonics, Inc.(sonicsinc.com)
   34  *
   35  * Cliff Wright cliff@snipe444.org
   36  */
   38 #include "bpfilter.h"
   40 #include <sys/param.h>
   41 #include <sys/systm.h>
   42 #include <sys/timeout.h>
   43 #include <sys/sockio.h>
   44 #include <sys/mbuf.h>
   45 #include <sys/malloc.h>
   46 #include <sys/kernel.h>
   47 #include <sys/device.h>
   48 #include <sys/socket.h>
   50 #include <net/if.h>
   51 #include <net/if_dl.h>
   52 #include <net/if_media.h>
   54 #ifdef INET
   55 #include <netinet/in.h>
   56 #include <netinet/in_systm.h>
   57 #include <netinet/in_var.h>
   58 #include <netinet/ip.h>
   59 #include <netinet/if_ether.h>
   60 #endif
   61 #if NBPFILTER > 0
   62 #include <net/bpf.h>
   63 #endif
   65 #include <dev/pci/pcireg.h>
   66 #include <dev/pci/pcivar.h>
   67 #include <dev/pci/pcidevs.h>
   69 #include <dev/mii/mii.h>
   70 #include <dev/mii/miivar.h>
   71 #include <dev/mii/miidevs.h>
   72 #include <dev/mii/brgphyreg.h>
   74 #include <dev/pci/if_bcereg.h>
   76 #include <uvm/uvm_extern.h>
   78 /* transmit buffer max frags allowed */
   79 #define BCE_NTXFRAGS    16
   81 /* ring descriptor */
   82 struct bce_dma_slot {
u_int32_t ctrl;
u_int32_t addr;
   85 };
   86 #define CTRL_BC_MASK    0x1fff  /* buffer byte count */
   87 #define CTRL_EOT        0x10000000      /* end of descriptor table */
   88 #define CTRL_IOC        0x20000000      /* interrupt on completion */
   89 #define CTRL_EOF        0x40000000      /* end of frame */
   90 #define CTRL_SOF        0x80000000      /* start of frame */
   92 /* Packet status is returned in a pre-packet header */
   93 struct rx_pph {
u_int16_t len;
u_int16_t flags;
u_int16_t pad[12];
   97 };
   99 #define BCE_PREPKT_HEADER_SIZE          30
  101 /* packet status flags bits */
  102 #define RXF_NO                          0x8     /* odd number of nibbles */
  103 #define RXF_RXER                        0x4     /* receive symbol error */
  104 #define RXF_CRC                         0x2     /* crc error */
  105 #define RXF_OV                          0x1     /* fifo overflow */
  107 /* number of descriptors used in a ring */
  108 #define BCE_NRXDESC             128
  109 #define BCE_NTXDESC             128
  111 /*
  112  * Mbuf pointers. We need these to keep track of the virtual addresses
  113  * of our mbuf chains since we can only convert from physical to virtual,
  114  * not the other way around.
  115  */
  116 struct bce_chain_data {
  117         struct mbuf    *bce_tx_chain[BCE_NTXDESC];
  118         struct mbuf    *bce_rx_chain[BCE_NRXDESC];
bus_dmamap_t    bce_tx_map[BCE_NTXDESC];
bus_dmamap_t    bce_rx_map[BCE_NRXDESC];
  121 };
  123 #define BCE_TIMEOUT             100     /* # 10us for mii read/write */
  125 struct bce_softc {
  126         struct device           bce_dev;
bus_space_tag_t         bce_btag;
bus_space_handle_t      bce_bhandle;
bus_dma_tag_t           bce_dmatag;
  130         struct arpcom           bce_ac;         /* interface info */
  131         void                    *bce_intrhand;
  132         struct pci_attach_args  bce_pa;
  133         struct mii_data         bce_mii;
u_int32_t               bce_phy;        /* eeprom indicated phy */
  135         struct bce_dma_slot     *bce_rx_ring;   /* receive ring */
  136         struct bce_dma_slot     *bce_tx_ring;   /* transmit ring */
  137         struct bce_chain_data   bce_cdata;      /* mbufs */
bus_dmamap_t            bce_ring_map;
u_int32_t               bce_intmask;    /* current intr mask */
u_int32_t               bce_rxin;       /* last rx descriptor seen */
u_int32_t               bce_txin;       /* last tx descriptor seen */
  142         int                     bce_txsfree;    /* no. tx slots available */
  143         int                     bce_txsnext;    /* next available tx slot */
  144         struct timeout          bce_timeout;
  145 };
  147 /* for ring descriptors */
  148 #define BCE_RXBUF_LEN   (MCLBYTES - 4)
  149 #define BCE_INIT_RXDESC(sc, x)                                          \
  150 do {                                                                    \
  151         struct bce_dma_slot *__bced = &sc->bce_rx_ring[x];              \
  152                                                                         \
  153         *mtod(sc->bce_cdata.bce_rx_chain[x], u_int32_t *) = 0;          \
__bced->addr =                                                  \
htole32(sc->bce_cdata.bce_rx_map[x]->dm_segs[0].ds_addr     \
  156             + 0x40000000);                                              \
  157         if (x != (BCE_NRXDESC - 1))                                     \
__bced->ctrl = htole32(BCE_RXBUF_LEN);                  \
  159         else                                                            \
__bced->ctrl = htole32(BCE_RXBUF_LEN | CTRL_EOT);       \
bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map,               \
  162             sizeof(struct bce_dma_slot) * x,                            \
  163             sizeof(struct bce_dma_slot),                                \
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);                  \
  165 } while (/* CONSTCOND */ 0)
  167 int     bce_probe(struct device *, void *, void *);
  168 void    bce_attach(struct device *, struct device *, void *);
  169 int     bce_ioctl(struct ifnet *, u_long, caddr_t);
  170 void    bce_start(struct ifnet *);
  171 void    bce_watchdog(struct ifnet *);
  172 int     bce_intr(void *);
  173 void    bce_rxintr(struct bce_softc *);
  174 void    bce_txintr(struct bce_softc *);
  175 int     bce_init(struct ifnet *);
  176 void    bce_add_mac(struct bce_softc *, u_int8_t *, unsigned long);
  177 int     bce_add_rxbuf(struct bce_softc *, int);
  178 void    bce_rxdrain(struct bce_softc *);
  179 void    bce_stop(struct ifnet *, int);
  180 void    bce_reset(struct bce_softc *);
  181 void    bce_set_filter(struct ifnet *);
  182 int     bce_mii_read(struct device *, int, int);
  183 void    bce_mii_write(struct device *, int, int, int);
  184 void    bce_statchg(struct device *);
  185 int     bce_mediachange(struct ifnet *);
  186 void    bce_mediastatus(struct ifnet *, struct ifmediareq *);
  187 void    bce_tick(void *);
  189 #ifdef BCE_DEBUG
  190 #define DPRINTF(x)      do {            \
  191         if (bcedebug)                   \
printf x;               \
  193 } while (/* CONSTCOND */ 0)
  194 #define DPRINTFN(n,x)   do {            \
  195         if (bcedebug >= (n))            \
printf x;               \
  197 } while (/* CONSTCOND */ 0)
  198 int             bcedebug = 0;
  199 #else
  200 #define DPRINTF(x)
  201 #define DPRINTFN(n,x)
  202 #endif
  204 struct cfattach bce_ca = {
  205         sizeof(struct bce_softc), bce_probe, bce_attach
  206 };
  207 struct cfdriver bce_cd = {
  208         0, "bce", DV_IFNET
  209 };
  211 const struct pci_matchid bce_devices[] = {
  212         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401 },
  213         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401B0 },
  214         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401B1 }
  215 };
  217 int
bce_probe(struct device *parent, void *match, void *aux)
  219 {
  220         return (pci_matchbyid((struct pci_attach_args *)aux, bce_devices,
  221             sizeof(bce_devices)/sizeof(bce_devices[0])));
  222 }
  224 void
bce_attach(struct device *parent, struct device *self, void *aux)
  226 {
  227         struct bce_softc *sc = (struct bce_softc *) self;
  228         struct pci_attach_args *pa = aux;
pci_chipset_tag_t pc = pa->pa_pc;
pci_intr_handle_t ih;
  231         const char     *intrstr = NULL;
caddr_t         kva;
bus_dma_segment_t seg;
  234         int             rseg;
  235         struct ifnet   *ifp;
pcireg_t        memtype;
bus_addr_t      memaddr;
bus_size_t      memsize;
  239         int             pmreg;
pcireg_t        pmode;
  241         int             error;
  242         int             i;
sc->bce_pa = *pa;
sc->bce_dmatag = pa->pa_dmat;
  247         /*
  248          * Map control/status registers.
  249          */
memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BCE_PCI_BAR0);
  251         switch (memtype) {
  252         case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
  253         case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
  254                 if (pci_mapreg_map(pa, BCE_PCI_BAR0, memtype, 0, &sc->bce_btag,
  255                     &sc->bce_bhandle, &memaddr, &memsize, 0) == 0)
  256                         break;
  257         default:
printf("%s: unable to find mem space\n",
sc->bce_dev.dv_xname);
  260                 return;
  261         }
  263         /* Get it out of power save mode if needed. */
  264         if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) {
pmode = pci_conf_read(pc, pa->pa_tag, pmreg + 4) & 0x3;
  266                 if (pmode == 3) {
  267                         /*
  268                          * The card has lost all configuration data in
  269                          * this state, so punt.
  270                          */
printf("%s: unable to wake up from power state D3\n",
sc->bce_dev.dv_xname);
  273                         return;
  274                 }
  275                 if (pmode != 0) {
printf("%s: waking up from power state D%d\n",
sc->bce_dev.dv_xname, pmode);
pci_conf_write(pc, pa->pa_tag, pmreg + 4, 0);
  279                 }
  280         }
  281         if (pci_intr_map(pa, &ih)) {
printf("%s: couldn't map interrupt\n",
sc->bce_dev.dv_xname);
  284                 return;
  285         }
intrstr = pci_intr_string(pc, ih);
sc->bce_intrhand = pci_intr_establish(pc, ih, IPL_NET, bce_intr, sc,
self->dv_xname);
  291         if (sc->bce_intrhand == NULL) {
printf("%s: couldn't establish interrupt",
sc->bce_dev.dv_xname);
  294                 if (intrstr != NULL)
printf(" at %s", intrstr);
printf("\n");
  297                 return;
  298         }
  300         /* reset the chip */
bce_reset(sc);
  303         /*
  304          * Allocate DMA-safe memory for ring descriptors.
  305          * The receive, and transmit rings can not share the same
  306          * 4k space, however both are allocated at once here.
  307          */
  308         /*
  309          * XXX PAGE_SIZE is wasteful; we only need 1KB + 1KB, but
  310          * due to the limition above. ??
  311          */
  312         if ((error = bus_dmamem_alloc(sc->bce_dmatag,
  313             2 * PAGE_SIZE, PAGE_SIZE, 2 * PAGE_SIZE,
  314                                       &seg, 1, &rseg, BUS_DMA_NOWAIT))) {
printf("%s: unable to alloc space for ring descriptors, "
  316                        "error = %d\n", sc->bce_dev.dv_xname, error);
  317                 return;
  318         }
  319         /* map ring space to kernel */
  320         if ((error = bus_dmamem_map(sc->bce_dmatag, &seg, rseg,
  321             2 * PAGE_SIZE, &kva, BUS_DMA_NOWAIT))) {
printf("%s: unable to map DMA buffers, error = %d\n",
sc->bce_dev.dv_xname, error);
bus_dmamem_free(sc->bce_dmatag, &seg, rseg);
  325                 return;
  326         }
  327         /* create a dma map for the ring */
  328         if ((error = bus_dmamap_create(sc->bce_dmatag,
  329             2 * PAGE_SIZE, 1, 2 * PAGE_SIZE, 0, BUS_DMA_NOWAIT,
  330                                        &sc->bce_ring_map))) {
printf("%s: unable to create ring DMA map, error = %d\n",
sc->bce_dev.dv_xname, error);
bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE);
bus_dmamem_free(sc->bce_dmatag, &seg, rseg);
  335                 return;
  336         }
  337         /* connect the ring space to the dma map */
  338         if (bus_dmamap_load(sc->bce_dmatag, sc->bce_ring_map, kva,
  339             2 * PAGE_SIZE, NULL, BUS_DMA_NOWAIT)) {
bus_dmamap_destroy(sc->bce_dmatag, sc->bce_ring_map);
bus_dmamem_unmap(sc->bce_dmatag, kva, 2 * PAGE_SIZE);
bus_dmamem_free(sc->bce_dmatag, &seg, rseg);
  343                 return;
  344         }
  345         /* save the ring space in softc */
sc->bce_rx_ring = (struct bce_dma_slot *) kva;
sc->bce_tx_ring = (struct bce_dma_slot *) (kva + PAGE_SIZE);
  349         /* Create the transmit buffer DMA maps. */
  350         for (i = 0; i < BCE_NTXDESC; i++) {
  351                 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES,
BCE_NTXFRAGS, MCLBYTES, 0, 0, &sc->bce_cdata.bce_tx_map[i])) != 0) {
printf("%s: unable to create tx DMA map, error = %d\n",
sc->bce_dev.dv_xname, error);
  355                 }
sc->bce_cdata.bce_tx_chain[i] = NULL;
  357         }
  359         /* Create the receive buffer DMA maps. */
  360         for (i = 0; i < BCE_NRXDESC; i++) {
  361                 if ((error = bus_dmamap_create(sc->bce_dmatag, MCLBYTES, 1,
MCLBYTES, 0, 0, &sc->bce_cdata.bce_rx_map[i])) != 0) {
printf("%s: unable to create rx DMA map, error = %d\n",
sc->bce_dev.dv_xname, error);
  365                 }
sc->bce_cdata.bce_rx_chain[i] = NULL;
  367         }
  369         /* Set up ifnet structure */
ifp = &sc->bce_ac.ac_if;
strlcpy(ifp->if_xname, sc->bce_dev.dv_xname, IF_NAMESIZE);
ifp->if_softc = sc;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_ioctl = bce_ioctl;
ifp->if_start = bce_start;
ifp->if_watchdog = bce_watchdog;
ifp->if_init = bce_init;
IFQ_SET_READY(&ifp->if_snd);
ifp->if_capabilities = IFCAP_VLAN_MTU;
  382         /* MAC address */
sc->bce_ac.ac_enaddr[0] =
bus_space_read_1(sc->bce_btag, sc->bce_bhandle, BCE_ENET0);
sc->bce_ac.ac_enaddr[1] =
bus_space_read_1(sc->bce_btag, sc->bce_bhandle, BCE_ENET1);
sc->bce_ac.ac_enaddr[2] =
bus_space_read_1(sc->bce_btag, sc->bce_bhandle, BCE_ENET2);
sc->bce_ac.ac_enaddr[3] =
bus_space_read_1(sc->bce_btag, sc->bce_bhandle, BCE_ENET3);
sc->bce_ac.ac_enaddr[4] =
bus_space_read_1(sc->bce_btag, sc->bce_bhandle, BCE_ENET4);
sc->bce_ac.ac_enaddr[5] =
bus_space_read_1(sc->bce_btag, sc->bce_bhandle, BCE_ENET5);
printf(": %s, address %s\n", intrstr,
ether_sprintf(sc->bce_ac.ac_enaddr));
  398         /* Initialize our media structures and probe the MII. */
sc->bce_mii.mii_ifp = ifp;
sc->bce_mii.mii_readreg = bce_mii_read;
sc->bce_mii.mii_writereg = bce_mii_write;
sc->bce_mii.mii_statchg = bce_statchg;
ifmedia_init(&sc->bce_mii.mii_media, 0, bce_mediachange,
bce_mediastatus);
mii_attach(&sc->bce_dev, &sc->bce_mii, 0xffffffff, MII_PHY_ANY,
MII_OFFSET_ANY, 0);
  408         if (LIST_FIRST(&sc->bce_mii.mii_phys) == NULL) {
ifmedia_add(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE, 0, NULL);
ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_NONE);
  411         } else
ifmedia_set(&sc->bce_mii.mii_media, IFM_ETHER | IFM_AUTO);
  413         /* get the phy */
sc->bce_phy = bus_space_read_1(sc->bce_btag, sc->bce_bhandle,
BCE_PHY) & 0x1f;
  416         /*
  417          * Enable activity led.
  418          * XXX This should be in a phy driver, but not currently.
  419          */
bce_mii_write((struct device *) sc, 1, 26,       /* MAGIC */
bce_mii_read((struct device *) sc, 1, 26) & 0x7fff);         /* MAGIC */
  422         /* enable traffic meter led mode */
bce_mii_write((struct device *) sc, 1, 27,       /* MAGIC */
bce_mii_read((struct device *) sc, 1, 27) | (1 << 6));       /* MAGIC */
  427         /* Attach the interface */
if_attach(ifp);
ether_ifattach(ifp);
timeout_set(&sc->bce_timeout, bce_tick, sc);
  431 }
  433 /* handle media, and ethernet requests */
  434 int
bce_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
  436 {
  437         struct bce_softc *sc = ifp->if_softc;
  438         struct ifreq   *ifr = (struct ifreq *) data;
  439         struct ifaddr *ifa = (struct ifaddr *)data;
  440         int             s, error = 0;
s = splnet();
  444         if ((error = ether_ioctl(ifp, &sc->bce_ac, cmd, data)) > 0) {
splx(s);
  446                 return (error);
  447         }
  449         switch (cmd) {
  450         case SIOCSIFADDR:
ifp->if_flags |= IFF_UP;
  453                 switch (ifa->ifa_addr->sa_family) {
  454 #ifdef INET
  455                 case AF_INET:
bce_init(ifp);
arp_ifinit(&sc->bce_ac, ifa);
  458                         break;
  459 #endif /* INET */
  460                 default:
bce_init(ifp);
  462                         break;
  463                 }
  464                 break;
  465         case SIOCSIFMTU:
  466                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU)
error = EINVAL;
  468                 else if (ifp->if_mtu != ifr->ifr_mtu)
ifp->if_mtu = ifr->ifr_mtu;
  470                 break;
  471         case SIOCSIFFLAGS:
  472                 if(ifp->if_flags & IFF_UP)
  473                         if(ifp->if_flags & IFF_RUNNING)
bce_set_filter(ifp);
  475                         else
bce_init(ifp);
  477                 else if(ifp->if_flags & IFF_RUNNING)
bce_stop(ifp, 0);
  480                 break;
  481         case SIOCADDMULTI:
  482         case SIOCDELMULTI:
error = (cmd == SIOCADDMULTI) ?
ether_addmulti(ifr, &sc->bce_ac) :
ether_delmulti(ifr, &sc->bce_ac);
  487                 if (error == ENETRESET) {
  488                         /*
  489                          * Multicast list has changed; set the hardware
  490                          * filter accordingly.
  491                          */
  492                         if (ifp->if_flags & IFF_RUNNING)
bce_set_filter(ifp);
error = 0;
  495                 }
  496                 break;
  497         case SIOCSIFMEDIA:
  498         case SIOCGIFMEDIA:
error = ifmedia_ioctl(ifp, ifr, &sc->bce_mii.mii_media, cmd);
  500                 break;
  501         default:
error = ENOTTY;
  503                 break;
  504         }
  506         if (error == 0) {
  507                 /* Try to get more packets going. */
bce_start(ifp);
  509         }
splx(s);
  512         return error;
  513 }
  515 /* Start packet transmission on the interface. */
  516 void
bce_start(struct ifnet *ifp)
  518 {
  519         struct bce_softc *sc = ifp->if_softc;
  520         struct mbuf    *m0;
bus_dmamap_t    dmamap;
  522         int             txstart;
  523         int             txsfree;
  524         int             newpkts = 0;
  525         int             error;
  527         /*
  528          * do not start another if currently transmitting, and more
  529          * descriptors(tx slots) are needed for next packet.
  530          */
  531         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
  532                 return;
  534         /* determine number of descriptors available */
  535         if (sc->bce_txsnext >= sc->bce_txin)
txsfree = BCE_NTXDESC - 1 + sc->bce_txin - sc->bce_txsnext;
  537         else
txsfree = sc->bce_txin - sc->bce_txsnext - 1;
  540         /*
  541          * Loop through the send queue, setting up transmit descriptors
  542          * until we drain the queue, or use up all available transmit
  543          * descriptors.
  544          */
  545         while (txsfree > 0) {
  546                 int             seg;
  548                 /* Grab a packet off the queue. */
IFQ_POLL(&ifp->if_snd, m0);
  550                 if (m0 == NULL)
  551                         break;
  553                 /* get the transmit slot dma map */
dmamap = sc->bce_cdata.bce_tx_map[sc->bce_txsnext];
  556                 /*
  557                  * Load the DMA map.  If this fails, the packet either
  558                  * didn't fit in the alloted number of segments, or we
  559                  * were short on resources. If the packet will not fit,
  560                  * it will be dropped. If short on resources, it will
  561                  * be tried again later.
  562                  */
error = bus_dmamap_load_mbuf(sc->bce_dmatag, dmamap, m0,
BUS_DMA_WRITE | BUS_DMA_NOWAIT);
  565                 if (error == EFBIG) {
printf("%s: Tx packet consumes too many DMA segments, "
  567                             "dropping...\n", sc->bce_dev.dv_xname);
IFQ_DEQUEUE(&ifp->if_snd, m0);
m_freem(m0);
ifp->if_oerrors++;
  571                         continue;
  572                 } else if (error) {
  573                         /* short on resources, come back later */
printf("%s: unable to load Tx buffer, error = %d\n",
sc->bce_dev.dv_xname, error);
  576                         break;
  577                 }
  578                 /* If not enough descriptors available, try again later */
  579                 if (dmamap->dm_nsegs > txsfree) {
ifp->if_flags |= IFF_OACTIVE;
bus_dmamap_unload(sc->bce_dmatag, dmamap);
  582                         break;
  583                 }
  584                 /* WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET. */
  586                 /* So take it off the queue */
IFQ_DEQUEUE(&ifp->if_snd, m0);
  589                 /* save the pointer so it can be freed later */
sc->bce_cdata.bce_tx_chain[sc->bce_txsnext] = m0;
  592                 /* Sync the data DMA map. */
bus_dmamap_sync(sc->bce_dmatag, dmamap, 0, dmamap->dm_mapsize,
BUS_DMASYNC_PREWRITE);
  596                 /* Initialize the transmit descriptor(s). */
txstart = sc->bce_txsnext;
  598                 for (seg = 0; seg < dmamap->dm_nsegs; seg++) {
u_int32_t ctrl;
ctrl = dmamap->dm_segs[seg].ds_len & CTRL_BC_MASK;
  602                         if (seg == 0)
ctrl |= CTRL_SOF;
  604                         if (seg == dmamap->dm_nsegs - 1)
ctrl |= CTRL_EOF;
  606                         if (sc->bce_txsnext == BCE_NTXDESC - 1)
ctrl |= CTRL_EOT;
ctrl |= CTRL_IOC;
sc->bce_tx_ring[sc->bce_txsnext].ctrl = htole32(ctrl);
sc->bce_tx_ring[sc->bce_txsnext].addr =
htole32(dmamap->dm_segs[seg].ds_addr + 0x40000000); /* MAGIC */
  612                         if (sc->bce_txsnext + 1 > BCE_NTXDESC - 1)
sc->bce_txsnext = 0;
  614                         else
sc->bce_txsnext++;
txsfree--;
  617                 }
  618                 /* sync descriptors being used */
bus_dmamap_sync(sc->bce_dmatag, sc->bce_ring_map,
  620                           sizeof(struct bce_dma_slot) * txstart + PAGE_SIZE,
  621                              sizeof(struct bce_dma_slot) * dmamap->dm_nsegs,
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
  624                 /* Give the packet to the chip. */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_DPTR,
sc->bce_txsnext * sizeof(struct bce_dma_slot));
newpkts++;
  630 #if NBPFILTER > 0
  631                 /* Pass the packet to any BPF listeners. */
  632                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m0, BPF_DIRECTION_OUT);
  634 #endif                          /* NBPFILTER > 0 */
  635         }
  636         if (txsfree == 0) {
  637                 /* No more slots left; notify upper layer. */
ifp->if_flags |= IFF_OACTIVE;
  639         }
  640         if (newpkts) {
  641                 /* Set a watchdog timer in case the chip flakes out. */
ifp->if_timer = 5;
  643         }
  644 }
  646 /* Watchdog timer handler. */
  647 void
bce_watchdog(struct ifnet *ifp)
  649 {
  650         struct bce_softc *sc = ifp->if_softc;
printf("%s: device timeout\n", sc->bce_dev.dv_xname);
ifp->if_oerrors++;
  655         (void) bce_init(ifp);
  657         /* Try to get more packets going. */
bce_start(ifp);
  659 }
  661 int
bce_intr(void *xsc)
  663 {
  664         struct bce_softc *sc;
  665         struct ifnet   *ifp;
u_int32_t intstatus;
  667         int             wantinit;
  668         int             handled = 0;
sc = xsc;
ifp = &sc->bce_ac.ac_if;
  674         for (wantinit = 0; wantinit == 0;) {
intstatus = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
BCE_INT_STS);
  678                 /* ignore if not ours, or unsolicited interrupts */
intstatus &= sc->bce_intmask;
  680                 if (intstatus == 0)
  681                         break;
handled = 1;
  685                 /* Ack interrupt */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_STS,
intstatus);
  689                 /* Receive interrupts. */
  690                 if (intstatus & I_RI)
bce_rxintr(sc);
  692                 /* Transmit interrupts. */
  693                 if (intstatus & I_XI)
bce_txintr(sc);
  695                 /* Error interrupts */
  696                 if (intstatus & ~(I_RI | I_XI)) {
  697                         if (intstatus & I_XU)
printf("%s: transmit fifo underflow\n",
sc->bce_dev.dv_xname);
  700                         if (intstatus & I_RO) {
printf("%s: receive fifo overflow\n",
sc->bce_dev.dv_xname);
ifp->if_ierrors++;
  704                         }
  705                         if (intstatus & I_RU)
printf("%s: receive descriptor underflow\n",
sc->bce_dev.dv_xname);
  708                         if (intstatus & I_DE)
printf("%s: descriptor protocol error\n",
sc->bce_dev.dv_xname);
  711                         if (intstatus & I_PD)
printf("%s: data error\n",
sc->bce_dev.dv_xname);
  714                         if (intstatus & I_PC)
printf("%s: descriptor error\n",
sc->bce_dev.dv_xname);
  717                         if (intstatus & I_TO)
printf("%s: general purpose timeout\n",
sc->bce_dev.dv_xname);
wantinit = 1;
  721                 }
  722         }
  724         if (handled) {
  725                 if (wantinit)
bce_init(ifp);
  727                 /* Try to get more packets going. */
bce_start(ifp);
  729         }
  730         return (handled);
  731 }
  733 /* Receive interrupt handler */
  734 void
bce_rxintr(struct bce_softc *sc)
  736 {
  737         struct ifnet   *ifp = &sc->bce_ac.ac_if;
  738         struct rx_pph  *pph;
  739         struct mbuf    *m;
  740         int             curr;
  741         int             len;
  742         int             i;
  744         /* get pointer to active receive slot */
curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS)
  746             & RS_CD_MASK;
curr = curr / sizeof(struct bce_dma_slot);
  748         if (curr >= BCE_NRXDESC)
curr = BCE_NRXDESC - 1;
  751         /* process packets up to but not current packet being worked on */
  752         for (i = sc->bce_rxin; i != curr;
i + 1 > BCE_NRXDESC - 1 ? i = 0 : i++) {
  754                 /* complete any post dma memory ops on packet */
bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[i], 0,
sc->bce_cdata.bce_rx_map[i]->dm_mapsize,
BUS_DMASYNC_POSTREAD);
  759                 /*
  760                  * If the packet had an error, simply recycle the buffer,
  761                  * resetting the len, and flags.
  762                  */
pph = mtod(sc->bce_cdata.bce_rx_chain[i], struct rx_pph *);
  764                 if (pph->flags & (RXF_NO | RXF_RXER | RXF_CRC | RXF_OV)) {
ifp->if_ierrors++;
pph->len = 0;
pph->flags = 0;
  768                         continue;
  769                 }
  770                 /* receive the packet */
len = pph->len;
  772                 if (len == 0)
  773                         continue;       /* no packet if empty */
pph->len = 0;
pph->flags = 0;
  776                 /* bump past pre header to packet */
sc->bce_cdata.bce_rx_chain[i]->m_data +=
BCE_PREPKT_HEADER_SIZE;
  780                 /*
  781                  * The chip includes the CRC with every packet.  Trim
  782                  * it off here.
  783                  */
len -= ETHER_CRC_LEN;
  786                 /*
  787                  * If the packet is small enough to fit in a
  788                  * single header mbuf, allocate one and copy
  789                  * the data into it.  This greatly reduces
  790                  * memory consumption when receiving lots
  791                  * of small packets.
  792                  *
  793                  * Otherwise, add a new buffer to the receive
  794                  * chain.  If this fails, drop the packet and
  795                  * recycle the old buffer.
  796                  */
  797                 if (len <= (MHLEN - 2)) {
MGETHDR(m, M_DONTWAIT, MT_DATA);
  799                         if (m == NULL)
  800                                 goto dropit;
m->m_data += 2;
memcpy(mtod(m, caddr_t),
mtod(sc->bce_cdata.bce_rx_chain[i], caddr_t), len);
sc->bce_cdata.bce_rx_chain[i]->m_data -=
BCE_PREPKT_HEADER_SIZE;
  806                 } else {
m = sc->bce_cdata.bce_rx_chain[i];
  808                         if (bce_add_rxbuf(sc, i) != 0) {
dropit:
ifp->if_ierrors++;
  811                                 /* continue to use old buffer */
sc->bce_cdata.bce_rx_chain[i]->m_data -=
BCE_PREPKT_HEADER_SIZE;
bus_dmamap_sync(sc->bce_dmatag,
sc->bce_cdata.bce_rx_map[i], 0,
sc->bce_cdata.bce_rx_map[i]->dm_mapsize,
BUS_DMASYNC_PREREAD);
  818                                 continue;
  819                         }
  820                 }
m->m_pkthdr.rcvif = ifp;
m->m_pkthdr.len = m->m_len = len;
ifp->if_ipackets++;
  826 #if NBPFILTER > 0
  827                 /*
  828                  * Pass this up to any BPF listeners, but only
  829                  * pass it up the stack if it's for us.
  830                  */
  831                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN);
  833 #endif                          /* NBPFILTER > 0 */
  835                 /* Pass it on. */
ether_input_mbuf(ifp, m);
  838                 /* re-check current in case it changed */
curr = (bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
BCE_DMA_RXSTATUS) & RS_CD_MASK) /
  841                     sizeof(struct bce_dma_slot);
  842                 if (curr >= BCE_NRXDESC)
curr = BCE_NRXDESC - 1;
  844         }
sc->bce_rxin = curr;
  846 }
  848 /* Transmit interrupt handler */
  849 void
bce_txintr(struct bce_softc *sc)
  851 {
  852         struct ifnet   *ifp = &sc->bce_ac.ac_if;
  853         int             curr;
  854         int             i;
ifp->if_flags &= ~IFF_OACTIVE;
  858         /*
  859          * Go through the Tx list and free mbufs for those
  860          * frames which have been transmitted.
  861          */
curr = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXSTATUS) &
RS_CD_MASK;
curr = curr / sizeof(struct bce_dma_slot);
  865         if (curr >= BCE_NTXDESC)
curr = BCE_NTXDESC - 1;
  867         for (i = sc->bce_txin; i != curr;
i + 1 > BCE_NTXDESC - 1 ? i = 0 : i++) {
  869                 /* do any post dma memory ops on transmit data */
  870                 if (sc->bce_cdata.bce_tx_chain[i] == NULL)
  871                         continue;
bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i], 0,
sc->bce_cdata.bce_tx_map[i]->dm_mapsize,
BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->bce_dmatag, sc->bce_cdata.bce_tx_map[i]);
m_freem(sc->bce_cdata.bce_tx_chain[i]);
sc->bce_cdata.bce_tx_chain[i] = NULL;
ifp->if_opackets++;
  879         }
sc->bce_txin = curr;
  882         /*
  883          * If there are no more pending transmissions, cancel the watchdog
  884          * timer
  885          */
  886         if (sc->bce_txsnext == sc->bce_txin)
ifp->if_timer = 0;
  888 }
  890 /* initialize the interface */
  891 int
bce_init(struct ifnet *ifp)
  893 {
  894         struct bce_softc *sc = ifp->if_softc;
u_int32_t reg_win;
  896         int             error;
  897         int             i;
  899         /* Cancel any pending I/O. */
bce_stop(ifp, 0);
  902         /* enable pci inerrupts, bursts, and prefetch */
  904         /* remap the pci registers to the Sonics config registers */
  906         /* save the current map, so it can be restored */
reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag,
BCE_REG_WIN);
  910         /* set register window to Sonics registers */
pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN,
BCE_SONICS_WIN);
  914         /* enable SB to PCI interrupt */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC,
bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC) |
SBIV_ENET0);
  919         /* enable prefetch and bursts for sonics-to-pci translation 2 */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2,
bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2) |
SBTOPCI_PREF | SBTOPCI_BURST);
  924         /* restore to ethernet register space */
pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN,
reg_win);
  928         /* Reset the chip to a known state. */
bce_reset(sc);
  931         /* Initialize transmit descriptors */
memset(sc->bce_tx_ring, 0, BCE_NTXDESC * sizeof(struct bce_dma_slot));
sc->bce_txsnext = 0;
sc->bce_txin = 0;
  936         /* enable crc32 generation and set proper LED modes */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL,
bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL) |
BCE_EMC_CRC32_ENAB | BCE_EMC_LED);
  941         /* reset or clear powerdown control bit  */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL,
bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MACCTL) &
  944             ~BCE_EMC_PDOWN);
  946         /* setup DMA interrupt control */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL, 1 << 24);        /* MAGIC */
  949         /* setup packet filter */
bce_set_filter(ifp);
  952         /* set max frame length, account for possible VLAN tag */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_MAX,
ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN);
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_MAX,
ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN);
  958         /* set tx watermark */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_WATER, 56);
  961         /* enable transmit */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, XC_XE);
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXADDR,
sc->bce_ring_map->dm_segs[0].ds_addr + PAGE_SIZE + 0x40000000);     /* MAGIC */
  966         /*
  967          * Give the receive ring to the chip, and
  968          * start the receive DMA engine.
  969          */
sc->bce_rxin = 0;
  972         /* clear the rx descriptor ring */
memset(sc->bce_rx_ring, 0, BCE_NRXDESC * sizeof(struct bce_dma_slot));
  974         /* enable receive */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL,
BCE_PREPKT_HEADER_SIZE << 1 | XC_XE);
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXADDR,
sc->bce_ring_map->dm_segs[0].ds_addr + 0x40000000);         /* MAGIC */
  980         /* Initalize receive descriptors */
  981         for (i = 0; i < BCE_NRXDESC; i++) {
  982                 if (sc->bce_cdata.bce_rx_chain[i] == NULL) {
  983                         if ((error = bce_add_rxbuf(sc, i)) != 0) {
printf("%s: unable to allocate or map rx(%d) "
  985                                     "mbuf, error = %d\n", sc->bce_dev.dv_xname,
i, error);
bce_rxdrain(sc);
  988                                 return (error);
  989                         }
  990                 } else
BCE_INIT_RXDESC(sc, i);
  992         }
  994         /* Enable interrupts */
sc->bce_intmask =
I_XI | I_RI | I_XU | I_RO | I_RU | I_DE | I_PD | I_PC | I_TO;
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK,
sc->bce_intmask);
 1000         /* start the receive dma */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXDPTR,
BCE_NRXDESC * sizeof(struct bce_dma_slot));
 1004         /* set media */
mii_mediachg(&sc->bce_mii);
 1007         /* turn on the ethernet mac */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL,
bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
BCE_ENET_CTL) | EC_EE);
 1012         /* start timer */
timeout_add(&sc->bce_timeout, hz);
 1015         /* mark as running, and no outputs active */
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
 1019         return 0;
 1020 }
 1022 /* add a mac address to packet filter */
 1023 void
bce_add_mac(struct bce_softc *sc, u_int8_t *mac, unsigned long idx)
 1025 {
 1026         int             i;
u_int32_t rval;
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_LOW,
mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]);
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_HI,
mac[0] << 8 | mac[1] | 0x10000);    /* MAGIC */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL,
idx << 16 | 8);     /* MAGIC */
 1035         /* wait for write to complete */
 1036         for (i = 0; i < 100; i++) {
rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
BCE_FILT_CTL);
 1039                 if (!(rval & 0x80000000))       /* MAGIC */
 1040                         break;
delay(10);
 1042         }
 1043         if (i == 100) {
printf("%s: timed out writing pkt filter ctl\n",
sc->bce_dev.dv_xname);
 1046         }
 1047 }
 1049 /* Add a receive buffer to the indiciated descriptor. */
 1050 int
bce_add_rxbuf(struct bce_softc *sc, int idx)
 1052 {
 1053         struct mbuf    *m;
 1054         int             error;
MGETHDR(m, M_DONTWAIT, MT_DATA);
 1057         if (m == NULL)
 1058                 return (ENOBUFS);
MCLGET(m, M_DONTWAIT);
 1061         if ((m->m_flags & M_EXT) == 0) {
m_freem(m);
 1063                 return (ENOBUFS);
 1064         }
 1065         if (sc->bce_cdata.bce_rx_chain[idx] != NULL)
bus_dmamap_unload(sc->bce_dmatag,
sc->bce_cdata.bce_rx_map[idx]);
sc->bce_cdata.bce_rx_chain[idx] = m;
error = bus_dmamap_load(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx],
m->m_ext.ext_buf, m->m_ext.ext_size, NULL,
BUS_DMA_READ | BUS_DMA_NOWAIT);
 1074         if (error)
 1075                 return (error);
bus_dmamap_sync(sc->bce_dmatag, sc->bce_cdata.bce_rx_map[idx], 0,
sc->bce_cdata.bce_rx_map[idx]->dm_mapsize, BUS_DMASYNC_PREREAD);
BCE_INIT_RXDESC(sc, idx);
 1082         return (0);
 1084 }
 1086 /* Drain the receive queue. */
 1087 void
bce_rxdrain(struct bce_softc *sc)
 1089 {
 1090         int             i;
 1092         for (i = 0; i < BCE_NRXDESC; i++) {
 1093                 if (sc->bce_cdata.bce_rx_chain[i] != NULL) {
bus_dmamap_unload(sc->bce_dmatag,
sc->bce_cdata.bce_rx_map[i]);
m_freem(sc->bce_cdata.bce_rx_chain[i]);
sc->bce_cdata.bce_rx_chain[i] = NULL;
 1098                 }
 1099         }
 1100 }
 1102 /* Stop transmission on the interface */
 1103 void
bce_stop(struct ifnet *ifp, int disable)
 1105 {
 1106         struct bce_softc *sc = ifp->if_softc;
 1107         int             i;
u_int32_t val;
 1110         /* Stop the 1 second timer */
timeout_del(&sc->bce_timeout);
 1113         /* Mark the interface down and cancel the watchdog timer. */
ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
ifp->if_timer = 0;
 1117         /* Down the MII. */
mii_down(&sc->bce_mii);
 1120         /* Disable interrupts. */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_INT_MASK, 0);
sc->bce_intmask = 0;
delay(10);
 1125         /* Disable emac */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_ED);
 1127         for (i = 0; i < 200; i++) {
val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
BCE_ENET_CTL);
 1130                 if (!(val & EC_ED))
 1131                         break;
delay(10);
 1133         }
 1135         /* Stop the DMA */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXCTL, 0);
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0);
delay(10);
 1140         /* Release any queued transmit buffers. */
 1141         for (i = 0; i < BCE_NTXDESC; i++) {
 1142                 if (sc->bce_cdata.bce_tx_chain[i] != NULL) {
bus_dmamap_unload(sc->bce_dmatag,
sc->bce_cdata.bce_tx_map[i]);
m_freem(sc->bce_cdata.bce_tx_chain[i]);
sc->bce_cdata.bce_tx_chain[i] = NULL;
 1147                 }
 1148         }
 1150         /* drain receive queue */
 1151         if (disable)
bce_rxdrain(sc);
 1153 }
 1155 /* reset the chip */
 1156 void
bce_reset(struct bce_softc *sc)
 1158 {
u_int32_t val;
u_int32_t sbval;
 1161         int             i;
 1163         /* if SB core is up */
sbval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
BCE_SBTMSTATELOW);
 1166         if ((sbval & (SBTML_RESET | SBTML_REJ | SBTML_CLK)) == SBTML_CLK) {
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMAI_CTL,
 1168                     0);
 1170                 /* disable emac */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL,
EC_ED);
 1173                 for (i = 0; i < 200; i++) {
val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
BCE_ENET_CTL);
 1176                         if (!(val & EC_ED))
 1177                                 break;
delay(10);
 1179                 }
 1180                 if (i == 200)
printf("%s: timed out disabling ethernet mac\n",
sc->bce_dev.dv_xname);
 1184                 /* reset the dma engines */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_TXCTL, 0);
val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DMA_RXSTATUS);
 1187                 /* if error on receive, wait to go idle */
 1188                 if (val & RS_ERROR) {
 1189                         for (i = 0; i < 100; i++) {
val = bus_space_read_4(sc->bce_btag,
sc->bce_bhandle, BCE_DMA_RXSTATUS);
 1192                                 if (val & RS_DMA_IDLE)
 1193                                         break;
delay(10);
 1195                         }
 1196                         if (i == 100)
printf("%s: receive dma did not go idle after"
 1198                                     " error\n", sc->bce_dev.dv_xname);
 1199                 }
bus_space_write_4(sc->bce_btag, sc->bce_bhandle,
BCE_DMA_RXSTATUS, 0);
 1203                 /* reset ethernet mac */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL,
EC_ES);
 1206                 for (i = 0; i < 200; i++) {
val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
BCE_ENET_CTL);
 1209                         if (!(val & EC_ES))
 1210                                 break;
delay(10);
 1212                 }
 1213                 if (i == 200)
printf("%s: timed out resetting ethernet mac\n",
sc->bce_dev.dv_xname);
 1216         } else {
u_int32_t reg_win;
 1219                 /* remap the pci registers to the Sonics config registers */
 1221                 /* save the current map, so it can be restored */
reg_win = pci_conf_read(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag,
BCE_REG_WIN);
 1224                 /* set register window to Sonics registers */
pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag,
BCE_REG_WIN, BCE_SONICS_WIN);
 1228                 /* enable SB to PCI interrupt */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBINTVEC,
bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
BCE_SBINTVEC) |
SBIV_ENET0);
 1234                 /* enable prefetch and bursts for sonics-to-pci translation 2 */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SPCI_TR2,
bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
BCE_SPCI_TR2) |
SBTOPCI_PREF | SBTOPCI_BURST);
 1240                 /* restore to ethernet register space */
pci_conf_write(sc->bce_pa.pa_pc, sc->bce_pa.pa_tag, BCE_REG_WIN,
reg_win);
 1243         }
 1245         /* disable SB core if not in reset */
 1246         if (!(sbval & SBTML_RESET)) {
 1248                 /* set the reject bit */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle,
BCE_SBTMSTATELOW, SBTML_REJ | SBTML_CLK);
 1251                 for (i = 0; i < 200; i++) {
val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
BCE_SBTMSTATELOW);
 1254                         if (val & SBTML_REJ)
 1255                                 break;
delay(1);
 1257                 }
 1258                 if (i == 200)
printf("%s: while resetting core, reject did not set\n",
sc->bce_dev.dv_xname);
 1261                 /* wait until busy is clear */
 1262                 for (i = 0; i < 200; i++) {
val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
BCE_SBTMSTATEHI);
 1265                         if (!(val & 0x4))
 1266                                 break;
delay(1);
 1268                 }
 1269                 if (i == 200)
printf("%s: while resetting core, busy did not clear\n",
sc->bce_dev.dv_xname);
 1272                 /* set reset and reject while enabling the clocks */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle,
BCE_SBTMSTATELOW,
SBTML_FGC | SBTML_CLK | SBTML_REJ | SBTML_RESET);
val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
BCE_SBTMSTATELOW);
delay(10);
bus_space_write_4(sc->bce_btag, sc->bce_bhandle,
BCE_SBTMSTATELOW, SBTML_REJ | SBTML_RESET);
delay(1);
 1282         }
 1283         /* enable clock */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW,
SBTML_FGC | SBTML_CLK | SBTML_RESET);
val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW);
delay(1);
 1289         /* clear any error bits that may be on */
val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI);
 1291         if (val & 1)
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATEHI,
 1293                     0);
val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE);
 1295         if (val & SBIM_ERRORBITS)
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBIMSTATE,
val & ~SBIM_ERRORBITS);
 1299         /* clear reset and allow it to propagate throughout the core */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW,
SBTML_FGC | SBTML_CLK);
val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW);
delay(1);
 1305         /* leave clock enabled */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW,
SBTML_CLK);
val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_SBTMSTATELOW);
delay(1);
 1311         /* initialize MDC preamble, frequency */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_CTL, 0x8d);     /* MAGIC */
 1314         /* enable phy, differs for internal, and external */
val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL);
 1316         if (!(val & BCE_DC_IP)) {
 1317                 /* select external phy */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_ENET_CTL, EC_EP);
 1319         } else if (val & BCE_DC_ER) {   /* internal, clear reset bit if on */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_DEVCTL,
val & ~BCE_DC_ER);
delay(100);
 1323         }
 1324 }
 1326 /* Set up the receive filter. */
 1327 void
bce_set_filter(struct ifnet *ifp)
 1329 {
 1330         struct bce_softc *sc = ifp->if_softc;
 1332         if (ifp->if_flags & IFF_PROMISC) {
ifp->if_flags |= IFF_ALLMULTI;
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL,
bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL)
 1336                     | ERC_PE);
 1337         } else {
ifp->if_flags &= ~IFF_ALLMULTI;
 1340                 /* turn off promiscuous */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL,
bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
BCE_RX_CTL) & ~ERC_PE);
 1345                 /* enable/disable broadcast */
 1346                 if (ifp->if_flags & IFF_BROADCAST)
bus_space_write_4(sc->bce_btag, sc->bce_bhandle,
BCE_RX_CTL, bus_space_read_4(sc->bce_btag,
sc->bce_bhandle, BCE_RX_CTL) & ~ERC_DB);
 1350                 else
bus_space_write_4(sc->bce_btag, sc->bce_bhandle,
BCE_RX_CTL, bus_space_read_4(sc->bce_btag,
sc->bce_bhandle, BCE_RX_CTL) | ERC_DB);
 1355                 /* disable the filter */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL,
 1357                     0);
 1359                 /* add our own address */
bce_add_mac(sc, sc->bce_ac.ac_enaddr, 0);
 1362                 /* for now accept all multicast */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL,
bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_RX_CTL) |
ERC_AM);
ifp->if_flags |= IFF_ALLMULTI;
 1368                 /* enable the filter */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_FILT_CTL,
bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
BCE_FILT_CTL) | 1);
 1372         }
 1373 }
 1375 /* Read a PHY register on the MII. */
 1376 int
bce_mii_read(struct device *self, int phy, int reg)
 1378 {
 1379         struct bce_softc *sc = (struct bce_softc *) self;
 1380         int             i;
u_int32_t val;
 1383         /* clear mii_int */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS, BCE_MIINTR);
 1386         /* Read the PHY register */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM,
 1388             (MII_COMMAND_READ << 28) | (MII_COMMAND_START << 30) |      /* MAGIC */
 1389             (MII_COMMAND_ACK << 16) | BCE_MIPHY(phy) | BCE_MIREG(reg)); /* MAGIC */
 1391         for (i = 0; i < BCE_TIMEOUT; i++) {
val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS);
 1393                 if (val & BCE_MIINTR)
 1394                         break;
delay(10);
 1396         }
val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM);
 1398         if (i == BCE_TIMEOUT) {
printf("%s: PHY read timed out reading phy %d, reg %d, val = "
 1400                     "0x%08x\n", sc->bce_dev.dv_xname, phy, reg, val);
 1401                 return (0);
 1402         }
 1403         return (val & BCE_MICOMM_DATA);
 1404 }
 1406 /* Write a PHY register on the MII */
 1407 void
bce_mii_write(struct device *self, int phy, int reg, int val)
 1409 {
 1410         struct bce_softc *sc = (struct bce_softc *) self;
 1411         int             i;
u_int32_t rval;
 1414         /* clear mii_int */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_STS,
BCE_MIINTR);
 1418         /* Write the PHY register */
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM,
 1420             (MII_COMMAND_WRITE << 28) | (MII_COMMAND_START << 30) |     /* MAGIC */
 1421             (MII_COMMAND_ACK << 16) | (val & BCE_MICOMM_DATA) | /* MAGIC */
BCE_MIPHY(phy) | BCE_MIREG(reg));
 1424         /* wait for write to complete */
 1425         for (i = 0; i < BCE_TIMEOUT; i++) {
rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle,
BCE_MI_STS);
 1428                 if (rval & BCE_MIINTR)
 1429                         break;
delay(10);
 1431         }
rval = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_MI_COMM);
 1433         if (i == BCE_TIMEOUT) {
printf("%s: PHY timed out writing phy %d, reg %d, val "
 1435                     "= 0x%08x\n", sc->bce_dev.dv_xname, phy, reg, val);
 1436         }
 1437 }
 1439 /* sync hardware duplex mode to software state */
 1440 void
bce_statchg(struct device *self)
 1442 {
 1443         struct bce_softc *sc = (struct bce_softc *) self;
u_int32_t reg;
 1446         /* if needed, change register to match duplex mode */
reg = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL);
 1448         if (sc->bce_mii.mii_media_active & IFM_FDX && !(reg & EXC_FD))
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL,
reg | EXC_FD);
 1451         else if (!(sc->bce_mii.mii_media_active & IFM_FDX) && reg & EXC_FD)
bus_space_write_4(sc->bce_btag, sc->bce_bhandle, BCE_TX_CTL,
reg & ~EXC_FD);
 1455         /*
 1456          * Enable activity led.
 1457          * XXX This should be in a phy driver, but not currently.
 1458          */
bce_mii_write((struct device *) sc, 1, 26,      /* MAGIC */
bce_mii_read((struct device *) sc, 1, 26) & 0x7fff);        /* MAGIC */
 1461         /* enable traffic meter led mode */
bce_mii_write((struct device *) sc, 1, 26,      /* MAGIC */
bce_mii_read((struct device *) sc, 1, 27) | (1 << 6));      /* MAGIC */
 1464 }
 1466 /* Set hardware to newly-selected media */
 1467 int
bce_mediachange(struct ifnet *ifp)
 1469 {
 1470         struct bce_softc *sc = ifp->if_softc;
 1472         if (ifp->if_flags & IFF_UP)
mii_mediachg(&sc->bce_mii);
 1474         return (0);
 1475 }
 1477 /* Get the current interface media status */
 1478 void
bce_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
 1480 {
 1481         struct bce_softc *sc = ifp->if_softc;
mii_pollstat(&sc->bce_mii);
ifmr->ifm_active = sc->bce_mii.mii_media_active;
ifmr->ifm_status = sc->bce_mii.mii_media_status;
 1486 }
 1488 /* One second timer, checks link status */
 1489 void
bce_tick(void *v)
 1491 {
 1492         struct bce_softc *sc = v;
 1494         /* Tick the MII. */
mii_tick(&sc->bce_mii);
timeout_add(&sc->bce_timeout, hz);
 1498 }