1 /* $OpenBSD: if_bcereg.h,v 1.3 2006/11/08 01:32:00 brad Exp $ */
2 /* $NetBSD: if_bcereg.h,v 1.3 2003/09/29 01:53:02 mrg Exp $ */
3
4 /*
5 * Copyright (c) 2003 Clifford Wright. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31 /* Broadcom BCM440x */
32
33 /* PCI registers defined in the PCI 2.2 spec. */
34 #define BCE_PCI_BAR0 0x10
35
36 /* Sonics SB register access */
37 #define BCE_REG_WIN 0x80
38 #define BCE_SONICS_WIN 0x18002000
39
40 /* Sonics PCI control */
41 #define BCE_SPCI_TR2 0x0108 /* Sonics to PCI translation
42 * 2 */
43 /* bit defines */
44 #define SBTOPCI_PREF 0x4 /* prefetch enable */
45 #define SBTOPCI_BURST 0x8 /* burst enable */
46 #define BCE_SBINTVEC 0x0f94
47 /* interrupt bits */
48 #define SBIV_ENET0 0x02 /* enable for enet 0 */
49 #define SBIV_ENET1 0x40 /* enable for enet 1 */
50
51
52 /* Host Interface Registers */
53
54 #define BCE_DEVCTL 0x0000 /* device control */
55 /* device control bits */
56 #define BCE_DC_IP 0x00000400 /* internal phy present */
57 #define BCE_DC_ER 0x00008000 /* ephy reset */
58 /* Interrupt Control */
59 #define BCE_INT_STS 0x0020
60 #define BCE_INT_MASK 0x0024
61 /* bits for both status, and mask */
62 #define I_TO 0x00000080 /* general timeout */
63 #define I_PC 0x00000400 /* descriptor error */
64 #define I_PD 0x00000800 /* data error */
65 #define I_DE 0x00001000 /* desc. protocol error */
66 #define I_RU 0x00002000 /* rx desc. underflow */
67 #define I_RO 0x00004000 /* rx fifo overflow */
68 #define I_XU 0x00008000 /* tx fifo underflow */
69 #define I_RI 0x00010000 /* receive interrupt */
70 #define I_XI 0x01000000 /* transmit interrupt */
71
72 /* Ethernet MAC Control */
73 #define BCE_MACCTL 0x00A8 /* ethernet mac control */
74 /* mac control bits */
75 #define BCE_EMC_CRC32_ENAB 0x00000001 /* crc32 generation */
76 #define BCE_EMC_PDOWN 0x00000004 /* PHY powerdown */
77 #define BCE_EMC_EDET 0x00000008 /* PHY energy detect */
78 #define BCE_EMC_LED 0x000000e0 /* PHY LED control */
79
80 /* DMA Interrupt control */
81 #define BCE_DMAI_CTL 0x0100
82
83 /* DMA registers */
84 #define BCE_DMA_TXCTL 0x0200 /* transmit control */
85 /* transmit control bits */
86 #define XC_XE 0x1 /* transmit enable */
87 #define XC_LE 0x4 /* loopback enable */
88 #define BCE_DMA_TXADDR 0x0204 /* tx ring base address */
89 #define BCE_DMA_DPTR 0x0208 /* last tx descriptor */
90 #define BCE_DMA_TXSTATUS 0x020C /* active desc, etc */
91 #define BCE_DMA_RXCTL 0x0210 /* enable, etc */
92 #define BCE_DMA_RXADDR 0x0214 /* rx ring base address */
93 #define BCE_DMA_RXDPTR 0x0218 /* last descriptor */
94 #define BCE_DMA_RXSTATUS 0x021C /* active desc, etc */
95 /* receive status bits */
96 #define RS_CD_MASK 0x0fff /* current descriptor pointer */
97 #define RS_DMA_IDLE 0x2000 /* DMA is idle */
98 #define RS_ERROR 0xf0000 /* had an error */
99
100 /* Ethernet MAC control registers */
101 #define BCE_RX_CTL 0x0400 /* receive config */
102 /* config bits */
103 #define ERC_DB 0x00000001 /* disable broadcast */
104 #define ERC_AM 0x00000002 /* rx all multicast */
105 #define ERC_PE 0x00000008 /* promiscuous enable */
106
107 #define BCE_RX_MAX 0x0404 /* max packet length */
108 #define BCE_TX_MAX 0x0408
109 #define BCE_MI_CTL 0x0410
110 #define BCE_MI_COMM 0x0414
111 #define BCE_MI_STS 0x041C
112 /* mii status bits */
113 #define BCE_MIINTR 0x00000001 /* mii mdio interrupt */
114
115 #define BCE_FILT_LOW 0x0420 /* mac low 4 bytes */
116 #define BCE_FILT_HI 0x0424 /* mac hi 2 bytes */
117 #define BCE_FILT_CTL 0x0428 /* packet filter ctrl */
118 #define BCE_ENET_CTL 0x042C
119 /* bits for mac control */
120 #define EC_EE 0x00000001 /* emac enable */
121 #define EC_ED 0x00000002 /* disable emac */
122 #define EC_ES 0x00000004 /* soft reset emac */
123 #define EC_EP 0x00000008 /* external phy */
124 #define BCE_TX_CTL 0x0430
125 /* bits for transmit control */
126 #define EXC_FD 0x00000001 /* full duplex */
127 #define BCE_TX_WATER 0x0434 /* tx watermark */
128
129 /* statistics counters */
130 #define BCE_RX_PKTS 0x058C
131
132 /* SiliconBackplane registers */
133 #define BCE_SBIMSTATE 0x0f90
134 #define BCE_SBTMSTATELOW 0x0f98
135 #define BCE_SBTMSTATEHI 0x0f9C
136 #define SBTML_RESET 0x1 /* reset */
137 #define SBTML_REJ 0x2 /* reject */
138 #define SBTML_CLK 0x10000 /* clock enable */
139 #define SBTML_FGC 0x20000 /* force gated clocks on */
140
141 /* MI communication register */
142 #define BCE_MICOMM_DATA 0x0000FFFF
143
144 #define BCE_MIREG(x) ((x & 0x1F) << 18)
145 #define BCE_MIPHY(x) ((x & 0x1F) << 23)
146
147 /* SPROM constants */
148 #define BCE_SPROM_BASE 0x1000
149 #define BCE_PHY (BCE_SPROM_BASE + 0x5A) /* MII Address */
150 #define BCE_ENET0 (BCE_SPROM_BASE + 0x4F)
151 #define BCE_ENET1 (BCE_SPROM_BASE + 0x4E)
152 #define BCE_ENET2 (BCE_SPROM_BASE + 0x51)
153 #define BCE_ENET3 (BCE_SPROM_BASE + 0x50)
154 #define BCE_ENET4 (BCE_SPROM_BASE + 0x53)
155 #define BCE_ENET5 (BCE_SPROM_BASE + 0x52)
156
157 #define SBIM_INBAND_ERROR 0x20000
158 #define SBIM_TIMEOUT 0x40000
159 #define SBIM_ERRORBITS (SBIM_INBAND_ERROR|SBIM_TIMEOUT)