mii_status_reg   2312 dev/pci/if_em_hw.c     uint16_t mii_status_reg;
mii_status_reg   2444 dev/pci/if_em_hw.c         mii_status_reg = 0;
mii_status_reg   2451 dev/pci/if_em_hw.c             ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
mii_status_reg   2455 dev/pci/if_em_hw.c             ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
mii_status_reg   2459 dev/pci/if_em_hw.c             if (mii_status_reg & MII_SR_LINK_STATUS) break;
mii_status_reg   2474 dev/pci/if_em_hw.c             if (mii_status_reg & MII_SR_LINK_STATUS) break;
mii_status_reg   2479 dev/pci/if_em_hw.c             ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
mii_status_reg   2483 dev/pci/if_em_hw.c             ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
mii_status_reg   2715 dev/pci/if_em_hw.c     uint16_t mii_status_reg;
mii_status_reg   2748 dev/pci/if_em_hw.c         ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
mii_status_reg   2751 dev/pci/if_em_hw.c         ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
mii_status_reg   2755 dev/pci/if_em_hw.c         if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
mii_status_reg   7061 dev/pci/if_em_hw.c     uint16_t mii_status_reg;
mii_status_reg   7085 dev/pci/if_em_hw.c         ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
mii_status_reg   7089 dev/pci/if_em_hw.c         ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
mii_status_reg   7093 dev/pci/if_em_hw.c         if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
mii_status_reg   7128 dev/pci/if_em_hw.c         ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
mii_status_reg   7132 dev/pci/if_em_hw.c         ret_val = em_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
mii_status_reg   7136 dev/pci/if_em_hw.c         if (mii_status_reg & MII_SR_LINK_STATUS) break;