reg_data          880 dev/pci/if_em_hw.c     uint32_t reg_data;
reg_data          890 dev/pci/if_em_hw.c             reg_data = E1000_READ_REG(hw, STATUS);
reg_data          891 dev/pci/if_em_hw.c             reg_data &= ~0x80000000;
reg_data          892 dev/pci/if_em_hw.c             E1000_WRITE_REG(hw, STATUS, reg_data);
reg_data         1011 dev/pci/if_em_hw.c         reg_data = E1000_READ_REG(hw, TCTL);
reg_data         1012 dev/pci/if_em_hw.c         reg_data |= E1000_TCTL_RTLC;
reg_data         1013 dev/pci/if_em_hw.c         E1000_WRITE_REG(hw, TCTL, reg_data);
reg_data         1016 dev/pci/if_em_hw.c         reg_data = E1000_READ_REG(hw, TCTL_EXT);
reg_data         1017 dev/pci/if_em_hw.c         reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
reg_data         1018 dev/pci/if_em_hw.c         reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
reg_data         1019 dev/pci/if_em_hw.c         E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
reg_data         1022 dev/pci/if_em_hw.c         reg_data = E1000_READ_REG(hw, TIPG);
reg_data         1023 dev/pci/if_em_hw.c         reg_data &= ~E1000_TIPG_IPGT_MASK;
reg_data         1024 dev/pci/if_em_hw.c         reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
reg_data         1025 dev/pci/if_em_hw.c         E1000_WRITE_REG(hw, TIPG, reg_data);
reg_data         1027 dev/pci/if_em_hw.c         reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
reg_data         1028 dev/pci/if_em_hw.c         reg_data &= ~0x00100000;
reg_data         1029 dev/pci/if_em_hw.c         E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
reg_data         1614 dev/pci/if_em_hw.c     uint32_t reg_data;
reg_data         1701 dev/pci/if_em_hw.c         reg_data = E1000_READ_REG(hw, CTRL_EXT);
reg_data         1702 dev/pci/if_em_hw.c         reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
reg_data         1703 dev/pci/if_em_hw.c         E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
reg_data         1976 dev/pci/if_em_hw.c     uint16_t reg_data;
reg_data         1989 dev/pci/if_em_hw.c         ret_val = em_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
reg_data         1992 dev/pci/if_em_hw.c         reg_data |= 0x3F;
reg_data         1993 dev/pci/if_em_hw.c         ret_val = em_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
reg_data         2008 dev/pci/if_em_hw.c         reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
reg_data         2009 dev/pci/if_em_hw.c         reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
reg_data         2011 dev/pci/if_em_hw.c                                        reg_data);
reg_data         2089 dev/pci/if_em_hw.c     uint16_t reg_data;
reg_data         2093 dev/pci/if_em_hw.c     reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
reg_data         2095 dev/pci/if_em_hw.c                                    reg_data);
reg_data         2105 dev/pci/if_em_hw.c     ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
reg_data         2111 dev/pci/if_em_hw.c         reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
reg_data         2113 dev/pci/if_em_hw.c         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
reg_data         2115 dev/pci/if_em_hw.c     ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
reg_data         2124 dev/pci/if_em_hw.c     uint16_t reg_data;
reg_data         2129 dev/pci/if_em_hw.c     reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
reg_data         2131 dev/pci/if_em_hw.c                                    reg_data);
reg_data         2141 dev/pci/if_em_hw.c     ret_val = em_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
reg_data         2146 dev/pci/if_em_hw.c     reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
reg_data         2147 dev/pci/if_em_hw.c     ret_val = em_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
reg_data         8133 dev/pci/if_em_hw.c     uint16_t word_addr, reg_data, reg_addr;
reg_data         8141 dev/pci/if_em_hw.c         ret_val = em_read_eeprom(hw, (word_addr + i*2), 1, &reg_data);
reg_data         8153 dev/pci/if_em_hw.c         ret_val = em_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data);
reg_data         8172 dev/pci/if_em_hw.c     uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop;
reg_data         8178 dev/pci/if_em_hw.c     reg_data = E1000_READ_REG(hw, FEXTNVM);
reg_data         8179 dev/pci/if_em_hw.c     if (!(reg_data & FEXTNVM_SW_CONFIG))
reg_data         8185 dev/pci/if_em_hw.c         reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE;
reg_data         8188 dev/pci/if_em_hw.c     } while ((!reg_data) && (loop < 50));
reg_data         8191 dev/pci/if_em_hw.c     reg_data = E1000_READ_REG(hw, STATUS);
reg_data         8192 dev/pci/if_em_hw.c     reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
reg_data         8193 dev/pci/if_em_hw.c     E1000_WRITE_REG(hw, STATUS, reg_data);
reg_data         8197 dev/pci/if_em_hw.c     reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
reg_data         8198 dev/pci/if_em_hw.c     if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
reg_data         8199 dev/pci/if_em_hw.c         reg_data = E1000_READ_REG(hw, EXTCNF_SIZE);
reg_data         8200 dev/pci/if_em_hw.c         cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
reg_data         8203 dev/pci/if_em_hw.c             reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
reg_data         8204 dev/pci/if_em_hw.c             cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;