reg_tarc0         767 dev/pci/if_em_hw.c         uint32_t reg_tarc0, reg_tarc1;
reg_tarc0         771 dev/pci/if_em_hw.c         reg_tarc0 = E1000_READ_REG(hw, TARC0);
reg_tarc0         772 dev/pci/if_em_hw.c         reg_tarc0 &= ~0x78000000;           /* Clear bits 30, 29, 28, and 27 */
reg_tarc0         791 dev/pci/if_em_hw.c                 reg_tarc0 |= 0x07800000;    /* Set TARC0 bits 23-26 */
reg_tarc0         815 dev/pci/if_em_hw.c                     reg_tarc0 &= ~0x00100000;   /* Clear bit 20 */
reg_tarc0         831 dev/pci/if_em_hw.c                     reg_tarc0 |= 0x30000000;    /* Set TARC0 bits 29 and 28 */
reg_tarc0         836 dev/pci/if_em_hw.c                 reg_tarc0 |= 0x0d800000;    /* Set TARC0 bits 23, 24, 26, 27 */
reg_tarc0         854 dev/pci/if_em_hw.c         E1000_WRITE_REG(hw, TARC0, reg_tarc0);