fc 665 dev/ic/pdq.c pdq_uint32_t fc, datalen, pdulen, segcnt;
fc 675 dev/ic/pdq.c fc = dataptr[PDQ_RX_FC_OFFSET];
fc 676 dev/ic/pdq.c switch (fc & (PDQ_FDDIFC_C|PDQ_FDDIFC_L|PDQ_FDDIFC_F)) {
fc 693 dev/ic/pdq.c PDQ_PRINTF(("discard: bad fc 0x%x\n", fc));
fc 1756 dev/isa/gus.c unsigned int fc;
fc 1766 dev/isa/gus.c fc = (unsigned int)(((f << 9L) + (temp >> 1L)) / temp);
fc 1768 dev/isa/gus.c fc <<= 1;
fc 1777 dev/isa/gus.c bus_space_write_2(iot, ioh2, GUS_DATA_LOW, fc);
fc 1614 dev/pci/if_em.c sc->hw.fc = E1000_FC_FULL;
fc 1143 dev/pci/if_em_hw.c if (hw->fc == E1000_FC_DEFAULT) {
fc 1147 dev/pci/if_em_hw.c hw->fc = E1000_FC_FULL;
fc 1157 dev/pci/if_em_hw.c hw->fc = E1000_FC_NONE;
fc 1160 dev/pci/if_em_hw.c hw->fc = E1000_FC_TX_PAUSE;
fc 1162 dev/pci/if_em_hw.c hw->fc = E1000_FC_FULL;
fc 1172 dev/pci/if_em_hw.c hw->fc &= (~E1000_FC_TX_PAUSE);
fc 1175 dev/pci/if_em_hw.c hw->fc &= (~E1000_FC_RX_PAUSE);
fc 1177 dev/pci/if_em_hw.c hw->original_fc = hw->fc;
fc 1179 dev/pci/if_em_hw.c DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
fc 1227 dev/pci/if_em_hw.c if (!(hw->fc & E1000_FC_TX_PAUSE)) {
fc 1313 dev/pci/if_em_hw.c switch (hw->fc) {
fc 2249 dev/pci/if_em_hw.c switch (hw->fc) {
fc 2319 dev/pci/if_em_hw.c hw->fc = E1000_FC_NONE;
fc 2321 dev/pci/if_em_hw.c DEBUGOUT1("hw->fc = %d\n", hw->fc);
fc 2672 dev/pci/if_em_hw.c switch (hw->fc) {
fc 2814 dev/pci/if_em_hw.c hw->fc = E1000_FC_FULL;
fc 2817 dev/pci/if_em_hw.c hw->fc = E1000_FC_RX_PAUSE;
fc 2833 dev/pci/if_em_hw.c hw->fc = E1000_FC_TX_PAUSE;
fc 2848 dev/pci/if_em_hw.c hw->fc = E1000_FC_RX_PAUSE;
fc 2874 dev/pci/if_em_hw.c hw->fc = E1000_FC_NONE;
fc 2877 dev/pci/if_em_hw.c hw->fc = E1000_FC_RX_PAUSE;
fc 2892 dev/pci/if_em_hw.c hw->fc = E1000_FC_NONE;
fc 1378 dev/pci/if_em_hw.h uint32_t fc;
fc 190 dev/pci/if_ixgb.c sc->hw.fc.high_water = FCRTH;
fc 191 dev/pci/if_ixgb.c sc->hw.fc.low_water = FCRTL;
fc 192 dev/pci/if_ixgb.c sc->hw.fc.pause_time = FCPAUSE;
fc 193 dev/pci/if_ixgb.c sc->hw.fc.send_xon = TRUE;
fc 194 dev/pci/if_ixgb.c sc->hw.fc.type = FLOW_CONTROL;
fc 669 dev/pci/ixgb_hw.c switch(hw->fc.type) {
fc 682 dev/pci/ixgb_hw.c pap_reg = hw->fc.pause_time;
fc 688 dev/pci/ixgb_hw.c pap_reg = hw->fc.pause_time;
fc 709 dev/pci/ixgb_hw.c if(!(hw->fc.type & ixgb_fc_tx_pause)) {
fc 716 dev/pci/ixgb_hw.c if(hw->fc.send_xon) {
fc 718 dev/pci/ixgb_hw.c (hw->fc.low_water | IXGB_FCRTL_XONE));
fc 720 dev/pci/ixgb_hw.c IXGB_WRITE_REG(hw, FCRTL, hw->fc.low_water);
fc 722 dev/pci/ixgb_hw.c IXGB_WRITE_REG(hw, FCRTH, hw->fc.high_water);
fc 723 dev/pci/ixgb_hw.h struct ixgb_fc fc; /* Flow control parameters */
fc 200 net/zlib.c } fc;
fc 207 net/zlib.c #define Freq fc.freq
fc 208 net/zlib.c #define Code fc.code
fc 473 netbt/rfcomm_upper.c struct rfcomm_fc_info *fc;
fc 481 netbt/rfcomm_upper.c fc = addr;
fc 482 netbt/rfcomm_upper.c memset(fc, 0, sizeof(*fc));
fc 483 netbt/rfcomm_upper.c fc->lmodem = dlc->rd_lmodem;
fc 484 netbt/rfcomm_upper.c fc->rmodem = dlc->rd_rmodem;
fc 485 netbt/rfcomm_upper.c fc->tx_cred = max(dlc->rd_txcred, 0xff);
fc 486 netbt/rfcomm_upper.c fc->rx_cred = max(dlc->rd_rxcred, 0xff);
fc 489 netbt/rfcomm_upper.c fc->cfc = 1;
fc 491 netbt/rfcomm_upper.c return sizeof(*fc);