phy_data 148 dev/pci/if_em_hw.c uint16_t phy_data);
phy_data 150 dev/pci/if_em_hw.c uint16_t *phy_data);
phy_data 1406 dev/pci/if_em_hw.c uint16_t phy_data;
phy_data 1442 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
phy_data 1443 dev/pci/if_em_hw.c phy_data |= 0x00000008;
phy_data 1444 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
phy_data 1466 dev/pci/if_em_hw.c uint16_t phy_data;
phy_data 1506 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
phy_data 1513 dev/pci/if_em_hw.c phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX);
phy_data 1518 dev/pci/if_em_hw.c phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
phy_data 1522 dev/pci/if_em_hw.c phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
phy_data 1525 dev/pci/if_em_hw.c phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
phy_data 1529 dev/pci/if_em_hw.c phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
phy_data 1533 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
phy_data 1553 dev/pci/if_em_hw.c &phy_data);
phy_data 1556 dev/pci/if_em_hw.c phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
phy_data 1558 dev/pci/if_em_hw.c phy_data);
phy_data 1562 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
phy_data 1565 dev/pci/if_em_hw.c phy_data &= ~CR_1000T_MS_ENABLE;
phy_data 1566 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
phy_data 1571 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
phy_data 1576 dev/pci/if_em_hw.c hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
phy_data 1577 dev/pci/if_em_hw.c ((phy_data & CR_1000T_MS_VALUE) ?
phy_data 1584 dev/pci/if_em_hw.c phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
phy_data 1587 dev/pci/if_em_hw.c phy_data |= CR_1000T_MS_ENABLE;
phy_data 1588 dev/pci/if_em_hw.c phy_data &= ~(CR_1000T_MS_VALUE);
phy_data 1591 dev/pci/if_em_hw.c phy_data &= ~CR_1000T_MS_ENABLE;
phy_data 1596 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
phy_data 1613 dev/pci/if_em_hw.c uint16_t phy_data;
phy_data 1622 dev/pci/if_em_hw.c &phy_data);
phy_data 1626 dev/pci/if_em_hw.c phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
phy_data 1628 dev/pci/if_em_hw.c phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
phy_data 1631 dev/pci/if_em_hw.c phy_data);
phy_data 1642 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
phy_data 1646 dev/pci/if_em_hw.c phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
phy_data 1650 dev/pci/if_em_hw.c phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
phy_data 1653 dev/pci/if_em_hw.c phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
phy_data 1657 dev/pci/if_em_hw.c phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
phy_data 1667 dev/pci/if_em_hw.c phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
phy_data 1669 dev/pci/if_em_hw.c phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
phy_data 1670 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
phy_data 1691 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
phy_data 1695 dev/pci/if_em_hw.c phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
phy_data 1696 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
phy_data 1706 dev/pci/if_em_hw.c &phy_data);
phy_data 1716 dev/pci/if_em_hw.c phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
phy_data 1718 dev/pci/if_em_hw.c phy_data);
phy_data 1723 dev/pci/if_em_hw.c &phy_data);
phy_data 1727 dev/pci/if_em_hw.c phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
phy_data 1729 dev/pci/if_em_hw.c phy_data);
phy_data 1739 dev/pci/if_em_hw.c &phy_data);
phy_data 1742 dev/pci/if_em_hw.c phy_data |= GG82563_ICR_DIS_PADDING;
phy_data 1744 dev/pci/if_em_hw.c phy_data);
phy_data 1761 dev/pci/if_em_hw.c uint16_t phy_data;
phy_data 1769 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
phy_data 1773 dev/pci/if_em_hw.c phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
phy_data 1782 dev/pci/if_em_hw.c phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
phy_data 1786 dev/pci/if_em_hw.c phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
phy_data 1789 dev/pci/if_em_hw.c phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
phy_data 1792 dev/pci/if_em_hw.c phy_data |= M88E1000_PSCR_AUTO_X_1000T;
phy_data 1796 dev/pci/if_em_hw.c phy_data |= M88E1000_PSCR_AUTO_X_MODE;
phy_data 1806 dev/pci/if_em_hw.c phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
phy_data 1808 dev/pci/if_em_hw.c phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
phy_data 1809 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
phy_data 1817 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
phy_data 1821 dev/pci/if_em_hw.c phy_data |= M88E1000_EPSCR_TX_CLK_25;
phy_data 1826 dev/pci/if_em_hw.c phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
phy_data 1827 dev/pci/if_em_hw.c phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
phy_data 1829 dev/pci/if_em_hw.c M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
phy_data 1834 dev/pci/if_em_hw.c phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
phy_data 1836 dev/pci/if_em_hw.c phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
phy_data 1839 dev/pci/if_em_hw.c M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
phy_data 1865 dev/pci/if_em_hw.c uint16_t phy_data;
phy_data 1895 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data);
phy_data 1899 dev/pci/if_em_hw.c phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
phy_data 1900 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data);
phy_data 1975 dev/pci/if_em_hw.c uint16_t phy_data;
phy_data 2056 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
phy_data 2059 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
phy_data 2063 dev/pci/if_em_hw.c if (phy_data & MII_SR_LINK_STATUS) {
phy_data 2313 dev/pci/if_em_hw.c uint16_t phy_data;
phy_data 2383 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
phy_data 2390 dev/pci/if_em_hw.c phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
phy_data 2391 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
phy_data 2395 dev/pci/if_em_hw.c DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
phy_data 2401 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
phy_data 2405 dev/pci/if_em_hw.c phy_data &= ~IFE_PMC_AUTO_MDIX;
phy_data 2406 dev/pci/if_em_hw.c phy_data &= ~IFE_PMC_FORCE_MDIX;
phy_data 2408 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
phy_data 2415 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
phy_data 2419 dev/pci/if_em_hw.c phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
phy_data 2420 dev/pci/if_em_hw.c phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
phy_data 2422 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
phy_data 2494 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
phy_data 2498 dev/pci/if_em_hw.c phy_data |= M88E1000_EPSCR_TX_CLK_25;
phy_data 2499 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
phy_data 2506 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
phy_data 2510 dev/pci/if_em_hw.c phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
phy_data 2511 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
phy_data 2526 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
phy_data 2530 dev/pci/if_em_hw.c phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
phy_data 2533 dev/pci/if_em_hw.c phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
phy_data 2535 dev/pci/if_em_hw.c phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
phy_data 2538 dev/pci/if_em_hw.c phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
phy_data 2540 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
phy_data 2590 dev/pci/if_em_hw.c uint16_t phy_data;
phy_data 2609 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
phy_data 2613 dev/pci/if_em_hw.c if (phy_data & M88E1000_PSSR_DPLX)
phy_data 2623 dev/pci/if_em_hw.c if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
phy_data 2625 dev/pci/if_em_hw.c else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
phy_data 2926 dev/pci/if_em_hw.c uint16_t phy_data;
phy_data 2960 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
phy_data 2963 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
phy_data 2967 dev/pci/if_em_hw.c if (phy_data & MII_SR_LINK_STATUS) {
phy_data 3159 dev/pci/if_em_hw.c uint16_t phy_data;
phy_data 3194 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
phy_data 3198 dev/pci/if_em_hw.c if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
phy_data 3201 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
phy_data 3204 dev/pci/if_em_hw.c if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) ||
phy_data 3205 dev/pci/if_em_hw.c (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
phy_data 3239 dev/pci/if_em_hw.c uint16_t phy_data;
phy_data 3249 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
phy_data 3252 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
phy_data 3255 dev/pci/if_em_hw.c if (phy_data & MII_SR_AUTONEG_COMPLETE) {
phy_data 3487 dev/pci/if_em_hw.c uint16_t *phy_data)
phy_data 3537 dev/pci/if_em_hw.c phy_data);
phy_data 3545 dev/pci/if_em_hw.c uint16_t *phy_data)
phy_data 3583 dev/pci/if_em_hw.c *phy_data = (uint16_t) mdic;
phy_data 3611 dev/pci/if_em_hw.c *phy_data = em_shift_in_mdi_bits(hw);
phy_data 3625 dev/pci/if_em_hw.c uint16_t phy_data)
phy_data 3675 dev/pci/if_em_hw.c phy_data);
phy_data 3683 dev/pci/if_em_hw.c uint16_t phy_data)
phy_data 3701 dev/pci/if_em_hw.c mdic = (((uint32_t) phy_data) |
phy_data 3735 dev/pci/if_em_hw.c mdic |= (uint32_t) phy_data;
phy_data 3905 dev/pci/if_em_hw.c uint16_t phy_data;
phy_data 3925 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_CTRL, &phy_data);
phy_data 3929 dev/pci/if_em_hw.c phy_data |= MII_CR_RESET;
phy_data 3930 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, PHY_CTRL, phy_data);
phy_data 3964 dev/pci/if_em_hw.c uint16_t phy_data;
phy_data 3972 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
phy_data 3973 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, PHY_STATUS, &phy_data);
phy_data 3975 dev/pci/if_em_hw.c if (phy_data & MII_SR_LINK_STATUS) {
phy_data 3978 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
phy_data 3982 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
phy_data 3987 dev/pci/if_em_hw.c if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
phy_data 6173 dev/pci/if_em_hw.c uint16_t i, phy_data;
phy_data 6184 dev/pci/if_em_hw.c &phy_data);
phy_data 6187 dev/pci/if_em_hw.c cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
phy_data 6218 dev/pci/if_em_hw.c &phy_data);
phy_data 6221 dev/pci/if_em_hw.c cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
phy_data 6255 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, agc_reg_array[i], &phy_data);
phy_data 6259 dev/pci/if_em_hw.c cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
phy_data 6302 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, agc_reg_array[i], &phy_data);
phy_data 6309 dev/pci/if_em_hw.c cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
phy_data 6360 dev/pci/if_em_hw.c uint16_t phy_data;
phy_data 6368 dev/pci/if_em_hw.c &phy_data);
phy_data 6372 dev/pci/if_em_hw.c hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
phy_data 6376 dev/pci/if_em_hw.c &phy_data);
phy_data 6380 dev/pci/if_em_hw.c hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
phy_data 6407 dev/pci/if_em_hw.c uint16_t phy_data, phy_saved_data, speed, duplex, i;
phy_data 6438 dev/pci/if_em_hw.c &phy_data);
phy_data 6442 dev/pci/if_em_hw.c phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
phy_data 6445 dev/pci/if_em_hw.c phy_data);
phy_data 6460 dev/pci/if_em_hw.c &phy_data);
phy_data 6467 dev/pci/if_em_hw.c &phy_data);
phy_data 6471 dev/pci/if_em_hw.c idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
phy_data 6510 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
phy_data 6514 dev/pci/if_em_hw.c phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
phy_data 6515 dev/pci/if_em_hw.c phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
phy_data 6517 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw,dsp_reg_array[i], phy_data);
phy_data 6641 dev/pci/if_em_hw.c uint16_t phy_data;
phy_data 6652 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
phy_data 6661 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
phy_data 6669 dev/pci/if_em_hw.c phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
phy_data 6670 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
phy_data 6678 dev/pci/if_em_hw.c phy_data &= ~IGP02E1000_PM_D3_LPLU;
phy_data 6680 dev/pci/if_em_hw.c phy_data);
phy_data 6692 dev/pci/if_em_hw.c &phy_data);
phy_data 6696 dev/pci/if_em_hw.c phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
phy_data 6698 dev/pci/if_em_hw.c phy_data);
phy_data 6703 dev/pci/if_em_hw.c &phy_data);
phy_data 6707 dev/pci/if_em_hw.c phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
phy_data 6709 dev/pci/if_em_hw.c phy_data);
phy_data 6720 dev/pci/if_em_hw.c phy_data |= IGP01E1000_GMII_FLEX_SPD;
phy_data 6721 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
phy_data 6729 dev/pci/if_em_hw.c phy_data |= IGP02E1000_PM_D3_LPLU;
phy_data 6731 dev/pci/if_em_hw.c phy_data);
phy_data 6738 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
phy_data 6742 dev/pci/if_em_hw.c phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
phy_data 6743 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
phy_data 6771 dev/pci/if_em_hw.c uint16_t phy_data;
phy_data 6780 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
phy_data 6790 dev/pci/if_em_hw.c phy_data &= ~IGP02E1000_PM_D0_LPLU;
phy_data 6791 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
phy_data 6802 dev/pci/if_em_hw.c &phy_data);
phy_data 6806 dev/pci/if_em_hw.c phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
phy_data 6808 dev/pci/if_em_hw.c phy_data);
phy_data 6813 dev/pci/if_em_hw.c &phy_data);
phy_data 6817 dev/pci/if_em_hw.c phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
phy_data 6819 dev/pci/if_em_hw.c phy_data);
phy_data 6831 dev/pci/if_em_hw.c phy_data |= IGP02E1000_PM_D0_LPLU;
phy_data 6832 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
phy_data 6838 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
phy_data 6842 dev/pci/if_em_hw.c phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
phy_data 6843 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
phy_data 6861 dev/pci/if_em_hw.c uint16_t phy_data;
phy_data 6883 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
phy_data 6887 dev/pci/if_em_hw.c phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
phy_data 6888 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
phy_data 6898 dev/pci/if_em_hw.c ret_val = em_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
phy_data 6902 dev/pci/if_em_hw.c phy_data |= M88E1000_PHY_VCO_REG_BIT11;
phy_data 6903 dev/pci/if_em_hw.c ret_val = em_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
phy_data 321 dev/pci/if_em_hw.h int32_t em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data);