reg_tarc1         767 dev/pci/if_em_hw.c         uint32_t reg_tarc0, reg_tarc1;
reg_tarc1         785 dev/pci/if_em_hw.c                 reg_tarc1 = E1000_READ_REG(hw, TARC1);
reg_tarc1         789 dev/pci/if_em_hw.c                 reg_tarc1 &= ~0x60000000;   /* Clear bits 30 and 29 */
reg_tarc1         792 dev/pci/if_em_hw.c                 reg_tarc1 |= 0x07000000;    /* Set TARC1 bits 24-26 */
reg_tarc1         795 dev/pci/if_em_hw.c                     reg_tarc1 &= ~0x10000000;   /* Clear bit 28 if MULR is 1b */
reg_tarc1         797 dev/pci/if_em_hw.c                     reg_tarc1 |= 0x10000000;    /* Set bit 28 if MULR is 0b */
reg_tarc1         799 dev/pci/if_em_hw.c                 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
reg_tarc1         819 dev/pci/if_em_hw.c                 reg_tarc1 = E1000_READ_REG(hw, TARC1);
reg_tarc1         821 dev/pci/if_em_hw.c                     reg_tarc1 &= ~0x10000000;   /* Clear bit 28 if MULR is 1b */
reg_tarc1         823 dev/pci/if_em_hw.c                     reg_tarc1 |= 0x10000000;    /* Set bit 28 if MULR is 0b */
reg_tarc1         825 dev/pci/if_em_hw.c                 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
reg_tarc1         838 dev/pci/if_em_hw.c                 reg_tarc1 = E1000_READ_REG(hw, TARC1);
reg_tarc1         842 dev/pci/if_em_hw.c                     reg_tarc1 &= ~0x10000000;   /* Clear bit 28 if MULR is 1b */
reg_tarc1         844 dev/pci/if_em_hw.c                     reg_tarc1 |= 0x10000000;    /* Set bit 28 if MULR is 0b */
reg_tarc1         846 dev/pci/if_em_hw.c                 reg_tarc1 |= 0x45000000;        /* Set bit 24, 26 and 30 */
reg_tarc1         848 dev/pci/if_em_hw.c                 E1000_WRITE_REG(hw, TARC1, reg_tarc1);