1 /* $OpenBSD: if_xereg.h,v 1.4 2003/10/22 09:58:46 jmc Exp $ */
2
3 /*
4 * Copyright (c) 1999 Niklas Hallqvist, C Stone, Job de Haas
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Niklas Hallqvist,
18 * C Stone and Job de Haas.
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 /* Additional Card Configuration Registers on Dingo */
35
36 #define PCMCIA_CCR_DCOR0 0x20
37 #define PCMCIA_CCR_DCOR0_MRST_SFRST 0x80
38 #define PCMCIA_CCR_DCOR0_MRST_SFPWDN 0x40
39 #define PCMCIA_CCR_DCOR0_LED3_SFRST 0x20
40 #define PCMCIA_CCR_DCOR0_LED3_SFPWDN 0x10
41 #define PCMCIA_CCR_DCOR0_BUS 0x08
42 #define PCMCIA_CCR_DCOR0_DECODE 0x04
43 #define PCMCIA_CCR_DCOR0_SFINT 0x01
44 #define PCMCIA_CCR_DCOR1 0x22
45 #define PCMCIA_CCR_DCOR1_SFCSR_WAIT 0xC0
46 #define PCMCIA_CCR_DCOR1_SHADOW_SFIOB 0x20
47 #define PCMCIA_CCR_DCOR1_SHADOW_SFCSR 0x10
48 #define PCMCIA_CCR_DCOR1_FORCE_LEVIREQ 0x08
49 #define PCMCIA_CCR_DCOR1_D6 0x04
50 #define PCMCIA_CCR_DCOR1_SF_STSCHG 0x02
51 #define PCMCIA_CCR_DCOR1_SF_IREQ 0x01
52 #define PCMCIA_CCR_DCOR2 0x24
53 #define PCMCIA_CCR_DCOR2_SHADOW_SFCOR 0x10
54 #define PCMCIA_CCR_DCOR2_SMEM_BASE 0x0F
55 #define PCMCIA_CCR_DCOR3 0x26
56 #define PCMCIA_CCR_DCOR4 0x28
57 #define PCMCIA_CCR_SFCOR 0x40
58 #define PCMCIA_CCR_SFCOR_SRESET 0x80
59 #define PCMCIA_CCR_SFCOR_LEVIREQ 0x40
60 #define PCMCIA_CCR_SFCOR_IRQ_STSCHG 0x20
61 #define PCMCIA_CCR_SFCOR_CFINDEX 0x18
62 #define PCMCIA_CCR_SFCOR_IREQ_ENABLE 0x04
63 #define PCMCIA_CCR_SFCOR_ADDR_DECODE 0x02
64 #define PCMCIA_CCR_SFCOR_FUNC_ENABLE 0x01
65 #define PCMCIA_CCR_SFCSR 0x42
66 #define PCMCIA_CCR_SFCSR_IOIS8 0x20
67 #define PCMCIA_CCR_SFCSR_AUDIO 0x08
68 #define PCMCIA_CCR_SFCSR_PWRDWN 0x04
69 #define PCMCIA_CCR_SFCSR_INTR 0x02
70 #define PCMCIA_CCR_SFCSR_INTRACK 0x01
71 #define PCMCIA_CCR_SFIOBASE0 0x4A
72 #define PCMCIA_CCR_SFIOBASE1 0x4C
73 #define PCMCIA_CCR_SFILR 0x52
74
75 #define PCMCIA_CCR_SIZE_DINGO 0x54
76
77 /* All pages */
78 #define CR 0x0 /* W - Command register */
79 #define ESR 0x0 /* R - Ethernet status register */
80 #define PR 0x1 /* RW - Page register select */
81 #define EDP 0x4 /* RW - Ethernet data port, 4 registers */
82 #define ISR0 0x6 /* R - Ethernet interrupt status register */
83 #define GIR 0x7 /* RW - Global interrupt register */
84 #define PTR 0xd /* R - Packets Transmitted register */
85
86 /* Page 0 */
87 #define TSO0 0x8 /* R - Transmit space open, 3 registers */
88 #define TSO1 0x9
89 #define TSO2 0xa
90 #define DO0 0xc /* W - Data offset, 2 registers */
91 #define DO1 0xd
92 #define RSR 0xc /* R - Rx status register */
93 #define TPR 0xd /* R - Tx packets register */
94 #define RBC0 0xe /* R - Rx byte count, 2 registers */
95 #define RBC1 0xf
96
97 /* Page 1 */
98 #define IMR0 0xc /* RW - Interrupt mask, 2 registers */
99 #define IMR1 0xd
100 #define ECR 0xe /* RW - Ethernet config register */
101
102 /* Page 2 */
103 #define RBS0 0x8 /* RW - Receive buffer start, 2 registers */
104 #define RBS1 0x9
105 #define LED 0xa /* RW - LED control register */
106 #define LED3 0xb /* RW - LED3 control register */
107 #define MSR 0xc /* RW - Misc. setup register */
108 #define GP2 0xd /* RW - General purpose register 2 */
109
110 /* Page 3 */
111 #define TPT0 0xa /* RW - Tx packet threshold, 2 registers */
112 #define TPT1 0xb
113
114 /* Page 4 */
115 #define GP0 0x8 /* RW - General purpose register 0 */
116 #define GP1 0x9 /* RW - General purpose register 1 */
117 #define BV 0xa /* R - Bonding version register */
118 #define EES 0xb /* RW - EEPROM control register */
119
120 /* Page 5 */
121 #define RHSA0 0xa /* RX host start address */
122
123 /* Page 6 */
124
125 /* Page 7 */
126
127 /* Page 8 */
128
129 /* Page 16 */
130
131 /* Page 0x40 */
132 #define CMD0 0x8 /* W - Receive status register */
133 #define RXST0 0x9 /* RW - Receive status register */
134 #define TXST0 0xb /* RW - Transmit status, 2 registers */
135 #define TXST1 0xc
136 #define RX0MSK 0xd /* RW - Receive status mask register */
137 #define TX0MSK 0xe /* RW - Transmit status mask, 2 registers */
138 #define TX1MSK 0xf /* RW - Dingo does not define this register */
139
140 /* Page 0x42 */
141 #define SWC0 0x8 /* RW - Software configuration, 2 registers */
142 #define SWC1 0x9
143
144 /* Page 0x50-0x57 */
145 #define IA 0x8 /* RW - Individual address */
146
147 /* CR register bits */
148 #define TX_PKT 0x01 /* Transmit packet. */
149 #define SOFT_RESET 0x02 /* Software reset. */
150 #define ENABLE_INT 0x04 /* Enable interrupt. */
151 #define FORCE_INT 0x08 /* Force interrupt. */
152 #define CLR_TX_FIFO 0x10 /* Clear transmit FIFO. */
153 #define CLR_RX_OVERRUN 0x20 /* Clear receive overrun. */
154 #define RESTART_TX 0x40 /* Restart transmit process. */
155
156 /* ESR register bits */
157 #define FULL_PKT_RCV 0x01 /* Full packet received. */
158 #define PKT_REJECTED 0x04 /* A packet was rejected. */
159 #define TX_PKT_PEND 0x08 /* TX Packet Pending. */
160 #define INCOR_POLARITY 0x10 /* XXX from linux driver, but not used there */
161 #define MEDIA_SELECT 0x20 /* set if TP, clear if AUI */
162
163 /* DO register bits */
164 #define DO_OFF_MASK 0x1fff /* Mask for offset value. */
165 #define DO_CHG_OFFSET 0x2000 /* Change offset command. */
166 #define DO_SHM_MODE 0x4000 /* Shared memory mode. */
167 #define DO_SKIP_RX_PKT 0x8000 /* Skip Rx packet. */
168
169 /* RBC register bits */
170 #define RBC_COUNT_MASK 0x1fff /* Mask for byte count. */
171 #define RBC_RX_FULL 0x2000 /* Receive full packet. */
172 #define RBC_RX_PARTIAL 0x4000 /* Receive partial packet. */
173 #define RBC_RX_PKT_REJ 0x8000 /* Receive packet rejected. */
174
175 /* ISR0(/IMR0) register bits */
176 #define ISR_TX_OFLOW 0x01 /* Transmit buffer overflow. */
177 #define ISR_PKT_TX 0x02 /* Packet transmitted. */
178 #define ISR_MAC_INT 0x04 /* MAC interrupt. */
179 #define ISR_RX_EARLY 0x10 /* Receive early packet. */
180 #define ISR_RX_FULL 0x20 /* Receive full packet. */
181 #define ISR_RX_PKT_REJ 0x40 /* Receive packet rejected. */
182 #define ISR_FORCED_INT 0x80 /* Forced interrupt. */
183
184 /* ECR register bits */
185 #define ECR_EARLY_TX 0x01 /* Early transmit mode. */
186 #define ECR_EARLY_RX 0x02 /* Early receive mode. */
187 #define ECR_FULL_DUPLEX 0x04 /* Full duplex select. */
188 #define ECR_LNK_PLS_DIS 0x20 /* Link pulse disable. */
189 #define ECR_SW_COMPAT 0x80 /* Software compatibility switch. */
190
191 /* GP0 register bits */
192 #define GP1_WR 0x01 /* GP1 pin output value. */
193 #define GP2_WR 0x02 /* GP2 pin output value. */
194 #define GP1_OUT 0x04 /* GP1 pin output select. */
195 #define GP2_OUT 0x08 /* GP2 pin output select. */
196 #define GP1_RD 0x10 /* GP1 pin input value. */
197 #define GP2_RD 0x20 /* GP2 pin input value. */
198
199 /* GP1 register bits */
200 #define POWER_UP 0x01 /* When 0, power down analogue part of chip. */
201
202 /* LED register bits */
203 #define LED0_SHIFT 0 /* LED0 Output shift & mask */
204 #define LED0_MASK 0x7
205 #define LED1_SHIFT 3 /* LED1 Output shift & mask */
206 #define LED1_MASK 0x38
207 #define LED0_RX_ENA 0x40 /* LED0 - receive enable */
208 #define LED1_RX_ENA 0x80 /* LED1 - receive enable */
209
210 /* LED3 register bits */
211 #define LED3_SHIFT 0 /* LED0 output shift & mask */
212 #define LED3_MASK 0x7
213 #define LED3_RX_ENA 0x40 /* LED0 - receive enable */
214
215 /* LED output values */
216 #define LED_DISABLE 0 /* LED disabled */
217 #define LED_COLL_ACT 1 /* Collision activity */
218 #define LED_COLL_INACT 2 /* (NOT) Collision activity */
219 #define LED_10MB_LINK 3 /* 10 Mb link detected */
220 #define LED_100MB_LINK 4 /* 100 Mb link detected */
221 #define LED_LINK 5 /* 10 Mb or 100 Mb link detected */
222 #define LED_AUTO 6 /* Automatic assertion */
223 #define LED_TX_ACT 7 /* Transmit activity */
224
225 /* MSR register bits */
226 #define SRAM_128K_EXT 0x01 /* 128K SRAM extension */
227 #define RBS_BIT16 0x02 /* RBS bit 16 */
228 #define SELECT_MII 0x08 /* Select MII */
229 #define HASH_TBL_ENA 0x20 /* Hash table enable */
230
231 /* GP2 register bits */
232 #define GP3_WR 0x01 /* GP3 pin output value. */
233 #define GP4_WR 0x02 /* GP4 pin output value. */
234 #define GP3_OUT 0x04 /* GP3 pin output select. */
235 #define GP4_OUT 0x08 /* GP4 pin output select. */
236 #define GP3_RD 0x10 /* GP3 pin input value. */
237 #define GP4_RD 0x20 /* GP4 pin input value. */
238
239 /* RSR register bits */
240 #define RSR_NOTMCAST 0x01 /* clear when multicast packet */
241 #define RSR_BCAST 0x02 /* set when broadcast packet */
242 #define RSR_TOO_LONG 0x04 /* set if packet is longer than 1518 octets */
243 #define RSR_ALIGNERR 0x10 /* incorrect CRC and last octet not complete */
244 #define RSR_CRCERR 0x20 /* incorrect CRC and last octet complete */
245 #define RSR_RX_OK 0x80 /* packet received okay */
246
247 /* CMD0 register bits */
248 #define ONLINE 0x04 /* Online */
249 #define OFFLINE 0x08 /* Online */
250 #define ENABLE_RX 0x20 /* Enable receiver */
251 #define DISABLE_RX 0x80 /* Disable receiver */
252
253 /* RX0Msk register bits */
254 #define PKT_TOO_LONG 0x02 /* Packet too long mask. */
255 #define CRC_ERR 0x08 /* CRC error mask. */
256 #define RX_OVERRUN 0x10 /* Receive overrun mask. */
257 #define RX_ABORT 0x40 /* Receive abort mask. */
258 #define RX_OK 0x80 /* Receive OK mask. */
259
260 /* TX0Msk register bits */
261 #define CARRIER_LOST 0x01 /* Carrier sense lost. */
262 #define EXCESSIVE_COLL 0x02 /* Excessive collisions mask. */
263 #define TX_UNDERRUN 0x08 /* Transmit underrun mask. */
264 #define LATE_COLLISION 0x10 /* Late collision mask. */
265 #define SQE 0x20 /* Signal quality error mask.. */
266 #define TX_ABORT 0x40 /* Transmit abort mask. */
267 #define TX_OK 0x80 /* Transmit OK mask. */
268
269 /* SWC1 register bits */
270 #define SWC1_IND_ADDR 0x01 /* Individual address enable. */
271 #define SWC1_MCAST_PROM 0x02 /* Multicast promiscuous enable. */
272 #define SWC1_PROMISC 0x04 /* Promiscuous mode enable. */
273 #define SWC1_BCAST_DIS 0x08 /* Broadcast disable. */
274 #define SWC1_MEDIA_SEL 0x40 /* Media select (Mohawk). */
275 #define SWC1_AUTO_MEDIA 0x80 /* Automatic media select (Mohawk). */
276
277 /* Misc. defines. */
278
279 #define PAGE(sc, page) \
280 bus_space_write_1((sc->sc_bst), (sc->sc_bsh), (sc->sc_offset) + PR, (page))
281
282 /*
283 * GP3 is connected to the MDC pin of the NS DP83840A PHY, GP4 is
284 * connected to the MDIO pin. These are utility macros to enhance
285 * readability of the code.
286 */
287 #define MDC_LOW GP3_OUT
288 #define MDC_HIGH (GP3_OUT | GP3_WR)
289 #define MDIO_LOW GP4_OUT
290 #define MDIO_HIGH (GP4_OUT | GP4_WR)
291 #define MDIO GP4_RD
292
293 /* Values found in MANFID. */
294 #define XEMEDIA_ETHER 0x01
295 #define XEMEDIA_TOKEN 0x02
296 #define XEMEDIA_ARC 0x04
297 #define XEMEDIA_WIRELESS 0x08
298 #define XEMEDIA_MODEM 0x10
299 #define XEMEDIA_GSM 0x20
300
301 #define XEPROD_IDMASK 0x0f
302 #define XEPROD_POCKET 0x10
303 #define XEPROD_EXTERNAL 0x20
304 #define XEPROD_CREDITCARD 0x40
305 #define XEPROD_CARDBUS 0x80