ctrl_reg         1632 dev/ic/advlib.c 	u_int8_t        ctrl_reg;
ctrl_reg         1641 dev/ic/advlib.c 	ctrl_reg = ASC_GET_CHIP_CONTROL(iot, ioh);
ctrl_reg         1642 dev/ic/advlib.c 	saved_ctrl_reg = ctrl_reg & (~(ASC_CC_SCSI_RESET | ASC_CC_CHIP_RESET |
ctrl_reg         1671 dev/ic/advlib.c 		    (ctrl_reg & ASC_CC_SINGLE_STEP)) {
ctrl_reg           89 dev/pci/ixgb_hw.c 	uint32_t ctrl_reg;
ctrl_reg           91 dev/pci/ixgb_hw.c     ctrl_reg =  IXGB_CTRL0_RST |
ctrl_reg          102 dev/pci/ixgb_hw.c 	IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg);
ctrl_reg          104 dev/pci/ixgb_hw.c 	IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
ctrl_reg          109 dev/pci/ixgb_hw.c 	ctrl_reg = IXGB_READ_REG(hw, CTRL0);
ctrl_reg          112 dev/pci/ixgb_hw.c 	ASSERT(!(ctrl_reg & IXGB_CTRL0_RST));
ctrl_reg          119 dev/pci/ixgb_hw.c 	return ctrl_reg;
ctrl_reg          130 dev/pci/ixgb_hw.c 	uint32_t ctrl_reg;
ctrl_reg          163 dev/pci/ixgb_hw.c 	ctrl_reg = ixgb_mac_reset(hw);
ctrl_reg          172 dev/pci/ixgb_hw.c 	return (ctrl_reg & IXGB_CTRL0_RST);
ctrl_reg          300 dev/pci/ixgb_hw.c 	uint32_t ctrl_reg;
ctrl_reg          311 dev/pci/ixgb_hw.c 	ctrl_reg = ixgb_mac_reset(hw);
ctrl_reg          649 dev/pci/ixgb_hw.c 	uint32_t ctrl_reg;
ctrl_reg          656 dev/pci/ixgb_hw.c 	ctrl_reg = IXGB_READ_REG(hw, CTRL0);
ctrl_reg          659 dev/pci/ixgb_hw.c 	ctrl_reg &= ~(IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
ctrl_reg          672 dev/pci/ixgb_hw.c 		ctrl_reg |= (IXGB_CTRL0_CMDC);
ctrl_reg          676 dev/pci/ixgb_hw.c 		ctrl_reg |= (IXGB_CTRL0_RPE);
ctrl_reg          681 dev/pci/ixgb_hw.c 		ctrl_reg |= (IXGB_CTRL0_TPE);
ctrl_reg          687 dev/pci/ixgb_hw.c 		ctrl_reg |= (IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
ctrl_reg          698 dev/pci/ixgb_hw.c 	IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);