num_tx_desc_avail  952 dev/pci/if_em.c 	if (sc->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) {
num_tx_desc_avail  955 dev/pci/if_em.c 		if (sc->num_tx_desc_avail <= EM_TX_OP_THRESHOLD) {
num_tx_desc_avail  981 dev/pci/if_em.c 	if (map->dm_nsegs > sc->num_tx_desc_avail - 2)
num_tx_desc_avail 1008 dev/pci/if_em.c 				if (txd_used == sc->num_tx_desc_avail) {
num_tx_desc_avail 1047 dev/pci/if_em.c 		sc->num_tx_desc_avail -= txd_used;
num_tx_desc_avail 1049 dev/pci/if_em.c 		sc->num_tx_desc_avail -= map->dm_nsegs;
num_tx_desc_avail 1895 dev/pci/if_em.c 	sc->num_tx_desc_avail = sc->num_tx_desc;
num_tx_desc_avail 2105 dev/pci/if_em.c 	sc->num_tx_desc_avail--;
num_tx_desc_avail 2125 dev/pci/if_em.c 	if (sc->num_tx_desc_avail == sc->num_tx_desc)
num_tx_desc_avail 2128 dev/pci/if_em.c 	num_avail = sc->num_tx_desc_avail;
num_tx_desc_avail 2204 dev/pci/if_em.c 		else if (num_avail != sc->num_tx_desc_avail)
num_tx_desc_avail 2207 dev/pci/if_em.c 	sc->num_tx_desc_avail = num_avail;
num_tx_desc_avail  364 dev/pci/if_em.h 	volatile u_int16_t	num_tx_desc_avail;
num_tx_desc_avail  667 dev/pci/if_ixgb.c 	if (sc->num_tx_desc_avail <= IXGB_TX_CLEANUP_THRESHOLD) {
num_tx_desc_avail  670 dev/pci/if_ixgb.c 		if (sc->num_tx_desc_avail <= IXGB_TX_CLEANUP_THRESHOLD) {
num_tx_desc_avail  690 dev/pci/if_ixgb.c 	if (map->dm_nsegs > sc->num_tx_desc_avail)
num_tx_desc_avail  713 dev/pci/if_ixgb.c 	sc->num_tx_desc_avail -= map->dm_nsegs;
num_tx_desc_avail 1207 dev/pci/if_ixgb.c 	sc->num_tx_desc_avail = sc->num_tx_desc;
num_tx_desc_avail 1377 dev/pci/if_ixgb.c 	sc->num_tx_desc_avail--;
num_tx_desc_avail 1396 dev/pci/if_ixgb.c 	if (sc->num_tx_desc_avail == sc->num_tx_desc)
num_tx_desc_avail 1399 dev/pci/if_ixgb.c 	num_avail = sc->num_tx_desc_avail;
num_tx_desc_avail 1449 dev/pci/if_ixgb.c 		else if (num_avail != sc->num_tx_desc_avail)
num_tx_desc_avail 1452 dev/pci/if_ixgb.c 	sc->num_tx_desc_avail = num_avail;
num_tx_desc_avail  275 dev/pci/if_ixgb.h 	volatile u_int16_t	num_tx_desc_avail;