1 /* $OpenBSD: pte.h,v 1.9 2007/02/20 21:15:01 tom Exp $ */
2 /* $NetBSD: pte.h,v 1.11 1998/02/06 21:58:05 thorpej Exp $ */
3
4 /*
5 *
6 * Copyright (c) 1997 Charles D. Cranor and Washington University.
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgment:
19 * This product includes software developed by Charles D. Cranor and
20 * Washington University.
21 * 4. The name of the author may not be used to endorse or promote products
22 * derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 */
35
36 /*
37 * pte.h rewritten by chuck based on the jolitz version, plus random
38 * info on the pentium and other processors found on the net. the
39 * goal of this rewrite is to provide enough documentation on the MMU
40 * hardware that the reader will be able to understand it without having
41 * to refer to a hardware manual.
42 */
43
44 #ifndef _I386_PTE_H_
45 #define _I386_PTE_H_
46
47 /*
48 * i386 MMU hardware structure:
49 *
50 * the i386 MMU is a two-level MMU which maps 4GB of virtual memory.
51 * the pagesize is 4K (4096 [0x1000] bytes), although newer pentium
52 * processors can support a 4MB pagesize as well.
53 *
54 * the first level table (segment table?) is called a "page directory"
55 * and it contains 1024 page directory entries (PDEs). each PDE is
56 * 4 bytes (an int), so a PD fits in a single 4K page. this page is
57 * the page directory page (PDP). each PDE in a PDP maps 4MB of space
58 * (1024 * 4MB = 4GB). a PDE contains the physical address of the
59 * second level table: the page table. or, if 4MB pages are being used,
60 * then the PDE contains the PA of the 4MB page being mapped.
61 *
62 * a page table consists of 1024 page table entries (PTEs). each PTE is
63 * 4 bytes (an int), so a page table also fits in a single 4K page. a
64 * 4K page being used as a page table is called a page table page (PTP).
65 * each PTE in a PTP maps one 4K page (1024 * 4K = 4MB). a PTE contains
66 * the physical address of the page it maps and some flag bits (described
67 * below).
68 *
69 * the processor has a special register, "cr3", which points to the
70 * the PDP which is currently controlling the mappings of the virtual
71 * address space.
72 *
73 * the following picture shows the translation process for a 4K page:
74 *
75 * %cr3 register [PA of PDP]
76 * |
77 * |
78 * | bits <31-22> of VA bits <21-12> of VA bits <11-0>
79 * | index the PDP (0 - 1023) index the PTP are the page offset
80 * | | | |
81 * | v | |
82 * +--->+----------+ | |
83 * | PD Page | PA of v |
84 * | |---PTP-------->+------------+ |
85 * | 1024 PDE | | page table |--PTE--+ |
86 * | entries | | (aka PTP) | | |
87 * +----------+ | 1024 PTE | | |
88 * | entries | | |
89 * +------------+ | |
90 * | |
91 * bits <31-12> bits <11-0>
92 * p h y s i c a l a d d r
93 *
94 * the i386 caches PTEs in a TLB. it is important to flush out old
95 * TLB mappings when making a change to a mappings. writing to the
96 * %cr3 will flush the entire TLB. newer processors also have an
97 * instruction that will invalidate the mapping of a single page (which
98 * is useful if you are changing a single mappings because it preserves
99 * all the cached TLB entries).
100 *
101 * as shows, bits 31-12 of the PTE contain PA of the page being mapped.
102 * the rest of the PTE is defined as follows:
103 * bit# name use
104 * 11 n/a available for OS use, hardware ignores it
105 * 10 n/a available for OS use, hardware ignores it
106 * 9 n/a available for OS use, hardware ignores it
107 * 8 G global bit (see discussion below)
108 * 7 PS page size [for PDEs] (0=4k, 1=4M <if supported>)
109 * 6 D dirty (modified) page
110 * 5 A accessed (referenced) page
111 * 4 PCD cache disable
112 * 3 PWT prevent write through (cache)
113 * 2 U/S user/supervisor bit (0=supervisor only, 1=both u&s)
114 * 1 R/W read/write bit (0=read only, 1=read-write)
115 * 0 P present (valid)
116 *
117 * notes:
118 * - on the i386 the R/W bit is ignored if processor is in supervisor
119 * state (bug!)
120 * - PS is only supported on newer processors
121 * - PTEs with the G bit are global in the sense that they are not
122 * flushed from the TLB when %cr3 is written (to flush, use the
123 * "flush single page" instruction). this is only supported on
124 * newer processors. this bit can be used to keep the kernel's
125 * TLB entries around while context switching. since the kernel
126 * is mapped into all processes at the same place it does not make
127 * sense to flush these entries when switching from one process'
128 * pmap to another.
129 */
130
131 #if !defined(_LOCORE)
132
133 /*
134 * here we define the data types for PDEs and PTEs
135 */
136
137 typedef u_int32_t pd_entry_t; /* PDE */
138 typedef u_int32_t pt_entry_t; /* PTE */
139
140 #endif
141
142 /*
143 * now we define various for playing with virtual addresses
144 */
145
146 #define PDSHIFT 22 /* offset of PD index in VA */
147 #define NBPD (1 << PDSHIFT) /* # bytes mapped by PD (4MB) */
148 #define PDOFSET (NBPD-1) /* mask for non-PD part of VA */
149 #if 0 /* not used? */
150 #define NPTEPD (NBPD / NBPG) /* # of PTEs in a PD */
151 #else
152 #define PTES_PER_PTP (NBPD / NBPG) /* # of PTEs in a PTP */
153 #endif
154 #define PD_MASK 0xffc00000 /* page directory address bits */
155 #define PT_MASK 0x003ff000 /* page table address bits */
156
157 /*
158 * here we define the bits of the PDE/PTE, as described above:
159 *
160 * XXXCDC: need to rename these (PG_u == ugly).
161 */
162
163 #define PG_V 0x00000001 /* valid entry */
164 #define PG_RO 0x00000000 /* read-only page */
165 #define PG_RW 0x00000002 /* read-write page */
166 #define PG_u 0x00000004 /* user accessible page */
167 #define PG_PROT 0x00000806 /* all protection bits */
168 #define PG_N 0x00000018 /* non-cacheable */
169 #define PG_U 0x00000020 /* has been used */
170 #define PG_M 0x00000040 /* has been modified */
171 #define PG_PS 0x00000080 /* 4MB page size */
172 #define PG_G 0x00000100 /* global, don't TLB flush */
173 #define PG_AVAIL1 0x00000200 /* ignored by hardware */
174 #define PG_AVAIL2 0x00000400 /* ignored by hardware */
175 #define PG_AVAIL3 0x00000800 /* ignored by hardware */
176 #define PG_FRAME 0xfffff000 /* page frame mask */
177 #define PG_LGFRAME 0xffc00000 /* large (4M) page frame mask */
178
179 /*
180 * various short-hand protection codes
181 */
182
183 #define PG_KR 0x00000000 /* kernel read-only */
184 #define PG_KW 0x00000002 /* kernel read-write */
185
186 /*
187 * page protection exception bits
188 */
189
190 #define PGEX_P 0x01 /* protection violation (vs. no mapping) */
191 #define PGEX_W 0x02 /* exception during a write cycle */
192 #define PGEX_U 0x04 /* exception while in user mode (upl) */
193 #define PGEX_I 0x10 /* instruction fetch blocked by NX */
194
195 #endif /* _I386_PTE_H_ */