root/dev/pci/if_bge.c

DEFINITIONS

1. bge_readmem_ind
2. bge_writemem_ind
3. bge_writereg_ind
4. bge_eeprom_getbyte
5. bge_read_eeprom
6. bge_miibus_readreg
7. bge_miibus_writereg
8. bge_miibus_statchg
9. bge_alloc_jumbo_mem
10. bge_jalloc
11. bge_jfree
12. bge_newbuf_std
13. bge_newbuf_jumbo
14. bge_init_rx_ring_std
15. bge_free_rx_ring_std
16. bge_init_rx_ring_jumbo
17. bge_free_rx_ring_jumbo
18. bge_free_tx_ring
19. bge_init_tx_ring
20. bge_iff
21. bge_chipinit
22. bge_blockinit
23. bge_lookup_rev
24. bge_probe
25. bge_attach
26. bge_reset
27. bge_rxeof
28. bge_txeof
29. bge_intr
30. bge_tick
31. bge_stats_update_regs
32. bge_stats_update
33. bge_compact_dma_runt
34. bge_encap
35. bge_start
36. bge_init
37. bge_ifmedia_upd
38. bge_ifmedia_sts
39. bge_ioctl
40. bge_watchdog
41. bge_stop_block
42. bge_stop
43. bge_shutdown
44. bge_link_upd
45. bge_power

    1 /*      $OpenBSD: if_bge.c,v 1.213 2007/06/21 01:11:50 dlg Exp $        */
    3 /*
    4  * Copyright (c) 2001 Wind River Systems
    5  * Copyright (c) 1997, 1998, 1999, 2001
    6  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  * 3. All advertising materials mentioning features or use of this software
   17  *    must display the following acknowledgement:
   18  *      This product includes software developed by Bill Paul.
   19  * 4. Neither the name of the author nor the names of any co-contributors
   20  *    may be used to endorse or promote products derived from this software
   21  *    without specific prior written permission.
   22  *
   23  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   24  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   26  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   27  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   30  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   31  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   32  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   33  * THE POSSIBILITY OF SUCH DAMAGE.
   34  *
   35  * $FreeBSD: if_bge.c,v 1.25 2002/11/14 23:54:49 sam Exp $
   36  */
   38 /*
   39  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
   40  *
   41  * Written by Bill Paul <wpaul@windriver.com>
   42  * Senior Engineer, Wind River Systems
   43  */
   45 /*
   46  * The Broadcom BCM5700 is based on technology originally developed by
   47  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
   48  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
   49  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
   50  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, Jumbo
   51  * frames, highly configurable RX filtering, and 16 RX and TX queues
   52  * (which, along with RX filter rules, can be used for QOS applications).
   53  * Other features, such as TCP segmentation, may be available as part
   54  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
   55  * firmware images can be stored in hardware and need not be compiled
   56  * into the driver.
   57  *
   58  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
   59  * function in a 32-bit/64-bit 33/66MHz bus, or a 64-bit/133MHz bus.
   60  *
   61  * The BCM5701 is a single-chip solution incorporating both the BCM5700
   62  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
   63  * does not support external SSRAM.
   64  *
   65  * Broadcom also produces a variation of the BCM5700 under the "Altima"
   66  * brand name, which is functionally similar but lacks PCI-X support.
   67  *
   68  * Without external SSRAM, you can only have at most 4 TX rings,
   69  * and the use of the mini RX ring is disabled. This seems to imply
   70  * that these features are simply not available on the BCM5701. As a
   71  * result, this driver does not implement any support for the mini RX
   72  * ring.
   73  */
   75 #include "bpfilter.h"
   76 #include "vlan.h"
   78 #include <sys/param.h>
   79 #include <sys/systm.h>
   80 #include <sys/sockio.h>
   81 #include <sys/mbuf.h>
   82 #include <sys/malloc.h>
   83 #include <sys/kernel.h>
   84 #include <sys/device.h>
   85 #include <sys/timeout.h>
   86 #include <sys/socket.h>
   88 #include <net/if.h>
   89 #include <net/if_dl.h>
   90 #include <net/if_media.h>
   92 #ifdef INET
   93 #include <netinet/in.h>
   94 #include <netinet/in_systm.h>
   95 #include <netinet/in_var.h>
   96 #include <netinet/ip.h>
   97 #include <netinet/if_ether.h>
   98 #endif
  100 #if NVLAN > 0
  101 #include <net/if_types.h>
  102 #include <net/if_vlan_var.h>
  103 #endif
  105 #if NBPFILTER > 0
  106 #include <net/bpf.h>
  107 #endif
  109 #ifdef __sparc64__
  110 #include <dev/ofw/openfirm.h>
  111 #endif
  113 #include <dev/pci/pcireg.h>
  114 #include <dev/pci/pcivar.h>
  115 #include <dev/pci/pcidevs.h>
  117 #include <dev/mii/mii.h>
  118 #include <dev/mii/miivar.h>
  119 #include <dev/mii/miidevs.h>
  120 #include <dev/mii/brgphyreg.h>
  122 #include <dev/pci/if_bgereg.h>
  124 const struct bge_revision * bge_lookup_rev(u_int32_t);
  125 int bge_probe(struct device *, void *, void *);
  126 void bge_attach(struct device *, struct device *, void *);
  128 struct cfattach bge_ca = {
  129         sizeof(struct bge_softc), bge_probe, bge_attach
  130 };
  132 struct cfdriver bge_cd = {
  133         0, "bge", DV_IFNET
  134 };
  136 void bge_txeof(struct bge_softc *);
  137 void bge_rxeof(struct bge_softc *);
  139 void bge_tick(void *);
  140 void bge_stats_update(struct bge_softc *);
  141 void bge_stats_update_regs(struct bge_softc *);
  142 int bge_encap(struct bge_softc *, struct mbuf *, u_int32_t *);
  143 int bge_compact_dma_runt(struct mbuf *pkt);
  145 int bge_intr(void *);
  146 void bge_start(struct ifnet *);
  147 int bge_ioctl(struct ifnet *, u_long, caddr_t);
  148 void bge_init(void *);
  149 void bge_power(int, void *);
  150 void bge_stop_block(struct bge_softc *, bus_size_t, u_int32_t);
  151 void bge_stop(struct bge_softc *);
  152 void bge_watchdog(struct ifnet *);
  153 void bge_shutdown(void *);
  154 int bge_ifmedia_upd(struct ifnet *);
  155 void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
u_int8_t bge_eeprom_getbyte(struct bge_softc *, int, u_int8_t *);
  158 int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
  160 void bge_iff(struct bge_softc *);
  162 int bge_alloc_jumbo_mem(struct bge_softc *);
  163 void *bge_jalloc(struct bge_softc *);
  164 void bge_jfree(caddr_t, u_int, void *);
  165 int bge_newbuf_std(struct bge_softc *, int, struct mbuf *, bus_dmamap_t);
  166 int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
  167 int bge_init_rx_ring_std(struct bge_softc *);
  168 void bge_free_rx_ring_std(struct bge_softc *);
  169 int bge_init_rx_ring_jumbo(struct bge_softc *);
  170 void bge_free_rx_ring_jumbo(struct bge_softc *);
  171 void bge_free_tx_ring(struct bge_softc *);
  172 int bge_init_tx_ring(struct bge_softc *);
  174 void bge_chipinit(struct bge_softc *);
  175 int bge_blockinit(struct bge_softc *);
u_int32_t bge_readmem_ind(struct bge_softc *, int);
  178 void bge_writemem_ind(struct bge_softc *, int, int);
  179 void bge_writereg_ind(struct bge_softc *, int, int);
  181 int bge_miibus_readreg(struct device *, int, int);
  182 void bge_miibus_writereg(struct device *, int, int, int);
  183 void bge_miibus_statchg(struct device *);
  185 void bge_reset(struct bge_softc *);
  186 void bge_link_upd(struct bge_softc *);
  188 #ifdef BGE_DEBUG
  189 #define DPRINTF(x)      do { if (bgedebug) printf x; } while (0)
  190 #define DPRINTFN(n,x)   do { if (bgedebug >= (n)) printf x; } while (0)
  191 int     bgedebug = 0;
  192 #else
  193 #define DPRINTF(x)
  194 #define DPRINTFN(n,x)
  195 #endif
  197 /*
  198  * Various supported device vendors/types and their names. Note: the
  199  * spec seems to indicate that the hardware still has Alteon's vendor
  200  * ID burned into it, though it will always be overridden by the vendor
  201  * ID in the EEPROM. Just to be safe, we cover all possibilities.
  202  */
  203 const struct pci_matchid bge_devices[] = {
  204         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700 },
  205         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701 },
  207         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000 },
  208         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001 },
  209         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100 },
  211         { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701 },
  213         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700 },
  214         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701 },
  215         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702 },
  216         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT },
  217         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X },
  218         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703 },
  219         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703_ALT },
  220         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X },
  221         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C },
  222         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S },
  223         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT },
  224         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705 },
  225         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F },
  226         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K },
  227         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M },
  228         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT },
  229         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714 },
  230         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S },
  231         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715 },
  232         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S },
  233         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720 },
  234         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721 },
  235         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722 },
  236         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750 },
  237         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M },
  238         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751 },
  239         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F },
  240         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M },
  241         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752 },
  242         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M },
  243         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753 },
  244         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F },
  245         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M },
  246         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754 },
  247         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M },
  248         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755 },
  249         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M },
  250         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756 },
  251         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780 },
  252         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S },
  253         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781 },
  254         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782 },
  255         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786 },
  256         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787 },
  257         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F },
  258         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M },
  259         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788 },
  260         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789 },
  261         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901 },
  262         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2 },
  263         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M },
  264 #if 0
  265         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906 },
  266         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M },
  267 #endif
  269         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK9D21 },
  271         { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996 },
  272 };
  274 #define BGE_IS_5705_OR_BEYOND(sc)  \
  275         (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705    || \
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750    || \
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714_A0 || \
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780    || \
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714    || \
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752    || \
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755    || \
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787    || \
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906)
  285 #define BGE_IS_575X_PLUS(sc)  \
  286         (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750    || \
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714_A0 || \
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780    || \
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714    || \
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752    || \
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755    || \
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787    || \
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906)
  295 #define BGE_IS_5714_FAMILY(sc)  \
  296         (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714_A0 || \
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780    || \
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5714)
  300 #define BGE_IS_JUMBO_CAPABLE(sc)  \
  301         (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700    || \
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701    || \
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703    || \
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704)
  307 static const struct bge_revision {
u_int32_t               br_chipid;
  309         const char              *br_name;
  310 } bge_revisions[] = {
  311         { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" },
  312         { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" },
  313         { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" },
  314         { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" },
  315         { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" },
  316         { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" },
  317         { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" },
  318         { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" },
  319         { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" },
  320         { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" },
  321         { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" },
  322         { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" },
  323         { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" },
  324         { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" },
  325         { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" },
  326         { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" },
  327         { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" },
  328         { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" },
  329         { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" },
  330         { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" },
  331         { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" },
  332         { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" },
  333         { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" },
  334         { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" },
  335         { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" },
  336         { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" },
  337         { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" },
  338         { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" },
  339         { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" },
  340         { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" },
  341         { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" },
  342         { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" },
  343         { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" },
  344         { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" },
  345         { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" },
  346         { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" },
  347         { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" },
  348         { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" },
  349         { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" },
  350         { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" },
  351         { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" },
  352         { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" },
  353         { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" },
  354         { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" },
  355         { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" },
  356         { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" },
  357         /* the 5754 and 5787 share the same ASIC ID */
  358         { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" },
  359         { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" },
  360         { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" },
  361         { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" },
  363         { 0, NULL }
  364 };
  366 /*
  367  * Some defaults for major revisions, so that newer steppings
  368  * that we don't know about have a shot at working.
  369  */
  370 static const struct bge_revision bge_majorrevs[] = {
  371         { BGE_ASICREV_BCM5700, "unknown BCM5700" },
  372         { BGE_ASICREV_BCM5701, "unknown BCM5701" },
  373         /* 5702 and 5703 share the same ASIC ID */
  374         { BGE_ASICREV_BCM5703, "unknown BCM5703" },
  375         { BGE_ASICREV_BCM5704, "unknown BCM5704" },
  376         { BGE_ASICREV_BCM5705, "unknown BCM5705" },
  377         { BGE_ASICREV_BCM5750, "unknown BCM5750" },
  378         { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" },
  379         { BGE_ASICREV_BCM5752, "unknown BCM5752" },
  380         { BGE_ASICREV_BCM5780, "unknown BCM5780" },
  381         { BGE_ASICREV_BCM5714, "unknown BCM5714" },
  382         { BGE_ASICREV_BCM5755, "unknown BCM5755" },
  383         /* 5754 and 5787 share the same ASIC ID */
  384         { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" },
  385         { BGE_ASICREV_BCM5906, "unknown BCM5906" },
  387         { 0, NULL }
  388 };
u_int32_t
bge_readmem_ind(struct bge_softc *sc, int off)
  392 {
  393         struct pci_attach_args  *pa = &(sc->bge_pa);
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off);
  396         return (pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA));
  397 }
  399 void
bge_writemem_ind(struct bge_softc *sc, int off, int val)
  401 {
  402         struct pci_attach_args  *pa = &(sc->bge_pa);
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_BASEADDR, off);
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MEMWIN_DATA, val);
  406 }
  408 void
bge_writereg_ind(struct bge_softc *sc, int off, int val)
  410 {
  411         struct pci_attach_args  *pa = &(sc->bge_pa);
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_BASEADDR, off);
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_REG_DATA, val);
  415 }
  417 /*
  418  * Read a byte of data stored in the EEPROM at address 'addr.' The
  419  * BCM570x supports both the traditional bitbang interface and an
  420  * auto access interface for reading the EEPROM. We use the auto
  421  * access method.
  422  */
u_int8_t
bge_eeprom_getbyte(struct bge_softc *sc, int addr, u_int8_t *dest)
  425 {
  426         int i;
u_int32_t byte = 0;
  429         /*
  430          * Enable use of auto EEPROM access so we can avoid
  431          * having to use the bitbang method.
  432          */
BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
  435         /* Reset the EEPROM, load the clock period. */
CSR_WRITE_4(sc, BGE_EE_ADDR,
BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
DELAY(20);
  440         /* Issue the read EEPROM command. */
CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
  443         /* Wait for completion */
  444         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
DELAY(10);
  446                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
  447                         break;
  448         }
  450         if (i == BGE_TIMEOUT * 10) {
printf("%s: eeprom read timed out\n", sc->bge_dev.dv_xname);
  452                 return (1);
  453         }
  455         /* Get result. */
byte = CSR_READ_4(sc, BGE_EE_DATA);
  458         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
  460         return (0);
  461 }
  463 /*
  464  * Read a sequence of bytes from the EEPROM.
  465  */
  466 int
bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
  468 {
  469         int err = 0, i;
u_int8_t byte = 0;
  472         for (i = 0; i < cnt; i++) {
err = bge_eeprom_getbyte(sc, off + i, &byte);
  474                 if (err)
  475                         break;
  476                 *(dest + i) = byte;
  477         }
  479         return (err ? 1 : 0);
  480 }
  482 int
bge_miibus_readreg(struct device *dev, int phy, int reg)
  484 {
  485         struct bge_softc *sc = (struct bge_softc *)dev;
u_int32_t val, autopoll;
  487         int i;
  489         /*
  490          * Broadcom's own driver always assumes the internal
  491          * PHY is at GMII address 1. On some chips, the PHY responds
  492          * to accesses at all addresses, which could cause us to
  493          * bogusly attach the PHY 32 times at probe type. Always
  494          * restricting the lookup to address 1 is simpler than
  495          * trying to figure out which chips revisions should be
  496          * special-cased.
  497          */
  498         if (phy != 1)
  499                 return (0);
  501         /* Reading with autopolling on may trigger PCI errors */
autopoll = CSR_READ_4(sc, BGE_MI_MODE);
  503         if (autopoll & BGE_MIMODE_AUTOPOLL) {
BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
DELAY(40);
  506         }
CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
BGE_MIPHY(phy)|BGE_MIREG(reg));
  511         for (i = 0; i < 200; i++) {
delay(1);
val = CSR_READ_4(sc, BGE_MI_COMM);
  514                 if (!(val & BGE_MICOMM_BUSY))
  515                         break;
delay(10);
  517         }
  519         if (i == 200) {
printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname);
val = 0;
  522                 goto done;
  523         }
val = CSR_READ_4(sc, BGE_MI_COMM);
done:
  528         if (autopoll & BGE_MIMODE_AUTOPOLL) {
BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
DELAY(40);
  531         }
  533         if (val & BGE_MICOMM_READFAIL)
  534                 return (0);
  536         return (val & 0xFFFF);
  537 }
  539 void
bge_miibus_writereg(struct device *dev, int phy, int reg, int val)
  541 {
  542         struct bge_softc *sc = (struct bge_softc *)dev;
u_int32_t autopoll;
  544         int i;
  546         /* Reading with autopolling on may trigger PCI errors */
autopoll = CSR_READ_4(sc, BGE_MI_MODE);
  548         if (autopoll & BGE_MIMODE_AUTOPOLL) {
DELAY(40);
BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
DELAY(10); /* 40 usec is supposed to be adequate */
  552         }
CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
  557         for (i = 0; i < 200; i++) {
delay(1);
  559                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
  560                         break;
delay(10);
  562         }
  564         if (autopoll & BGE_MIMODE_AUTOPOLL) {
BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
DELAY(40);
  567         }
  569         if (i == 200) {
printf("%s: PHY read timed out\n", sc->bge_dev.dv_xname);
  571         }
  572 }
  574 void
bge_miibus_statchg(struct device *dev)
  576 {
  577         struct bge_softc *sc = (struct bge_softc *)dev;
  578         struct mii_data *mii = &sc->bge_mii;
  580         /*
  581          * Get flow control negotiation result.
  582          */
  583         if (IFM_SUBTYPE(mii->mii_media.ifm_cur->ifm_media) == IFM_AUTO &&
  584             (mii->mii_media_active & IFM_ETH_FMASK) != sc->bge_flowflags) {
sc->bge_flowflags = mii->mii_media_active & IFM_ETH_FMASK;
mii->mii_media_active &= ~IFM_ETH_FMASK;
  587         }
BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
  590         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T)
BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
  592         else
BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
  595         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
  597         else
BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
  600         /*
  601          * 802.3x flow control
  602          */
  603         if (sc->bge_flowflags & IFM_ETH_RXPAUSE)
BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE);
  605         else
BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE);
  608         if (sc->bge_flowflags & IFM_ETH_TXPAUSE)
BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE);
  610         else
BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE);
  612 }
  614 /*
  615  * Memory management for Jumbo frames.
  616  */
  618 int
bge_alloc_jumbo_mem(struct bge_softc *sc)
  620 {
caddr_t                 ptr, kva;
bus_dma_segment_t       seg;
  623         int             i, rseg, state, error;
  624         struct bge_jpool_entry   *entry;
state = error = 0;
  628         /* Grab a big chunk o' storage. */
  629         if (bus_dmamem_alloc(sc->bge_dmatag, BGE_JMEM, PAGE_SIZE, 0,
  630                              &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
printf("%s: can't alloc rx buffers\n", sc->bge_dev.dv_xname);
  632                 return (ENOBUFS);
  633         }
state = 1;
  636         if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg, BGE_JMEM, &kva,
BUS_DMA_NOWAIT)) {
printf("%s: can't map dma buffers (%d bytes)\n",
sc->bge_dev.dv_xname, BGE_JMEM);
error = ENOBUFS;
  641                 goto out;
  642         }
state = 2;
  645         if (bus_dmamap_create(sc->bge_dmatag, BGE_JMEM, 1, BGE_JMEM, 0,
BUS_DMA_NOWAIT, &sc->bge_cdata.bge_rx_jumbo_map)) {
printf("%s: can't create dma map\n", sc->bge_dev.dv_xname);
error = ENOBUFS;
  649                 goto out;
  650         }
state = 3;
  653         if (bus_dmamap_load(sc->bge_dmatag, sc->bge_cdata.bge_rx_jumbo_map,
kva, BGE_JMEM, NULL, BUS_DMA_NOWAIT)) {
printf("%s: can't load dma map\n", sc->bge_dev.dv_xname);
error = ENOBUFS;
  657                 goto out;
  658         }
state = 4;
sc->bge_cdata.bge_jumbo_buf = (caddr_t)kva;
DPRINTFN(1,("bge_jumbo_buf = 0x%08X\n", sc->bge_cdata.bge_jumbo_buf));
SLIST_INIT(&sc->bge_jfree_listhead);
SLIST_INIT(&sc->bge_jinuse_listhead);
  667         /*
  668          * Now divide it up into 9K pieces and save the addresses
  669          * in an array.
  670          */
ptr = sc->bge_cdata.bge_jumbo_buf;
  672         for (i = 0; i < BGE_JSLOTS; i++) {
sc->bge_cdata.bge_jslots[i] = ptr;
ptr += BGE_JLEN;
entry = malloc(sizeof(struct bge_jpool_entry),
M_DEVBUF, M_NOWAIT);
  677                 if (entry == NULL) {
printf("%s: no memory for jumbo buffer queue!\n",
sc->bge_dev.dv_xname);
error = ENOBUFS;
  681                         goto out;
  682                 }
entry->slot = i;
SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
entry, jpool_entries);
  686         }
out:
  688         if (error != 0) {
  689                 switch (state) {
  690                 case 4:
bus_dmamap_unload(sc->bge_dmatag,
sc->bge_cdata.bge_rx_jumbo_map);
  693                 case 3:
bus_dmamap_destroy(sc->bge_dmatag,
sc->bge_cdata.bge_rx_jumbo_map);
  696                 case 2:
bus_dmamem_unmap(sc->bge_dmatag, kva, BGE_JMEM);
  698                 case 1:
bus_dmamem_free(sc->bge_dmatag, &seg, rseg);
  700                         break;
  701                 default:
  702                         break;
  703                 }
  704         }
  706         return (error);
  707 }
  709 /*
  710  * Allocate a Jumbo buffer.
  711  */
  712 void *
bge_jalloc(struct bge_softc *sc)
  714 {
  715         struct bge_jpool_entry   *entry;
entry = SLIST_FIRST(&sc->bge_jfree_listhead);
  719         if (entry == NULL)
  720                 return (NULL);
SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries);
SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries);
  724         return (sc->bge_cdata.bge_jslots[entry->slot]);
  725 }
  727 /*
  728  * Release a Jumbo buffer.
  729  */
  730 void
bge_jfree(caddr_t buf, u_int size, void *arg)
  732 {
  733         struct bge_jpool_entry *entry;
  734         struct bge_softc *sc;
  735         int i;
  737         /* Extract the softc struct pointer. */
sc = (struct bge_softc *)arg;
  740         if (sc == NULL)
panic("bge_jfree: can't find softc pointer!");
  743         /* calculate the slot this buffer belongs to */
i = ((vaddr_t)buf
  746              - (vaddr_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN;
  748         if ((i < 0) || (i >= BGE_JSLOTS))
panic("bge_jfree: asked to free buffer that we don't manage!");
entry = SLIST_FIRST(&sc->bge_jinuse_listhead);
  752         if (entry == NULL)
panic("bge_jfree: buffer not in use!");
entry->slot = i;
SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries);
SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries);
  757 }
  760 /*
  761  * Intialize a standard receive ring descriptor.
  762  */
  763 int
bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m,
bus_dmamap_t dmamap)
  766 {
  767         struct mbuf             *m_new = NULL;
  768         struct bge_rx_bd        *r;
  769         int                     error;
  771         if (dmamap == NULL) {
error = bus_dmamap_create(sc->bge_dmatag, MCLBYTES, 1,
MCLBYTES, 0, BUS_DMA_NOWAIT, &dmamap);
  774                 if (error != 0)
  775                         return (error);
  776         }
sc->bge_cdata.bge_rx_std_map[i] = dmamap;
  780         if (m == NULL) {
MGETHDR(m_new, M_DONTWAIT, MT_DATA);
  782                 if (m_new == NULL)
  783                         return (ENOBUFS);
MCLGET(m_new, M_DONTWAIT);
  786                 if (!(m_new->m_flags & M_EXT)) {
m_freem(m_new);
  788                         return (ENOBUFS);
  789                 }
m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
  791         } else {
  792                 /*
  793                  * We're re-using a previously allocated mbuf;
  794                  * be sure to re-init pointers and lengths to
  795                  * default values.
  796                  */
m_new = m;
m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
m_new->m_data = m_new->m_ext.ext_buf;
  800         }
  802         if (!(sc->bge_flags & BGE_RX_ALIGNBUG))
m_adj(m_new, ETHER_ALIGN);
error = bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_new,
BUS_DMA_READ|BUS_DMA_NOWAIT);
  807         if (error) {
  808                 if (m == NULL) {
m_freem(m_new);
sc->bge_cdata.bge_rx_std_chain[i] = NULL;
  811                 }
  812                 return (ENOBUFS);
  813         }
sc->bge_cdata.bge_rx_std_chain[i] = m_new;
r = &sc->bge_rdata->bge_rx_std_ring[i];
BGE_HOSTADDR(r->bge_addr, dmamap->dm_segs[0].ds_addr);
r->bge_flags = BGE_RXBDFLAG_END;
r->bge_len = m_new->m_len;
r->bge_idx = i;
bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
offsetof(struct bge_ring_data, bge_rx_std_ring) +
i * sizeof (struct bge_rx_bd),
  825             sizeof (struct bge_rx_bd),
BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
  828         return (0);
  829 }
  831 /*
  832  * Initialize a Jumbo receive ring descriptor. This allocates
  833  * a Jumbo buffer from the pool managed internally by the driver.
  834  */
  835 int
bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
  837 {
  838         struct mbuf *m_new = NULL;
  839         struct bge_rx_bd *r;
  841         if (m == NULL) {
caddr_t                 buf = NULL;
  844                 /* Allocate the mbuf. */
MGETHDR(m_new, M_DONTWAIT, MT_DATA);
  846                 if (m_new == NULL)
  847                         return (ENOBUFS);
  849                 /* Allocate the Jumbo buffer */
buf = bge_jalloc(sc);
  851                 if (buf == NULL) {
m_freem(m_new);
  853                         return (ENOBUFS);
  854                 }
  856                 /* Attach the buffer to the mbuf. */
m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN;
MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, 0, bge_jfree, sc);
  859         } else {
  860                 /*
  861                  * We're re-using a previously allocated mbuf;
  862                  * be sure to re-init pointers and lengths to
  863                  * default values.
  864                  */
m_new = m;
m_new->m_data = m_new->m_ext.ext_buf;
m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
  868         }
  870         if (!(sc->bge_flags & BGE_RX_ALIGNBUG))
m_adj(m_new, ETHER_ALIGN);
  872         /* Set up the descriptor. */
r = &sc->bge_rdata->bge_rx_jumbo_ring[i];
sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
BGE_HOSTADDR(r->bge_addr, BGE_JUMBO_DMA_ADDR(sc, m_new));
r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
r->bge_len = m_new->m_len;
r->bge_idx = i;
bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
offsetof(struct bge_ring_data, bge_rx_jumbo_ring) +
i * sizeof (struct bge_rx_bd),
  883             sizeof (struct bge_rx_bd),
BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
  886         return (0);
  887 }
  889 /*
  890  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
  891  * that's 1MB or memory, which is a lot. For now, we fill only the first
  892  * 256 ring entries and hope that our CPU is fast enough to keep up with
  893  * the NIC.
  894  */
  895 int
bge_init_rx_ring_std(struct bge_softc *sc)
  897 {
  898         int i;
  900         if (sc->bge_flags & BGE_RXRING_VALID)
  901                 return (0);
  903         for (i = 0; i < BGE_SSLOTS; i++) {
  904                 if (bge_newbuf_std(sc, i, NULL, 0) == ENOBUFS)
  905                         return (ENOBUFS);
  906         }
sc->bge_std = i - 1;
CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
sc->bge_flags |= BGE_RXRING_VALID;
  913         return (0);
  914 }
  916 void
bge_free_rx_ring_std(struct bge_softc *sc)
  918 {
  919         int i;
  921         if (!(sc->bge_flags & BGE_RXRING_VALID))
  922                 return;
  924         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
  925                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
sc->bge_cdata.bge_rx_std_chain[i] = NULL;
bus_dmamap_destroy(sc->bge_dmatag,
sc->bge_cdata.bge_rx_std_map[i]);
  930                 }
bzero((char *)&sc->bge_rdata->bge_rx_std_ring[i],
  932                     sizeof(struct bge_rx_bd));
  933         }
sc->bge_flags &= ~BGE_RXRING_VALID;
  936 }
  938 int
bge_init_rx_ring_jumbo(struct bge_softc *sc)
  940 {
  941         int i;
  942         volatile struct bge_rcb *rcb;
  944         if (sc->bge_flags & BGE_JUMBO_RXRING_VALID)
  945                 return (0);
  947         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
  948                 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
  949                         return (ENOBUFS);
  950         };
sc->bge_jumbo = i - 1;
sc->bge_flags |= BGE_JUMBO_RXRING_VALID;
rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
  961         return (0);
  962 }
  964 void
bge_free_rx_ring_jumbo(struct bge_softc *sc)
  966 {
  967         int i;
  969         if (!(sc->bge_flags & BGE_JUMBO_RXRING_VALID))
  970                 return;
  972         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
  973                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
  976                 }
bzero((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i],
  978                     sizeof(struct bge_rx_bd));
  979         }
sc->bge_flags &= ~BGE_JUMBO_RXRING_VALID;
  982 }
  984 void
bge_free_tx_ring(struct bge_softc *sc)
  986 {
  987         int i;
  988         struct txdmamap_pool_entry *dma;
  990         if (!(sc->bge_flags & BGE_TXRING_VALID))
  991                 return;
  993         for (i = 0; i < BGE_TX_RING_CNT; i++) {
  994                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
m_freem(sc->bge_cdata.bge_tx_chain[i]);
sc->bge_cdata.bge_tx_chain[i] = NULL;
SLIST_INSERT_HEAD(&sc->txdma_list, sc->txdma[i],
link);
sc->txdma[i] = 0;
 1000                 }
bzero((char *)&sc->bge_rdata->bge_tx_ring[i],
 1002                     sizeof(struct bge_tx_bd));
 1003         }
 1005         while ((dma = SLIST_FIRST(&sc->txdma_list))) {
SLIST_REMOVE_HEAD(&sc->txdma_list, link);
bus_dmamap_destroy(sc->bge_dmatag, dma->dmamap);
free(dma, M_DEVBUF);
 1009         }
sc->bge_flags &= ~BGE_TXRING_VALID;
 1012 }
 1014 int
bge_init_tx_ring(struct bge_softc *sc)
 1016 {
 1017         int i;
bus_dmamap_t dmamap;
 1019         struct txdmamap_pool_entry *dma;
 1021         if (sc->bge_flags & BGE_TXRING_VALID)
 1022                 return (0);
sc->bge_txcnt = 0;
sc->bge_tx_saved_considx = 0;
 1027         /* Initialize transmit producer index for host-memory send ring. */
sc->bge_tx_prodidx = 0;
CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
 1030         if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)
CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
 1033         /* NIC-memory send ring not used; initialize to zero. */
CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
 1035         if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)
CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
SLIST_INIT(&sc->txdma_list);
 1039         for (i = 0; i < BGE_TX_RING_CNT; i++) {
 1040                 if (bus_dmamap_create(sc->bge_dmatag, BGE_JLEN,
BGE_NTXSEG, BGE_JLEN, 0, BUS_DMA_NOWAIT,
 1042                     &dmamap))
 1043                         return (ENOBUFS);
 1044                 if (dmamap == NULL)
panic("dmamap NULL in bge_init_tx_ring");
dma = malloc(sizeof(*dma), M_DEVBUF, M_NOWAIT);
 1047                 if (dma == NULL) {
printf("%s: can't alloc txdmamap_pool_entry\n",
sc->bge_dev.dv_xname);
bus_dmamap_destroy(sc->bge_dmatag, dmamap);
 1051                         return (ENOMEM);
 1052                 }
dma->dmamap = dmamap;
SLIST_INSERT_HEAD(&sc->txdma_list, dma, link);
 1055         }
sc->bge_flags |= BGE_TXRING_VALID;
 1059         return (0);
 1060 }
 1062 void
bge_iff(struct bge_softc *sc)
 1064 {
 1065         struct arpcom           *ac = &sc->arpcom;
 1066         struct ifnet            *ifp = &ac->ac_if;
 1067         struct ether_multi      *enm;
 1068         struct ether_multistep  step;
u_int8_t                hashes[16];
u_int32_t               h, rxmode;
 1072         /* First, zot all the existing filters. */
rxmode = CSR_READ_4(sc, BGE_RX_MODE) & ~BGE_RXMODE_RX_PROMISC;
ifp->if_flags &= ~IFF_ALLMULTI;
memset(hashes, 0x00, sizeof(hashes));
 1077         if (ifp->if_flags & IFF_PROMISC)
rxmode |= BGE_RXMODE_RX_PROMISC;
 1079         else if (ac->ac_multirangecnt > 0) {
ifp->if_flags |= IFF_ALLMULTI;
memset(hashes, 0xff, sizeof(hashes));
 1082         } else {
ETHER_FIRST_MULTI(step, ac, enm);
 1084                 while (enm != NULL) {
h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
setbit(hashes, h & 0x7F);
ETHER_NEXT_MULTI(step, enm);
 1088                 }
 1089         }
bus_space_write_raw_region_4(sc->bge_btag, sc->bge_bhandle, BGE_MAR0,
hashes, sizeof(hashes));
CSR_WRITE_4(sc, BGE_RX_MODE, rxmode);
 1095 }
 1097 /*
 1098  * Do endian, PCI and DMA initialization.
 1099  */
 1100 void
bge_chipinit(struct bge_softc *sc)
 1102 {
 1103         struct pci_attach_args  *pa = &(sc->bge_pa);
u_int32_t dma_rw_ctl;
 1105         int i;
 1107         /* Set endianness before we access any non-PCI registers. */
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL,
BGE_INIT);
 1111         /* Clear the MAC control register */
CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
 1114         /*
 1115          * Clear the MAC statistics block in the NIC's
 1116          * internal memory.
 1117          */
 1118         for (i = BGE_STATS_BLOCK;
i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t))
BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0);
 1122         for (i = BGE_STATUS_BLOCK;
i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t))
BGE_MEMWIN_WRITE(pa->pa_pc, pa->pa_tag, i, 0);
 1126         /* Set up the PCI DMA control register. */
 1127         if (sc->bge_flags & BGE_PCIE) {
 1128                 /* PCI Express bus */
u_int32_t device_ctl;
 1131                 /* alternative from Linux driver */
 1132 #define DMA_CTRL_WRITE_PCIE_H20MARK_128         0x00180000
 1133 #define DMA_CTRL_WRITE_PCIE_H20MARK_256         0x00380000
dma_rw_ctl = 0x76000000; /* XXX XXX XXX */;
device_ctl = pci_conf_read(pa->pa_pc, pa->pa_tag,
BGE_PCI_CONF_DEV_CTRL);
 1139                 if ((device_ctl & 0x00e0) && 0) {
 1140                         /*
 1141                          * This clause is exactly what the Broadcom-supplied
 1142                          * Linux does; but given overall register programming
 1143                          * by bge(4), this larger DMA-write watermark
 1144                          * value causes BCM5721 chips to totally wedge.
 1145                          */
dma_rw_ctl |= BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_256;
 1147                 } else {
dma_rw_ctl |= BGE_PCIDMA_RWCTL_PCIE_WRITE_WATRMARK_128;
 1149                 }
 1150         } else if (sc->bge_flags & BGE_PCIX) {
 1151                 /* PCI-X bus */
 1152                 if (BGE_IS_5714_FAMILY(sc)) {
dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
 1155                         /* XXX magic values, Broadcom-supplied Linux driver */
 1156                         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5780)
dma_rw_ctl |= (1 << 20) | (1 << 18) |
BGE_PCIDMARWCTL_ONEDMA_ATONCE;
 1159                         else
dma_rw_ctl |= (1<<20) | (1<<18) | (1 << 15);
 1161                 } else if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704)
 1162                         /*
 1163                          * The 5704 uses a different encoding of read/write
 1164                          * watermarks.
 1165                          */
dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 1167                             (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 1168                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
 1169                 else
dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
 1171                             (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 1172                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
 1173                             (0x0F);
 1175                 /*
 1176                  * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
 1177                  * for hardware bugs.
 1178                  */
 1179                 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) {
u_int32_t tmp;
tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
 1184                         if (tmp == 0x6 || tmp == 0x7)
dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
 1186                 }
 1187         } else {
 1188                 /* Conventional PCI bus */
dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD |
 1190                     (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 1191                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
 1192                     (0x0f);
 1193         }
 1195         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704 ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705)
dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL, dma_rw_ctl);
 1202         /*
 1203          * Set up general mode register.
 1204          */
 1205 #ifndef BGE_CHECKSUM
CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM);
 1209 #else
CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS);
 1212 #endif
 1214         /*
 1215          * Disable memory write invalidate.  Apparently it is not supported
 1216          * properly by these devices.
 1217          */
PCI_CLRBIT(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
PCI_COMMAND_INVALIDATE_ENABLE);
 1221 #ifdef __brokenalpha__
 1222         /*
 1223          * Must insure that we do not cross an 8K (bytes) boundary
 1224          * for DMA reads.  Our highest limit is 1K bytes.  This is a
 1225          * restriction on some ALPHA platforms with early revision
 1226          * 21174 PCI chipsets, such as the AlphaPC 164lx
 1227          */
PCI_SETBIT(pa->pa_pc, pa->pa_tag, BGE_PCI_DMA_RW_CTL,
BGE_PCI_READ_BNDRY_1024);
 1230 #endif
 1232         /* Set the timer prescaler (always 66MHz) */
CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
 1234 }
 1236 int
bge_blockinit(struct bge_softc *sc)
 1238 {
 1239         volatile struct bge_rcb         *rcb;
vaddr_t                 rcb_addr;
 1241         int                     i;
bge_hostaddr            taddr;
u_int32_t               val;
 1245         /*
 1246          * Initialize the memory window pointer register so that
 1247          * we can access the first 32K of internal NIC RAM. This will
 1248          * allow us to set up the TX send ring RCBs and the RX return
 1249          * ring RCBs, plus other things which live in NIC memory.
 1250          */
CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
 1253         /* Configure mbuf memory pool */
 1254         if (!(BGE_IS_5705_OR_BEYOND(sc))) {
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
BGE_BUFFPOOL_1);
 1258                 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704)
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
 1260                 else
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
 1263                 /* Configure DMA resource pool */
CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
BGE_DMA_DESCRIPTORS);
CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
 1267         }
 1269         /* Configure mbuf pool watermarks */
 1270         /* new Broadcom docs strongly recommend these: */
 1271         if (!(BGE_IS_5705_OR_BEYOND(sc))) {
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
 1275         } else {
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
 1279         }
 1281         /* Configure DMA resource watermarks */
CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
 1285         /* Enable buffer manager */
CSR_WRITE_4(sc, BGE_BMAN_MODE,
BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
 1289         /* Poll for buffer manager start indication */
 1290         for (i = 0; i < 2000; i++) {
 1291                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
 1292                         break;
DELAY(10);
 1294         }
 1296         if (i == 2000) {
printf("%s: buffer manager failed to start\n",
sc->bge_dev.dv_xname);
 1299                 return (ENXIO);
 1300         }
 1302         /* Enable flow-through queues */
CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
 1306         /* Wait until queue initialization is complete */
 1307         for (i = 0; i < 2000; i++) {
 1308                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
 1309                         break;
DELAY(10);
 1311         }
 1313         if (i == 2000) {
printf("%s: flow-through queue init failed\n",
sc->bge_dev.dv_xname);
 1316                 return (ENXIO);
 1317         }
 1319         /* Initialize the standard RX ring control block */
rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb;
BGE_HOSTADDR(rcb->bge_hostaddr, BGE_RING_DMA_ADDR(sc, bge_rx_std_ring));
 1322         if (BGE_IS_5705_OR_BEYOND(sc))
rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
 1324         else
rcb->bge_maxlen_flags =
BGE_RCB_MAXLEN_FLAGS(ETHER_MAX_DIX_LEN, 0);
rcb->bge_nicaddr = BGE_STD_RX_RINGS;
CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
 1333         /*
 1334          * Initialize the Jumbo RX ring control block
 1335          * We set the 'ring disabled' bit in the flags
 1336          * field until we're actually ready to start
 1337          * using this ring (i.e. once we set the MTU
 1338          * high enough to require it).
 1339          */
 1340         if (BGE_IS_JUMBO_CAPABLE(sc)) {
rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
BGE_HOSTADDR(rcb->bge_hostaddr,
BGE_RING_DMA_ADDR(sc, bge_rx_jumbo_ring));
rcb->bge_maxlen_flags =
BGE_RCB_MAXLEN_FLAGS(BGE_JUMBO_FRAMELEN,
BGE_RCB_FLAG_RING_DISABLED);
rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
rcb->bge_hostaddr.bge_addr_hi);
CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
rcb->bge_hostaddr.bge_addr_lo);
CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
rcb->bge_maxlen_flags);
CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR,
rcb->bge_nicaddr);
 1358                 /* Set up dummy disabled mini ring RCB */
rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb;
rcb->bge_maxlen_flags =
BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
rcb->bge_maxlen_flags);
bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
offsetof(struct bge_ring_data, bge_info),
 1367                     sizeof (struct bge_gib),
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
 1369         }
 1371         /*
 1372          * Set the BD ring replenish thresholds. The recommended
 1373          * values are 1/8th the number of descriptors allocated to
 1374          * each ring.
 1375          */
i = BGE_STD_RX_RING_CNT / 8;
 1378         /*
 1379          * Use a value of 8 for the following chips to workaround HW errata.
 1380          * Some of these chips have been added based on empirical
 1381          * evidence (they don't work unless this is done).
 1382          */
 1383         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5750 ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787)
i = 8;
CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, i);
CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT / 8);
 1392         /*
 1393          * Disable all unused send rings by setting the 'ring disabled'
 1394          * bit in the flags field of all the TX send ring control blocks.
 1395          * These are located in NIC memory.
 1396          */
rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
 1398         for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0);
rcb_addr += sizeof(struct bge_rcb);
 1403         }
 1405         /* Configure TX RCB 0 (we use only the first ring) */
rcb_addr = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_tx_ring));
RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
RCB_WRITE_4(sc, rcb_addr, bge_nicaddr,
BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
 1412         if (!(BGE_IS_5705_OR_BEYOND(sc)))
RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
 1416         /* Disable all unused RX return rings */
rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
 1418         for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, 0);
RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, 0);
RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
BGE_RCB_FLAG_RING_DISABLED));
RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0);
CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
 1426                     (i * (sizeof(u_int64_t))), 0);
rcb_addr += sizeof(struct bge_rcb);
 1428         }
 1430         /* Initialize RX ring indexes */
CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
 1435         /*
 1436          * Set up RX return ring 0
 1437          * Note that the NIC address for RX return rings is 0x00000000.
 1438          * The return rings live entirely within the host, so the
 1439          * nicaddr field in the RCB isn't used.
 1440          */
rcb_addr = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_rx_return_ring));
RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
RCB_WRITE_4(sc, rcb_addr, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
RCB_WRITE_4(sc, rcb_addr, bge_nicaddr, 0x00000000);
RCB_WRITE_4(sc, rcb_addr, bge_maxlen_flags,
BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
 1449         /* Set random backoff seed for TX */
CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
BGE_TX_BACKOFF_SEED_MASK);
 1456         /* Set inter-packet gap */
CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
 1459         /*
 1460          * Specify which ring to use for packets that don't match
 1461          * any RX rules.
 1462          */
CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
 1465         /*
 1466          * Configure number of RX lists. One interrupt distribution
 1467          * list, sixteen active lists, one bad frames class.
 1468          */
CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
 1471         /* Inialize RX list placement stats mask. */
CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
 1475         /* Disable host coalescing until we get it set up */
CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
 1478         /* Poll to make sure it's shut down. */
 1479         for (i = 0; i < 2000; i++) {
 1480                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
 1481                         break;
DELAY(10);
 1483         }
 1485         if (i == 2000) {
printf("%s: host coalescing engine failed to idle\n",
sc->bge_dev.dv_xname);
 1488                 return (ENXIO);
 1489         }
 1491         /* Set up host coalescing defaults */
CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
 1496         if (!(BGE_IS_5705_OR_BEYOND(sc))) {
CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
 1499         }
CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
 1503         /* Set up address of statistics block */
 1504         if (!(BGE_IS_5705_OR_BEYOND(sc))) {
CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0);
CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
BGE_RING_DMA_ADDR(sc, bge_info.bge_stats));
CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
 1512         }
 1514         /* Set up address of status block */
BGE_HOSTADDR(taddr, BGE_RING_DMA_ADDR(sc, bge_status_block));
CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, taddr.bge_addr_hi);
CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, taddr.bge_addr_lo);
sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0;
sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0;
 1522         /* Turn on host coalescing state machine */
CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
 1525         /* Turn on RX BD completion state machine and enable attentions */
CSR_WRITE_4(sc, BGE_RBDC_MODE,
BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
 1529         /* Turn on RX list placement state machine */
CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
 1532         /* Turn on RX list selector state machine. */
 1533         if (!(BGE_IS_5705_OR_BEYOND(sc)))
CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
 1536         /* Turn on DMA, clear stats */
CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
 1541             (sc->bge_flags & BGE_TBI ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
 1543         /* Set misc. local control, enable interrupts on attentions */
CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
 1546 #ifdef notdef
 1547         /* Assert GPIO pins for PHY reset */
BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
 1552 #endif
 1554         /* Turn on DMA completion state machine */
 1555         if (!(BGE_IS_5705_OR_BEYOND(sc)))
CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
 1560         /* Enable host coalescing bug fix. */
 1561         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787)
val |= (1 << 29);
 1565         /* Turn on write DMA state machine */
CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
 1568         /* Turn on read DMA state machine */
 1569         {
uint32_t dma_read_modebits;
dma_read_modebits =
BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
 1575                 if (sc->bge_flags & BGE_PCIE && 0)
dma_read_modebits |= BGE_RDMA_MODE_FIFO_LONG_BURST;
CSR_WRITE_4(sc, BGE_RDMA_MODE, dma_read_modebits);
 1579         }
 1581         /* Turn on RX data completion state machine */
CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
 1584         /* Turn on RX BD initiator state machine */
CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
 1587         /* Turn on RX data and RX BD initiator state machine */
CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
 1590         /* Turn on Mbuf cluster free state machine */
 1591         if (!(BGE_IS_5705_OR_BEYOND(sc)))
CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
 1594         /* Turn on send BD completion state machine */
CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
 1597         /* Turn on send data completion state machine */
CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
 1600         /* Turn on send data initiator state machine */
CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
 1603         /* Turn on send BD initiator state machine */
CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
 1606         /* Turn on send BD selector state machine */
CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
 1613         /* ack/clear link change events */
CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
BGE_MACSTAT_LINK_CHANGED);
 1618         /* Enable PHY auto polling (for MII/GMII only) */
 1619         if (sc->bge_flags & BGE_TBI) {
CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
 1621         } else {
BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
 1623                 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 &&
sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
BGE_EVTENB_MI_INTERRUPT);
 1627         }
 1629         /*
 1630          * Clear any pending link state attention.
 1631          * Otherwise some link state change events may be lost until attention
 1632          * is cleared by bge_intr() -> bge_link_upd() sequence.
 1633          * It's not necessary on newer BCM chips - perhaps enabling link
 1634          * state change attentions implies clearing pending attention.
 1635          */
CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
BGE_MACSTAT_LINK_CHANGED);
 1640         /* Enable link state change attentions. */
BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
 1643         return (0);
 1644 }
 1646 const struct bge_revision *
bge_lookup_rev(u_int32_t chipid)
 1648 {
 1649         const struct bge_revision *br;
 1651         for (br = bge_revisions; br->br_name != NULL; br++) {
 1652                 if (br->br_chipid == chipid)
 1653                         return (br);
 1654         }
 1656         for (br = bge_majorrevs; br->br_name != NULL; br++) {
 1657                 if (br->br_chipid == BGE_ASICREV(chipid))
 1658                         return (br);
 1659         }
 1661         return (NULL);
 1662 }
 1664 /*
 1665  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
 1666  * against our list and return its name if we find a match. Note
 1667  * that since the Broadcom controller contains VPD support, we
 1668  * can get the device name string from the controller itself instead
 1669  * of the compiled-in string. This is a little slow, but it guarantees
 1670  * we'll always announce the right product name.
 1671  */
 1672 int
bge_probe(struct device *parent, void *match, void *aux)
 1674 {
 1675         return (pci_matchbyid((struct pci_attach_args *)aux, bge_devices,
 1676             sizeof(bge_devices)/sizeof(bge_devices[0])));
 1677 }
 1679 void
bge_attach(struct device *parent, struct device *self, void *aux)
 1681 {
 1682         struct bge_softc        *sc = (struct bge_softc *)self;
 1683         struct pci_attach_args  *pa = aux;
pci_chipset_tag_t       pc = pa->pa_pc;
 1685         const struct bge_revision *br;
pcireg_t                pm_ctl, memtype, subid;
pci_intr_handle_t       ih;
 1688         const char              *intrstr = NULL;
bus_size_t              size;
bus_dma_segment_t       seg;
 1691         int                     rseg, gotenaddr = 0;
u_int32_t               hwcfg = 0;
u_int32_t               mac_addr = 0;
u_int32_t               misccfg;
 1695         struct ifnet            *ifp;
caddr_t                 kva;
 1697 #ifdef __sparc64__
 1698         int                     subvendor;
 1699 #endif
sc->bge_pa = *pa;
subid = pci_conf_read(pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
 1705         /*
 1706          * Map control/status registers.
 1707          */
DPRINTFN(5, ("Map control/status regs\n"));
DPRINTFN(5, ("pci_mapreg_map\n"));
memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, BGE_PCI_BAR0);
 1712         switch (memtype) {
 1713         case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
 1714         case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
 1715                 if (pci_mapreg_map(pa, BGE_PCI_BAR0,
memtype, 0, &sc->bge_btag, &sc->bge_bhandle,
NULL, &size, 0) == 0)
 1718                         break;
 1719         default:
printf(": can't find mem space\n");
 1721                 return;
 1722         }
DPRINTFN(5, ("pci_intr_map\n"));
 1725         if (pci_intr_map(pa, &ih)) {
printf(": couldn't map interrupt\n");
 1727                 goto fail_1;
 1728         }
DPRINTFN(5, ("pci_intr_string\n"));
intrstr = pci_intr_string(pc, ih);
 1733         /*
 1734          * Kludge for 5700 Bx bug: a hardware bug (PCIX byte enable?)
 1735          * can clobber the chip's PCI config-space power control registers,
 1736          * leaving the card in D3 powersave state.
 1737          * We do not have memory-mapped registers in this state,
 1738          * so force device into D0 state before starting initialization.
 1739          */
pm_ctl = pci_conf_read(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD);
pm_ctl &= ~(PCI_PWR_D0|PCI_PWR_D1|PCI_PWR_D2|PCI_PWR_D3);
pm_ctl |= (1 << 8) | PCI_PWR_D0 ; /* D0 state */
pci_conf_write(pc, pa->pa_tag, BGE_PCI_PWRMGMT_CMD, pm_ctl);
DELAY(1000);    /* 27 usec is allegedly sufficent */
 1746         /*
 1747          * Save ASIC rev.
 1748          */
sc->bge_chipid =
pci_conf_read(pc, pa->pa_tag, BGE_PCI_MISC_CTL) &
BGE_PCIMISCCTL_ASICREV;
printf(", ");
br = bge_lookup_rev(sc->bge_chipid);
 1756         if (br == NULL)
printf("unknown ASIC (0x%04x)", sc->bge_chipid >> 16);
 1758         else
printf("%s (0x%04x)", br->br_name, sc->bge_chipid >> 16);
 1761         /*
 1762          * PCI Express check.
 1763          */
 1764         if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS,
NULL, NULL) != 0)
sc->bge_flags |= BGE_PCIE;
 1768         /*
 1769          * PCI-X check.
 1770          */
 1771         if ((pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE) &
BGE_PCISTATE_PCI_BUSMODE) == 0)
sc->bge_flags |= BGE_PCIX;
 1775         /*
 1776          * SEEPROM check.
 1777          */
 1778 #ifdef __sparc64__
 1779         if (OF_getprop(PCITAG_NODE(pa->pa_tag), "subsystem-vendor-id",
 1780             &subvendor, sizeof(subvendor)) == sizeof(subvendor)) {
 1781                 if (subvendor == PCI_VENDOR_SUN)
sc->bge_flags |= BGE_NO_EEPROM;
 1783         }
 1784 #endif
 1786         /*
 1787          * When using the BCM5701 in PCI-X mode, data corruption has
 1788          * been observed in the first few bytes of some received packets.
 1789          * Aligning the packet buffer in memory eliminates the corruption.
 1790          * Unfortunately, this misaligns the packet payloads.  On platforms
 1791          * which do not support unaligned accesses, we will realign the
 1792          * payloads by copying the received packets.
 1793          */
 1794         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701 &&
sc->bge_flags & BGE_PCIX)
sc->bge_flags |= BGE_RX_ALIGNBUG;
 1798         if (BGE_IS_JUMBO_CAPABLE(sc))
sc->bge_flags |= BGE_JUMBO_CAP;
 1801         if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5701) &&
PCI_VENDOR(subid) == DELL_VENDORID)
sc->bge_flags |= BGE_NO_3LED;
misccfg = CSR_READ_4(sc, BGE_MISC_CFG);
misccfg &= BGE_MISCCFG_BOARD_ID_MASK;
 1809         if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5703 &&
 1810              (misccfg == 0x4000 || misccfg == 0x8000)) ||
 1811             (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 &&
PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM &&
 1813              (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901 ||
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5901A2 ||
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5705F)) ||
 1816             (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM &&
 1817              (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5751F ||
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5753F ||
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5787F)) ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906)
sc->bge_flags |= BGE_10_100_ONLY;
 1823         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 ||
 1824             (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5705 &&
 1825              (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5906)
sc->bge_flags |= BGE_NO_ETH_WIRE_SPEED;
 1830         if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5703_AX ||
BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5704_AX)
sc->bge_flags |= BGE_PHY_ADC_BUG;
 1833         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
sc->bge_flags |= BGE_PHY_5704_A0_BUG;
 1836         if (BGE_IS_5705_OR_BEYOND(sc)) {
 1837                 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787) {
 1839                         if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5722 &&
PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_BROADCOM_BCM5756)
sc->bge_flags |= BGE_PHY_JITTER_BUG;
 1842                         if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_BCM5755M)
sc->bge_flags |= BGE_PHY_ADJUST_TRIM;
 1844                 } else if (BGE_ASICREV(sc->bge_chipid) != BGE_ASICREV_BCM5906)
sc->bge_flags |= BGE_PHY_BER_BUG;
 1846         }
 1848         /* Try to reset the chip. */
DPRINTFN(5, ("bge_reset\n"));
bge_reset(sc);
bge_chipinit(sc);
 1854 #ifdef __sparc64__
 1855         if (!gotenaddr) {
 1856                 if (OF_getprop(PCITAG_NODE(pa->pa_tag), "local-mac-address",
sc->arpcom.ac_enaddr, ETHER_ADDR_LEN) == ETHER_ADDR_LEN)
gotenaddr = 1;
 1859         }
 1860 #endif
 1862         /*
 1863          * Get station address from the EEPROM.
 1864          */
 1865         if (!gotenaddr) {
mac_addr = bge_readmem_ind(sc, 0x0c14);
 1867                 if ((mac_addr >> 16) == 0x484b) {
sc->arpcom.ac_enaddr[0] = (u_char)(mac_addr >> 8);
sc->arpcom.ac_enaddr[1] = (u_char)mac_addr;
mac_addr = bge_readmem_ind(sc, 0x0c18);
sc->arpcom.ac_enaddr[2] = (u_char)(mac_addr >> 24);
sc->arpcom.ac_enaddr[3] = (u_char)(mac_addr >> 16);
sc->arpcom.ac_enaddr[4] = (u_char)(mac_addr >> 8);
sc->arpcom.ac_enaddr[5] = (u_char)mac_addr;
gotenaddr = 1;
 1876                 }
 1877         }
 1878         if (!gotenaddr && (!(sc->bge_flags & BGE_NO_EEPROM))) {
 1879                 if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN) == 0)
gotenaddr = 1;
 1882         }
 1884 #ifdef __sparc64__
 1885         if (!gotenaddr) {
 1886                 extern void myetheraddr(u_char *);
myetheraddr(sc->arpcom.ac_enaddr);
gotenaddr = 1;
 1890         }
 1891 #endif
 1893         if (!gotenaddr) {
printf(": failed to read station address\n");
 1895                 goto fail_1;
 1896         }
 1898         /* Allocate the general information block and ring buffers. */
sc->bge_dmatag = pa->pa_dmat;
DPRINTFN(5, ("bus_dmamem_alloc\n"));
 1901         if (bus_dmamem_alloc(sc->bge_dmatag, sizeof(struct bge_ring_data),
PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
printf(": can't alloc rx buffers\n");
 1904                 goto fail_1;
 1905         }
DPRINTFN(5, ("bus_dmamem_map\n"));
 1907         if (bus_dmamem_map(sc->bge_dmatag, &seg, rseg,
 1908                            sizeof(struct bge_ring_data), &kva,
BUS_DMA_NOWAIT)) {
printf(": can't map dma buffers (%d bytes)\n",
 1911                     sizeof(struct bge_ring_data));
 1912                 goto fail_2;
 1913         }
DPRINTFN(5, ("bus_dmamem_create\n"));
 1915         if (bus_dmamap_create(sc->bge_dmatag, sizeof(struct bge_ring_data), 1,
 1916             sizeof(struct bge_ring_data), 0,
BUS_DMA_NOWAIT, &sc->bge_ring_map)) {
printf(": can't create dma map\n");
 1919                 goto fail_3;
 1920         }
DPRINTFN(5, ("bus_dmamem_load\n"));
 1922         if (bus_dmamap_load(sc->bge_dmatag, sc->bge_ring_map, kva,
 1923                             sizeof(struct bge_ring_data), NULL,
BUS_DMA_NOWAIT)) {
 1925                 goto fail_4;
 1926         }
DPRINTFN(5, ("bzero\n"));
sc->bge_rdata = (struct bge_ring_data *)kva;
bzero(sc->bge_rdata, sizeof(struct bge_ring_data));
 1933         /*
 1934          * Try to allocate memory for Jumbo buffers.
 1935          */
 1936         if (BGE_IS_JUMBO_CAPABLE(sc)) {
 1937                 if (bge_alloc_jumbo_mem(sc)) {
printf(": jumbo buffer allocation failed\n");
 1939                         goto fail_5;
 1940                 }
 1941         }
 1943         /* Set default tuneable values. */
sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
sc->bge_rx_coal_ticks = 150;
sc->bge_rx_max_coal_bds = 64;
sc->bge_tx_coal_ticks = 300;
sc->bge_tx_max_coal_bds = 400;
 1950         /* 5705 limits RX return ring to 512 entries. */
 1951         if (BGE_IS_5705_OR_BEYOND(sc))
sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
 1953         else
sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
 1956         /* Set up ifnet structure */
ifp = &sc->arpcom.ac_if;
ifp->if_softc = sc;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_ioctl = bge_ioctl;
ifp->if_start = bge_start;
ifp->if_watchdog = bge_watchdog;
ifp->if_baudrate = 1000000000;
IFQ_SET_MAXLEN(&ifp->if_snd, BGE_TX_RING_CNT - 1);
IFQ_SET_READY(&ifp->if_snd);
DPRINTFN(5, ("bcopy\n"));
bcopy(sc->bge_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
ifp->if_capabilities = IFCAP_VLAN_MTU;
 1971 #if NVLAN > 0
ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
 1973 #endif
 1975         if (BGE_IS_JUMBO_CAPABLE(sc))
ifp->if_hardmtu = BGE_JUMBO_MTU;
 1978         /*
 1979          * Do MII setup.
 1980          */
DPRINTFN(5, ("mii setup\n"));
sc->bge_mii.mii_ifp = ifp;
sc->bge_mii.mii_readreg = bge_miibus_readreg;
sc->bge_mii.mii_writereg = bge_miibus_writereg;
sc->bge_mii.mii_statchg = bge_miibus_statchg;
 1987         /*
 1988          * Figure out what sort of media we have by checking the hardware
 1989          * config word in the first 32K of internal NIC memory, or fall back to
 1990          * examining the EEPROM if necessary.  Note: on some BCM5700 cards,
 1991          * this value seems to be unset. If that's the case, we have to rely on
 1992          * identifying the NIC by its PCI subsystem ID, as we do below for the
 1993          * SysKonnect SK-9D41.
 1994          */
 1995         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
 1997         else if (!(sc->bge_flags & BGE_NO_EEPROM)) {
 1998                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
 1999                     sizeof(hwcfg))) {
printf(": failed to read media type\n");
 2001                         goto fail_5;
 2002                 }
hwcfg = ntohl(hwcfg);
 2004         }
 2006         if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)           
sc->bge_flags |= BGE_TBI;
 2009         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
 2010         if (PCI_PRODUCT(subid) == SK_SUBSYSID_9D41)
sc->bge_flags |= BGE_TBI;
 2013         /* Hookup IRQ last. */
DPRINTFN(5, ("pci_intr_establish\n"));
sc->bge_intrhand = pci_intr_establish(pc, ih, IPL_NET, bge_intr, sc,
sc->bge_dev.dv_xname);
 2017         if (sc->bge_intrhand == NULL) {
printf(": couldn't establish interrupt");
 2019                 if (intrstr != NULL)
printf(" at %s", intrstr);
printf("\n");
 2022                 goto fail_5;
 2023         }
 2025         /*
 2026          * A Broadcom chip was detected. Inform the world.
 2027          */
printf(": %s, address %s\n", intrstr,
ether_sprintf(sc->arpcom.ac_enaddr));
 2031         if (sc->bge_flags & BGE_TBI) {
ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
bge_ifmedia_sts);
ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX|IFM_FDX,
 2036                             0, NULL);
ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
 2040         } else {
 2041                 /*
 2042                  * Do transceiver setup.
 2043                  */
ifmedia_init(&sc->bge_mii.mii_media, 0, bge_ifmedia_upd,
bge_ifmedia_sts);
mii_attach(&sc->bge_dev, &sc->bge_mii, 0xffffffff,
MII_PHY_ANY, MII_OFFSET_ANY, MIIF_DOPAUSE);
 2049                 if (LIST_FIRST(&sc->bge_mii.mii_phys) == NULL) {
printf("%s: no PHY found!\n", sc->bge_dev.dv_xname);
ifmedia_add(&sc->bge_mii.mii_media,
IFM_ETHER|IFM_MANUAL, 0, NULL);
ifmedia_set(&sc->bge_mii.mii_media,
IFM_ETHER|IFM_MANUAL);
 2055                 } else
ifmedia_set(&sc->bge_mii.mii_media,
IFM_ETHER|IFM_AUTO);
 2058         }
 2060         /*
 2061          * Call MI attach routine.
 2062          */
if_attach(ifp);
ether_ifattach(ifp);
sc->sc_shutdownhook = shutdownhook_establish(bge_shutdown, sc);
sc->sc_powerhook = powerhook_establish(bge_power, sc);  
timeout_set(&sc->bge_timeout, bge_tick, sc);
 2070         return;
fail_5:
bus_dmamap_unload(sc->bge_dmatag, sc->bge_ring_map);
fail_4:
bus_dmamap_destroy(sc->bge_dmatag, sc->bge_ring_map);
fail_3:
bus_dmamem_unmap(sc->bge_dmatag, kva,
 2080             sizeof(struct bge_ring_data));
fail_2:
bus_dmamem_free(sc->bge_dmatag, &seg, rseg);
fail_1:
bus_space_unmap(sc->bge_btag, sc->bge_bhandle, size);
 2087 }
 2089 void
bge_reset(struct bge_softc *sc)
 2091 {
 2092         struct pci_attach_args *pa = &sc->bge_pa;
pcireg_t cachesize, command, pcistate, new_pcistate;
u_int32_t reset;
 2095         int i, val = 0;
 2097         /* Save some important PCI state. */
cachesize = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ);
command = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD);
pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag, BGE_PCI_PCISTATE);
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL,
BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW);
 2106         /* Disable fastboot on controllers that support it. */
 2107         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5752 ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5755 ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5787)
CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0);
reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
 2114         if (sc->bge_flags & BGE_PCIE) {
 2115                 if (CSR_READ_4(sc, 0x7e2c) == 0x60) {
 2116                         /* PCI Express 1.0 system */
CSR_WRITE_4(sc, 0x7e2c, 0x20);
 2118                 }
 2119                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
 2120                         /*
 2121                          * Prevent PCI Express link training
 2122                          * during global reset.
 2123                          */
CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
reset |= (1<<29);
 2126                 }
 2127         }
 2129         /*
 2130          * Set GPHY Power Down Override to leave GPHY
 2131          * powered up in D0 uninitialized.
 2132          */
 2133         if (BGE_IS_5705_OR_BEYOND(sc))
reset |= BGE_MISCCFG_KEEP_GPHY_POWER;
 2136         /* Issue global reset */
bge_writereg_ind(sc, BGE_MISC_CFG, reset);
DELAY(1000);
 2141         if (sc->bge_flags & BGE_PCIE) {
 2142                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
pcireg_t v;
DELAY(500000); /* wait for link training to complete */
v = pci_conf_read(pa->pa_pc, pa->pa_tag, 0xc4);
pci_conf_write(pa->pa_pc, pa->pa_tag, 0xc4, v | (1<<15));
 2148                 }
 2150                 /*
 2151                  * Set PCI Express max payload size to 128 bytes
 2152                  * and clear error status.
 2153                  */
pci_conf_write(pa->pa_pc, pa->pa_tag,
BGE_PCI_CONF_DEV_CTRL, 0xf5000);
 2156         }
 2158         /* Reset some of the PCI state that got zapped by reset */
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_MISC_CTL,
BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW);
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CACHESZ, cachesize);
pci_conf_write(pa->pa_pc, pa->pa_tag, BGE_PCI_CMD, command);
bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
 2166         /* Enable memory arbiter. */
 2167         if (BGE_IS_5714_FAMILY(sc)) {
u_int32_t val;
val = CSR_READ_4(sc, BGE_MARB_MODE);
CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
 2172         } else
CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
 2175         /*
 2176          * Prevent PXE restart: write a magic number to the
 2177          * general communications memory at 0xB50.
 2178          */
bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
 2181         /*
 2182          * Poll until we see 1's complement of the magic number.
 2183          * This indicates that the firmware initialization
 2184          * is complete.  We expect this to fail if no SEEPROM
 2185          * is fitted.
 2186          */
 2187         for (i = 0; i < BGE_TIMEOUT; i++) {
val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
 2189                 if (val == ~BGE_MAGIC_NUMBER)
 2190                         break;
DELAY(10);
 2192         }
 2194         if (i >= BGE_TIMEOUT && (!(sc->bge_flags & BGE_NO_EEPROM)))
printf("%s: firmware handshake timed out\n",
sc->bge_dev.dv_xname);
 2198         /*
 2199          * XXX Wait for the value of the PCISTATE register to
 2200          * return to its original pre-reset state. This is a
 2201          * fairly good indicator of reset completion. If we don't
 2202          * wait for the reset to fully complete, trying to read
 2203          * from the device's non-PCI registers may yield garbage
 2204          * results.
 2205          */
 2206         for (i = 0; i < BGE_TIMEOUT; i++) {
new_pcistate = pci_conf_read(pa->pa_pc, pa->pa_tag,
BGE_PCI_PCISTATE);
 2209                 if ((new_pcistate & ~BGE_PCISTATE_RESERVED) ==
 2210                     (pcistate & ~BGE_PCISTATE_RESERVED))
 2211                         break;
DELAY(10);
 2213         }
 2214         if ((new_pcistate & ~BGE_PCISTATE_RESERVED) != 
 2215             (pcistate & ~BGE_PCISTATE_RESERVED)) {
DPRINTFN(5, ("%s: pcistate failed to revert\n",
sc->bge_dev.dv_xname));
 2218         }
 2220         /* Fix up byte swapping */
CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS);
CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
 2225         /*
 2226          * The 5704 in TBI mode apparently needs some special
 2227          * adjustment to insure the SERDES drive level is set
 2228          * to 1.2V.
 2229          */
 2230         if (sc->bge_flags & BGE_TBI &&
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) {
u_int32_t serdescfg;
serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
serdescfg = (serdescfg & ~0xFFF) | 0x880;
CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
 2237         }
 2239         if (sc->bge_flags & BGE_PCIE &&
sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
u_int32_t v;
 2243                 /* Enable PCI Express bug fix */
v = CSR_READ_4(sc, 0x7c00);
CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
 2246         }
DELAY(10000);
 2248 }
 2250 /*
 2251  * Frame reception handling. This is called if there's a frame
 2252  * on the receive return list.
 2253  *
 2254  * Note: we have to be able to handle two possibilities here:
 2255  * 1) the frame is from the Jumbo receive ring
 2256  * 2) the frame is from the standard receive ring
 2257  */
 2259 void
bge_rxeof(struct bge_softc *sc)
 2261 {
 2262         struct ifnet *ifp;
 2263         int stdcnt = 0, jumbocnt = 0;
bus_dmamap_t dmamap;
bus_addr_t offset, toff;
bus_size_t tlen;
 2267         int tosync;
 2269         /* Nothing to do */
 2270         if (sc->bge_rx_saved_considx ==
sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx)
 2272                 return;
ifp = &sc->arpcom.ac_if;
bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
offsetof(struct bge_ring_data, bge_status_block),
 2278             sizeof (struct bge_status_block),
BUS_DMASYNC_POSTREAD);
offset = offsetof(struct bge_ring_data, bge_rx_return_ring);
tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx -
sc->bge_rx_saved_considx;
toff = offset + (sc->bge_rx_saved_considx * sizeof (struct bge_rx_bd));
 2287         if (tosync < 0) {
tlen = (sc->bge_return_ring_cnt - sc->bge_rx_saved_considx) *
 2289                     sizeof (struct bge_rx_bd);
bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
toff, tlen, BUS_DMASYNC_POSTREAD);
tosync = -tosync;
 2293         }
bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
offset, tosync * sizeof (struct bge_rx_bd),
BUS_DMASYNC_POSTREAD);
 2299         while(sc->bge_rx_saved_considx !=
sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) {
 2301                 struct bge_rx_bd        *cur_rx;
u_int32_t               rxidx;
 2303                 struct mbuf             *m = NULL;
 2304 #ifdef BGE_CHECKSUM
 2305                 int                     sumflags = 0;
 2306 #endif
cur_rx = &sc->bge_rdata->
bge_rx_return_ring[sc->bge_rx_saved_considx];
rxidx = cur_rx->bge_idx;
BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
 2314                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
jumbocnt++;
 2319                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
ifp->if_ierrors++;
bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
 2322                                 continue;
 2323                         }
 2324                         if (bge_newbuf_jumbo(sc, sc->bge_jumbo, NULL)
 2325                             == ENOBUFS) {
 2326                                 struct mbuf             *m0;
m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
cur_rx->bge_len - ETHER_CRC_LEN +
ETHER_ALIGN, 0, ifp, NULL);
bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
 2331                                 if (m0 == NULL) {
ifp->if_ierrors++;
 2333                                         continue;
 2334                                 }
m_adj(m0, ETHER_ALIGN);
m = m0;
 2337                         }
 2338                 } else {
BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
m = sc->bge_cdata.bge_rx_std_chain[rxidx];
sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
stdcnt++;
dmamap = sc->bge_cdata.bge_rx_std_map[rxidx];
sc->bge_cdata.bge_rx_std_map[rxidx] = 0;
bus_dmamap_unload(sc->bge_dmatag, dmamap);
 2346                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
ifp->if_ierrors++;
bge_newbuf_std(sc, sc->bge_std, m, dmamap);
 2349                                 continue;
 2350                         }
 2351                         if (bge_newbuf_std(sc, sc->bge_std,
NULL, dmamap) == ENOBUFS) {
ifp->if_ierrors++;
bge_newbuf_std(sc, sc->bge_std, m, dmamap);
 2355                                 continue;
 2356                         }
 2357                 }
ifp->if_ipackets++;
 2360 #ifdef __STRICT_ALIGNMENT
 2361                 /*
 2362                  * The i386 allows unaligned accesses, but for other
 2363                  * platforms we must make sure the payload is aligned.
 2364                  */
 2365                 if (sc->bge_flags & BGE_RX_ALIGNBUG) {
bcopy(m->m_data, m->m_data + ETHER_ALIGN,
cur_rx->bge_len);
m->m_data += ETHER_ALIGN;
 2369                 }
 2370 #endif
m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 
m->m_pkthdr.rcvif = ifp;
 2374 #if NBPFILTER > 0
 2375                 /*
 2376                  * Handle BPF listeners. Let the BPF user see the packet.
 2377                  */
 2378                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN);
 2380 #endif
 2382 #ifdef BGE_CHECKSUM
 2383                 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
sumflags |= M_IPV4_CSUM_IN_OK;
 2385                 else
sumflags |= M_IPV4_CSUM_IN_BAD;
 2388                 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
m->m_pkthdr.csum_data =
cur_rx->bge_tcp_udp_csum;
m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
 2392                 }
m->m_pkthdr.csum_flags = sumflags;
sumflags = 0;
 2396 #endif
ether_input_mbuf(ifp, m);
 2398         }
CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
 2401         if (stdcnt)
CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
 2403         if (jumbocnt)
CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
 2405 }
 2407 void
bge_txeof(struct bge_softc *sc)
 2409 {
 2410         struct bge_tx_bd *cur_tx = NULL;
 2411         struct ifnet *ifp;
 2412         struct txdmamap_pool_entry *dma;
bus_addr_t offset, toff;
bus_size_t tlen;
 2415         int tosync;
 2416         struct mbuf *m;
 2418         /* Nothing to do */
 2419         if (sc->bge_tx_saved_considx ==
sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx)
 2421                 return;
ifp = &sc->arpcom.ac_if;
bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
offsetof(struct bge_ring_data, bge_status_block),
 2427             sizeof (struct bge_status_block),
BUS_DMASYNC_POSTREAD);
offset = offsetof(struct bge_ring_data, bge_tx_ring);
tosync = sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx -
sc->bge_tx_saved_considx;
toff = offset + (sc->bge_tx_saved_considx * sizeof (struct bge_tx_bd));
 2436         if (tosync < 0) {
tlen = (BGE_TX_RING_CNT - sc->bge_tx_saved_considx) *
 2438                     sizeof (struct bge_tx_bd);
bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
toff, tlen, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
tosync = -tosync;
 2442         }
bus_dmamap_sync(sc->bge_dmatag, sc->bge_ring_map,
offset, tosync * sizeof (struct bge_tx_bd),
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
 2448         /*
 2449          * Go through our tx ring and free mbufs for those
 2450          * frames that have been sent.
 2451          */
 2452         while (sc->bge_tx_saved_considx !=
sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) {
u_int32_t               idx = 0;
idx = sc->bge_tx_saved_considx;
cur_tx = &sc->bge_rdata->bge_tx_ring[idx];
 2458                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
ifp->if_opackets++;
m = sc->bge_cdata.bge_tx_chain[idx];
 2461                 if (m != NULL) {
sc->bge_cdata.bge_tx_chain[idx] = NULL;
dma = sc->txdma[idx];
bus_dmamap_sync(sc->bge_dmatag, dma->dmamap, 0,
dma->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->bge_dmatag, dma->dmamap);
SLIST_INSERT_HEAD(&sc->txdma_list, dma, link);
sc->txdma[idx] = NULL;
m_freem(m);
 2471                 }
sc->bge_txcnt--;
BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
ifp->if_timer = 0;
 2475         }
 2477         if (cur_tx != NULL)
ifp->if_flags &= ~IFF_OACTIVE;
 2479 }
 2481 int
bge_intr(void *xsc)
 2483 {
 2484         struct bge_softc *sc;
 2485         struct ifnet *ifp;
u_int32_t statusword;
sc = xsc;
ifp = &sc->arpcom.ac_if;
 2491         /* It is possible for the interrupt to arrive before
 2492          * the status block is updated prior to the interrupt.
 2493          * Reading the PCI State register will confirm whether the
 2494          * interrupt is ours and will flush the status block.
 2495          */
 2497         /* read status word from status block */
statusword = sc->bge_rdata->bge_status_block.bge_status;
 2500         if ((statusword & BGE_STATFLAG_UPDATED) ||
 2501             (!(CSR_READ_4(sc, BGE_PCI_PCISTATE) & BGE_PCISTATE_INTR_NOT_ACTIVE))) {
 2503                 /* Ack interrupt and stop others from occurring. */
CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
 2506                 /* clear status word */
sc->bge_rdata->bge_status_block.bge_status = 0;
 2509                 if ((BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 &&
sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
statusword & BGE_STATFLAG_LINKSTATE_CHANGED ||
sc->bge_link_evt)
bge_link_upd(sc);
 2515                 if (ifp->if_flags & IFF_RUNNING) {
 2516                         /* Check RX return ring producer/consumer */
bge_rxeof(sc);
 2519                         /* Check TX ring producer/consumer */
bge_txeof(sc);
 2521                 }
 2523                 /* Re-enable interrupts. */
CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
 2526                 if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd))
bge_start(ifp);
 2529                 return (1);
 2530         } else
 2531                 return (0);
 2532 }
 2534 void
bge_tick(void *xsc)
 2536 {
 2537         struct bge_softc *sc = xsc;
 2538         struct mii_data *mii = &sc->bge_mii;
 2539         int s;
s = splnet();
 2543         if (BGE_IS_5705_OR_BEYOND(sc))
bge_stats_update_regs(sc);
 2545         else
bge_stats_update(sc);
 2548         if (sc->bge_flags & BGE_TBI) {
 2549                 /*
 2550                  * Since in TBI mode auto-polling can't be used we should poll
 2551                  * link status manually. Here we register pending link event
 2552                  * and trigger interrupt.
 2553                  */
sc->bge_link_evt++;
BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
 2556         } else
mii_tick(mii);
timeout_add(&sc->bge_timeout, hz);
splx(s);
 2562 }
 2564 void
bge_stats_update_regs(struct bge_softc *sc)
 2566 {
 2567         struct ifnet *ifp;
 2568         struct bge_mac_stats_regs stats;
u_int32_t *s;
u_long cnt;
 2571         int i;
ifp = &sc->arpcom.ac_if;
s = (u_int32_t *)&stats;
 2576         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
 2577                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
s++;
 2579         }
cnt = stats.dot3StatsSingleCollisionFrames +
stats.dot3StatsMultipleCollisionFrames +
stats.dot3StatsExcessiveCollisions +
stats.dot3StatsLateCollisions;
ifp->if_collisions += cnt >= sc->bge_tx_collisions ?
cnt - sc->bge_tx_collisions : cnt;
sc->bge_tx_collisions = cnt;
 2588 }
 2590 void
bge_stats_update(struct bge_softc *sc)
 2592 {
 2593         struct ifnet *ifp = &sc->arpcom.ac_if;
bus_size_t stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
u_long cnt;
 2597 #define READ_STAT(sc, stats, stat) \
CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
cnt = READ_STAT(sc, stats,
txstats.dot3StatsSingleCollisionFrames.bge_addr_lo);
cnt += READ_STAT(sc, stats,
txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo);
cnt += READ_STAT(sc, stats,
txstats.dot3StatsExcessiveCollisions.bge_addr_lo);
cnt += READ_STAT(sc, stats,
txstats.dot3StatsLateCollisions.bge_addr_lo);
ifp->if_collisions += cnt >= sc->bge_tx_collisions ?
cnt - sc->bge_tx_collisions : cnt;
sc->bge_tx_collisions = cnt;
cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
ifp->if_ierrors += cnt >= sc->bge_rx_discards ?
cnt - sc->bge_rx_discards : cnt;
sc->bge_rx_discards = cnt;
cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
ifp->if_oerrors += cnt >= sc->bge_tx_discards ?
cnt - sc->bge_tx_discards : cnt;
sc->bge_tx_discards = cnt;
 2622 #undef READ_STAT
 2623 }
 2625 /*
 2626  * Compact outbound packets to avoid bug with DMA segments less than 8 bytes.
 2627  */
 2628 int
bge_compact_dma_runt(struct mbuf *pkt)
 2630 {
 2631         struct mbuf     *m, *prev, *n = NULL;
 2632         int             totlen, prevlen, newprevlen;
prev = NULL;
totlen = 0;
prevlen = -1;
 2638         for (m = pkt; m != NULL; prev = m,m = m->m_next) {
 2639                 int mlen = m->m_len;
 2640                 int shortfall = 8 - mlen ;
totlen += mlen;
 2643                 if (mlen == 0)
 2644                         continue;
 2645                 if (mlen >= 8)
 2646                         continue;
 2648                 /* If we get here, mbuf data is too small for DMA engine.
 2649                  * Try to fix by shuffling data to prev or next in chain.
 2650                  * If that fails, do a compacting deep-copy of the whole chain.
 2651                  */
 2653                 /* Internal frag. If fits in prev, copy it there. */
 2654                 if (prev && M_TRAILINGSPACE(prev) >= m->m_len) {
bcopy(m->m_data,
prev->m_data+prev->m_len,
mlen);
prev->m_len += mlen;
m->m_len = 0;
 2660                         /* XXX stitch chain */
prev->m_next = m_free(m);
m = prev;
 2663                         continue;
 2664                 } else if (m->m_next != NULL &&
M_TRAILINGSPACE(m) >= shortfall &&
m->m_next->m_len >= (8 + shortfall)) {
 2667                         /* m is writable and have enough data in next, pull up. */
bcopy(m->m_next->m_data,
m->m_data+m->m_len,
shortfall);
m->m_len += shortfall;
m->m_next->m_len -= shortfall;
m->m_next->m_data += shortfall;
 2675                 } else if (m->m_next == NULL || 1) {
 2676                         /* Got a runt at the very end of the packet.
 2677                          * borrow data from the tail of the preceding mbuf and
 2678                          * update its length in-place. (The original data is still
 2679                          * valid, so we can do this even if prev is not writable.)
 2680                          */
 2682                         /* if we'd make prev a runt, just move all of its data. */
 2683 #ifdef DEBUG
KASSERT(prev != NULL /*, ("runt but null PREV")*/);
KASSERT(prev->m_len >= 8 /*, ("runt prev")*/);
 2686 #endif
 2687                         if ((prev->m_len - shortfall) < 8)
shortfall = prev->m_len;
newprevlen = prev->m_len - shortfall;
MGET(n, M_NOWAIT, MT_DATA);
 2693                         if (n == NULL)
 2694                                 return (ENOBUFS);
KASSERT(m->m_len + shortfall < MLEN
 2696                                 /*,
 2697                                   ("runt %d +prev %d too big\n", m->m_len, shortfall)*/);
 2699                         /* first copy the data we're stealing from prev */
bcopy(prev->m_data + newprevlen, n->m_data, shortfall);
 2702                         /* update prev->m_len accordingly */
prev->m_len -= shortfall;
 2705                         /* copy data from runt m */
bcopy(m->m_data, n->m_data + shortfall, m->m_len);
 2708                         /* n holds what we stole from prev, plus m */
n->m_len = shortfall + m->m_len;
 2711                         /* stitch n into chain and free m */
n->m_next = m->m_next;
prev->m_next = n;
 2714                         /* KASSERT(m->m_next == NULL); */
m->m_next = NULL;
m_free(m);
m = n;  /* for continuing loop */
 2718                 }
prevlen = m->m_len;
 2720         }
 2721         return (0);
 2722 }
 2724 /*
 2725  * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
 2726  * pointers to descriptors.
 2727  */
 2728 int
bge_encap(struct bge_softc *sc, struct mbuf *m_head, u_int32_t *txidx)
 2730 {
 2731         struct bge_tx_bd        *f = NULL;
u_int32_t               frag, cur;
u_int16_t               csum_flags = 0;
 2734         struct txdmamap_pool_entry *dma;
bus_dmamap_t dmamap;
 2736         int                     i = 0;
 2737 #if NVLAN > 0
 2738         struct ifvlan           *ifv = NULL;
 2740         if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
m_head->m_pkthdr.rcvif != NULL)
ifv = m_head->m_pkthdr.rcvif->if_softc;
 2743 #endif
cur = frag = *txidx;
 2747 #ifdef BGE_CHECKSUM
 2748         if (m_head->m_pkthdr.csum_flags) {
 2749                 if (m_head->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT)
csum_flags |= BGE_TXBDFLAG_IP_CSUM;
 2751                 if (m_head->m_pkthdr.csum_flags & (M_TCPV4_CSUM_OUT |
M_UDPV4_CSUM_OUT))
csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
 2754 #ifdef fake
 2755                 if (m_head->m_flags & M_LASTFRAG)
csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
 2757                 else if (m_head->m_flags & M_FRAG)
csum_flags |= BGE_TXBDFLAG_IP_FRAG;
 2759 #endif
 2760         }
 2761 #endif
 2762         if (!(BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX))
 2763                 goto doit;
 2765         /*
 2766          * bcm5700 Revision B silicon cannot handle DMA descriptors with
 2767          * less than eight bytes.  If we encounter a teeny mbuf
 2768          * at the end of a chain, we can pad.  Otherwise, copy.
 2769          */
 2770         if (bge_compact_dma_runt(m_head) != 0)
 2771                 return (ENOBUFS);
doit:
dma = SLIST_FIRST(&sc->txdma_list);
 2775         if (dma == NULL)
 2776                 return (ENOBUFS);
dmamap = dma->dmamap;
 2779         /*
 2780          * Start packing the mbufs in this chain into
 2781          * the fragment pointers. Stop when we run out
 2782          * of fragments or hit the end of the mbuf chain.
 2783          */
 2784         if (bus_dmamap_load_mbuf(sc->bge_dmatag, dmamap, m_head,
BUS_DMA_NOWAIT))
 2786                 return (ENOBUFS);
 2788         /*
 2789          * Sanity check: avoid coming within 16 descriptors
 2790          * of the end of the ring.
 2791          */
 2792         if (dmamap->dm_nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16))
 2793                 goto fail_unload;
 2795         for (i = 0; i < dmamap->dm_nsegs; i++) {
f = &sc->bge_rdata->bge_tx_ring[frag];
 2797                 if (sc->bge_cdata.bge_tx_chain[frag] != NULL)
 2798                         break;
BGE_HOSTADDR(f->bge_addr, dmamap->dm_segs[i].ds_addr);
f->bge_len = dmamap->dm_segs[i].ds_len;
f->bge_flags = csum_flags;
 2802 #if NVLAN > 0
 2803                 if (ifv != NULL) {
f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
f->bge_vlan_tag = ifv->ifv_tag;
 2806                 } else {
f->bge_vlan_tag = 0;
 2808                 }
 2809 #endif
cur = frag;
BGE_INC(frag, BGE_TX_RING_CNT);
 2812         }
 2814         if (i < dmamap->dm_nsegs)
 2815                 goto fail_unload;
bus_dmamap_sync(sc->bge_dmatag, dmamap, 0, dmamap->dm_mapsize,
BUS_DMASYNC_PREWRITE);
 2820         if (frag == sc->bge_tx_saved_considx)
 2821                 goto fail_unload;
sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END;
sc->bge_cdata.bge_tx_chain[cur] = m_head;
SLIST_REMOVE_HEAD(&sc->txdma_list, link);
sc->txdma[cur] = dma;
sc->bge_txcnt += dmamap->dm_nsegs;
 2829         *txidx = frag;
 2831         return (0);
fail_unload:
bus_dmamap_unload(sc->bge_dmatag, dmamap);
 2836         return (ENOBUFS);
 2837 }
 2839 /*
 2840  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
 2841  * to the mbuf data regions directly in the transmit descriptors.
 2842  */
 2843 void
bge_start(struct ifnet *ifp)
 2845 {
 2846         struct bge_softc *sc;
 2847         struct mbuf *m_head = NULL;
u_int32_t prodidx;
 2849         int pkts = 0;
sc = ifp->if_softc;
 2853         if (!sc->bge_link || IFQ_IS_EMPTY(&ifp->if_snd))
 2854                 return;
prodidx = sc->bge_tx_prodidx;
 2858         while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
IFQ_POLL(&ifp->if_snd, m_head);
 2860                 if (m_head == NULL)
 2861                         break;
 2863                 /*
 2864                  * Pack the data into the transmit ring. If we
 2865                  * don't have room, set the OACTIVE flag and wait
 2866                  * for the NIC to drain the ring.
 2867                  */
 2868                 if (bge_encap(sc, m_head, &prodidx)) {
ifp->if_flags |= IFF_OACTIVE;
 2870                         break;
 2871                 }
 2873                 /* now we are committed to transmit the packet */
IFQ_DEQUEUE(&ifp->if_snd, m_head);
pkts++;
 2877 #if NBPFILTER > 0
 2878                 /*
 2879                  * If there's a BPF listener, bounce a copy of this frame
 2880                  * to him.
 2881                  */
 2882                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT);
 2884 #endif
 2885         }
 2886         if (pkts == 0)
 2887                 return;
 2889         /* Transmit */
CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
 2891         if (BGE_CHIPREV(sc->bge_chipid) == BGE_CHIPREV_5700_BX)
CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
sc->bge_tx_prodidx = prodidx;
 2896         /*
 2897          * Set a timeout in case the chip goes out to lunch.
 2898          */
ifp->if_timer = 5;
 2900 }
 2902 void
bge_init(void *xsc)
 2904 {
 2905         struct bge_softc *sc = xsc;
 2906         struct ifnet *ifp;
u_int16_t *m;
 2908         int s;
s = splnet();
ifp = &sc->arpcom.ac_if;
 2914         /* Cancel pending I/O and flush buffers. */
bge_stop(sc);
bge_reset(sc);
bge_chipinit(sc);
 2919         /*
 2920          * Init the various state machines, ring
 2921          * control blocks and firmware.
 2922          */
 2923         if (bge_blockinit(sc)) {
printf("%s: initialization failure\n", sc->bge_dev.dv_xname);
splx(s);
 2926                 return;
 2927         }
ifp = &sc->arpcom.ac_if;
 2931         /* Specify MRU. */
 2932         if (BGE_IS_JUMBO_CAPABLE(sc))
CSR_WRITE_4(sc, BGE_RX_MTU,
BGE_JUMBO_FRAMELEN + ETHER_VLAN_ENCAP_LEN);
 2935         else
CSR_WRITE_4(sc, BGE_RX_MTU,
ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN);
 2939         /* Load our MAC address. */
m = (u_int16_t *)&sc->arpcom.ac_enaddr[0];
CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
 2944         /* Disable hardware decapsulation of vlan frames. */
BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
 2947         /* Program promiscuous mode and multicast filters. */
bge_iff(sc);
 2950         /* Init RX ring. */
bge_init_rx_ring_std(sc);
 2953         /*
 2954          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
 2955          * memory to insure that the chip has in fact read the first
 2956          * entry of the ring.
 2957          */
 2958         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
u_int32_t               v, i;
 2960                 for (i = 0; i < 10; i++) {
DELAY(20);
v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
 2963                         if (v == (MCLBYTES - ETHER_ALIGN))
 2964                                 break;
 2965                 }
 2966                 if (i == 10)
printf("%s: 5705 A0 chip failed to load RX ring\n",
sc->bge_dev.dv_xname);
 2969         }
 2971         /* Init Jumbo RX ring. */
 2972         if (BGE_IS_JUMBO_CAPABLE(sc))
bge_init_rx_ring_jumbo(sc);
 2975         /* Init our RX return ring index */
sc->bge_rx_saved_considx = 0;
 2978         /* Init TX ring. */
bge_init_tx_ring(sc);
 2981         /* Turn on transmitter */
BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
 2984         /* Turn on receiver */
BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
 2989         /* Tell firmware we're alive. */
BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
 2992         /* Enable host interrupts. */
BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
bge_ifmedia_upd(ifp);
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
splx(s);
timeout_add(&sc->bge_timeout, hz);
 3005 }
 3007 /*
 3008  * Set media options.
 3009  */
 3010 int
bge_ifmedia_upd(struct ifnet *ifp)
 3012 {
 3013         struct bge_softc *sc = ifp->if_softc;
 3014         struct mii_data *mii = &sc->bge_mii;
 3015         struct ifmedia *ifm = &sc->bge_ifmedia;
 3017         /* If this is a 1000baseX NIC, enable the TBI port. */
 3018         if (sc->bge_flags & BGE_TBI) {
 3019                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
 3020                         return (EINVAL);
 3021                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
 3022                 case IFM_AUTO:
 3023                         /*
 3024                          * The BCM5704 ASIC appears to have a special
 3025                          * mechanism for programming the autoneg
 3026                          * advertisement registers in TBI mode.
 3027                          */
 3028                         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704) {
u_int32_t sgdig;
CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
sgdig |= BGE_SGDIGCFG_AUTO|
BGE_SGDIGCFG_PAUSE_CAP|
BGE_SGDIGCFG_ASYM_PAUSE;
CSR_WRITE_4(sc, BGE_SGDIG_CFG,
sgdig|BGE_SGDIGCFG_SEND);
DELAY(5);
CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
 3039                         }
 3040                         break;
 3041                 case IFM_1000_SX:
 3042                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
BGE_CLRBIT(sc, BGE_MAC_MODE,
BGE_MACMODE_HALF_DUPLEX);
 3045                         } else {
BGE_SETBIT(sc, BGE_MAC_MODE,
BGE_MACMODE_HALF_DUPLEX);
 3048                         }
 3049                         break;
 3050                 default:
 3051                         return (EINVAL);
 3052                 }
 3053                 /* XXX 802.3x flow control for 1000BASE-SX */
 3054                 return (0);
 3055         }
sc->bge_link_evt++;
 3058         if (mii->mii_instance) {
 3059                 struct mii_softc *miisc;
LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
mii_phy_reset(miisc);
 3062         }
mii_mediachg(mii);
 3065         return (0);
 3066 }
 3068 /*
 3069  * Report current media status.
 3070  */
 3071 void
bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
 3073 {
 3074         struct bge_softc *sc = ifp->if_softc;
 3075         struct mii_data *mii = &sc->bge_mii;
 3077         if (sc->bge_flags & BGE_TBI) {
ifmr->ifm_status = IFM_AVALID;
ifmr->ifm_active = IFM_ETHER;
 3080                 if (CSR_READ_4(sc, BGE_MAC_STS) &
BGE_MACSTAT_TBI_PCS_SYNCHED) {
ifmr->ifm_status |= IFM_ACTIVE;
 3083                 } else {
ifmr->ifm_active |= IFM_NONE;
 3085                         return;
 3086                 }
ifmr->ifm_active |= IFM_1000_SX;
 3088                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
ifmr->ifm_active |= IFM_HDX;
 3090                 else
ifmr->ifm_active |= IFM_FDX;
 3092                 return;
 3093         }
mii_pollstat(mii);
ifmr->ifm_status = mii->mii_media_status;
ifmr->ifm_active = (mii->mii_media_active & ~IFM_ETH_FMASK) |
sc->bge_flowflags;
 3099 }
 3101 int
bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
 3103 {
 3104         struct bge_softc *sc = ifp->if_softc;
 3105         struct ifreq *ifr = (struct ifreq *) data;
 3106         struct ifaddr *ifa = (struct ifaddr *)data;
 3107         int s, error = 0;
 3108         struct mii_data *mii;
s = splnet();
 3112         if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) {
splx(s);
 3114                 return (error);
 3115         }
 3117         switch(command) {
 3118         case SIOCSIFADDR:
ifp->if_flags |= IFF_UP;
 3120                 if (!(ifp->if_flags & IFF_RUNNING))
bge_init(sc);
 3122 #ifdef INET
 3123                 if (ifa->ifa_addr->sa_family == AF_INET)
arp_ifinit(&sc->arpcom, ifa);
 3125 #endif /* INET */
 3126                 break;
 3127         case SIOCSIFMTU:
 3128                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ifp->if_hardmtu)
error = EINVAL;
 3130                 else if (ifp->if_mtu != ifr->ifr_mtu)
ifp->if_mtu = ifr->ifr_mtu;
 3132                 break;
 3133         case SIOCSIFFLAGS:
 3134                 if (ifp->if_flags & IFF_UP) {
 3135                         if (ifp->if_flags & IFF_RUNNING)
bge_iff(sc);
 3137                         else
bge_init(sc);
 3139                 } else {
 3140                         if (ifp->if_flags & IFF_RUNNING)
bge_stop(sc);
 3142                 }
sc->bge_if_flags = ifp->if_flags;
 3144                 break;
 3145         case SIOCADDMULTI:
 3146         case SIOCDELMULTI:
error = (command == SIOCADDMULTI)
 3148                         ? ether_addmulti(ifr, &sc->arpcom)
 3149                         : ether_delmulti(ifr, &sc->arpcom);
 3151                 if (error == ENETRESET) {
 3152                         if (ifp->if_flags & IFF_RUNNING)
bge_iff(sc);
error = 0;
 3155                 }
 3156                 break;
 3157         case SIOCSIFMEDIA:
 3158                 /* XXX Flow control is not supported for 1000BASE-SX */
 3159                 if (sc->bge_flags & BGE_TBI) {
ifr->ifr_media &= ~IFM_ETH_FMASK;
sc->bge_flowflags = 0;
 3162                 }
 3164                 /* Flow control requires full-duplex mode. */
 3165                 if (IFM_SUBTYPE(ifr->ifr_media) == IFM_AUTO ||
 3166                     (ifr->ifr_media & IFM_FDX) == 0) {
ifr->ifr_media &= ~IFM_ETH_FMASK;
 3168                 }
 3169                 if (IFM_SUBTYPE(ifr->ifr_media) != IFM_AUTO) {
 3170                         if ((ifr->ifr_media & IFM_ETH_FMASK) == IFM_FLOW) {
 3171                                 /* We can do both TXPAUSE and RXPAUSE. */
ifr->ifr_media |=
IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE;
 3174                         }
sc->bge_flowflags = ifr->ifr_media & IFM_ETH_FMASK;
 3176                 }
 3177                 /* FALLTHROUGH */
 3178         case SIOCGIFMEDIA:
 3179                 if (sc->bge_flags & BGE_TBI) {
error = ifmedia_ioctl(ifp, ifr, &sc->bge_ifmedia,
command);
 3182                 } else {
mii = &sc->bge_mii;
error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
command);
 3186                 }
 3187                 break;
 3188         default:
error = ENOTTY;
 3190                 break;
 3191         }
splx(s);
 3195         return (error);
 3196 }
 3198 void
bge_watchdog(struct ifnet *ifp)
 3200 {
 3201         struct bge_softc *sc;
sc = ifp->if_softc;
printf("%s: watchdog timeout -- resetting\n", sc->bge_dev.dv_xname);
bge_init(sc);
ifp->if_oerrors++;
 3210 }
 3212 void
bge_stop_block(struct bge_softc *sc, bus_size_t reg, u_int32_t bit)
 3214 {
 3215         int i;
BGE_CLRBIT(sc, reg, bit);
 3219         for (i = 0; i < BGE_TIMEOUT; i++) {
 3220                 if ((CSR_READ_4(sc, reg) & bit) == 0)
 3221                         return;
delay(100);
 3223         }
DPRINTFN(5, ("%s: block failed to stop: reg 0x%lx, bit 0x%08x\n",
sc->bge_dev.dv_xname, (u_long) reg, bit));
 3227 }
 3229 /*
 3230  * Stop the adapter and free any mbufs allocated to the
 3231  * RX and TX lists.
 3232  */
 3233 void
bge_stop(struct bge_softc *sc)
 3235 {
 3236         struct ifnet *ifp = &sc->arpcom.ac_if;
 3237         struct ifmedia_entry *ifm;
 3238         struct mii_data *mii;
 3239         int mtmp, itmp;
timeout_del(&sc->bge_timeout);
ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 3245         /*
 3246          * Disable all of the receiver blocks
 3247          */
bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
 3251         if (!(BGE_IS_5705_OR_BEYOND(sc)))
bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
 3257         /*
 3258          * Disable all of the transmit blocks
 3259          */
bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
 3265         if (!(BGE_IS_5705_OR_BEYOND(sc)))
bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
 3269         /*
 3270          * Shut down all of the memory managers and related
 3271          * state machines.
 3272          */
bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
 3275         if (!(BGE_IS_5705_OR_BEYOND(sc)))
bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
 3281         if (!(BGE_IS_5705_OR_BEYOND(sc))) {
bge_stop_block(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
bge_stop_block(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
 3284         }
 3286         /* Disable host interrupts. */
BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
 3290         /*
 3291          * Tell firmware we're shutting down.
 3292          */
BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
 3295         /* Free the RX lists. */
bge_free_rx_ring_std(sc);
 3298         /* Free jumbo RX list. */
 3299         if (BGE_IS_JUMBO_CAPABLE(sc))
bge_free_rx_ring_jumbo(sc);
 3302         /* Free TX buffers. */
bge_free_tx_ring(sc);
 3305         /*
 3306          * Isolate/power down the PHY, but leave the media selection
 3307          * unchanged so that things will be put back to normal when
 3308          * we bring the interface back up.
 3309          */
 3310         if (!(sc->bge_flags & BGE_TBI)) {
mii = &sc->bge_mii;
itmp = ifp->if_flags;
ifp->if_flags |= IFF_UP;
ifm = mii->mii_media.ifm_cur;
mtmp = ifm->ifm_media;
ifm->ifm_media = IFM_ETHER|IFM_NONE;
mii_mediachg(mii);
ifm->ifm_media = mtmp;
ifp->if_flags = itmp;
 3320         }
sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
 3324         /*
 3325          * We can't just call bge_link_upd() cause chip is almost stopped so
 3326          * bge_link_upd -> bge_tick_locked -> bge_stats_update sequence may
 3327          * lead to hardware deadlock. So we just clearing MAC's link state
 3328          * (PHY may still have link UP).
 3329          */
sc->bge_link = 0;
 3331 }
 3333 /*
 3334  * Stop all chip I/O so that the kernel's probe routines don't
 3335  * get confused by errant DMAs when rebooting.
 3336  */
 3337 void
bge_shutdown(void *xsc)
 3339 {
 3340         struct bge_softc *sc = (struct bge_softc *)xsc;
bge_stop(sc);
bge_reset(sc);
 3344 }
 3346 void
bge_link_upd(struct bge_softc *sc)
 3348 {
 3349         struct ifnet *ifp = &sc->arpcom.ac_if;
 3350         struct mii_data *mii = &sc->bge_mii;
u_int32_t link, status;
 3353         /* Clear 'pending link event' flag */
sc->bge_link_evt = 0;
 3356         /*
 3357          * Process link state changes.
 3358          * Grrr. The link status word in the status block does
 3359          * not work correctly on the BCM5700 rev AX and BX chips,
 3360          * according to all available information. Hence, we have
 3361          * to enable MII interrupts in order to properly obtain
 3362          * async link changes. Unfortunately, this also means that
 3363          * we have to read the MAC status register to detect link
 3364          * changes, thereby adding an additional register access to
 3365          * the interrupt handler.
 3366          *
 3367          * XXX: perhaps link state detection procedure used for
 3368          * BGE_CHIPID_BCM5700_B2 can be used for other BCM5700 revisions.
 3369          */
 3371         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700 &&
sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
status = CSR_READ_4(sc, BGE_MAC_STS);
 3374                 if (status & BGE_MACSTAT_MI_INTERRUPT) {
timeout_del(&sc->bge_timeout);
bge_tick(sc);
 3378                         if (!sc->bge_link &&
mii->mii_media_status & IFM_ACTIVE &&
IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
sc->bge_link++;
 3382                         } else if (sc->bge_link &&
 3383                             (!(mii->mii_media_status & IFM_ACTIVE) ||
IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
sc->bge_link = 0;
 3386                         }
 3388                         /* Clear the interrupt */
CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
BGE_EVTENB_MI_INTERRUPT);
bge_miibus_readreg(&sc->bge_dev, 1, BRGPHY_MII_ISR);
bge_miibus_writereg(&sc->bge_dev, 1, BRGPHY_MII_IMR,
BRGPHY_INTRS);
 3394                 }
 3395                 return;
 3396         } 
 3398         if (sc->bge_flags & BGE_TBI) {
status = CSR_READ_4(sc, BGE_MAC_STS);
 3400                 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
 3401                         if (!sc->bge_link) {
sc->bge_link++;
 3403                                 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5704)
BGE_CLRBIT(sc, BGE_MAC_MODE,
BGE_MACMODE_TBI_SEND_CFGS);
CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
status = CSR_READ_4(sc, BGE_MAC_MODE);
ifp->if_link_state =
 3409                                     (status & BGE_MACMODE_HALF_DUPLEX) ?
LINK_STATE_HALF_DUPLEX :
LINK_STATE_FULL_DUPLEX;
if_link_state_change(ifp);
 3413                         }
 3414                 } else if (sc->bge_link) {
sc->bge_link = 0;
ifp->if_link_state = LINK_STATE_DOWN;
if_link_state_change(ifp);
 3418                 }
 3419         /* Discard link events for MII/GMII cards if MI auto-polling disabled */
 3420         } else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
 3421                 /* 
 3422                  * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
 3423                  * in status word always set. Workaround this bug by reading
 3424                  * PHY link status directly.
 3425                  */
link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
 3428                 if (link != sc->bge_link ||
BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_BCM5700) {
timeout_del(&sc->bge_timeout);
bge_tick(sc);
 3433                         if (!sc->bge_link &&
mii->mii_media_status & IFM_ACTIVE &&
IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)
sc->bge_link++;
 3437                         else if (sc->bge_link &&
 3438                             (!(mii->mii_media_status & IFM_ACTIVE) ||
IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE))
sc->bge_link = 0;
 3441                 }
 3442         }
 3444         /* Clear the attention */
CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
BGE_MACSTAT_LINK_CHANGED);
 3448 }
 3450 void
bge_power(int why, void *xsc)
 3452 {
 3453         struct bge_softc *sc = (struct bge_softc *)xsc;
 3454         struct ifnet *ifp;
 3456         if (why == PWR_RESUME) {
ifp = &sc->arpcom.ac_if;
 3458                 if (ifp->if_flags & IFF_UP) {
bge_init(xsc);
 3460                         if (ifp->if_flags & IFF_RUNNING)
bge_start(ifp);
 3462                 }
 3463         }
 3464 }