root/arch/i386/pci/pcibiosvar.h

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INCLUDED FROM


    1 /*      $OpenBSD: pcibiosvar.h,v 1.17 2007/03/19 05:32:05 deraadt Exp $ */
    2 /*      $NetBSD: pcibios.h,v 1.2 2000/04/28 17:15:16 uch Exp $  */
    3 
    4 /*
    5  * Copyright (c) 1999, by UCHIYAMA Yasushi
    6  * All rights reserved.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. The name of the developer may NOT be used to endorse or promote products
   14  *    derived from this software without specific prior written permission.
   15  *
   16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   26  * SUCH DAMAGE.
   27  */
   28 
   29 /*
   30  * Data structure definitions for the PCI BIOS interface.
   31  */
   32 
   33 #define PCIBIOS_ADDR_FIXUP      0x001
   34 #define PCIBIOS_BUS_FIXUP       0x002
   35 #define PCIBIOS_INTR_FIXUP      0x004
   36 #define PCIBIOS_INTR_GUESS      0x008
   37 #define PCIBIOS_VERBOSE         0x010
   38 #define PCIBIOS_INTRDEBUG       0x020
   39 #define PCIBIOS_FIXUP_FORCE     0x040
   40 
   41 /*
   42  * PCI BIOS return codes.
   43  */
   44 #define PCIBIOS_SUCCESS                 0x00
   45 #define PCIBIOS_SERVICE_NOT_PRESENT     0x80
   46 #define PCIBIOS_FUNCTION_NOT_SUPPORTED  0x81
   47 #define PCIBIOS_BAD_VENDOR_ID           0x83
   48 #define PCIBIOS_DEVICE_NOT_FOUND        0x86
   49 #define PCIBIOS_BAD_REGISTER_NUMBER     0x87
   50 #define PCIBIOS_SET_FAILED              0x88
   51 #define PCIBIOS_BUFFER_TOO_SMALL        0x89
   52 
   53 struct pcibios_softc {
   54         struct device sc_dev;
   55 
   56         int max_bus;
   57 
   58         /* address fixup guts */
   59         struct extent *extent_mem;
   60         struct extent *extent_port;
   61         bus_addr_t mem_alloc_start;
   62         bus_addr_t port_alloc_start;
   63         int nbogus;
   64 };
   65 
   66 /*
   67  * PCI IRQ Routing Table definitions.
   68  */
   69 
   70 /*
   71  * Slot entry (per PCI 2.1)
   72  */
   73 struct pcibios_linkmap {
   74         u_int8_t        link;
   75         u_int16_t       bitmap;
   76 } __packed;
   77 
   78 struct pcibios_intr_routing {
   79         u_int8_t        bus;
   80         u_int8_t        device;
   81         struct pcibios_linkmap linkmap[4];      /* INT[A:D]# */
   82         u_int8_t        slot;
   83         u_int8_t        reserved;
   84 } __packed;
   85 
   86 /*
   87  * $PIR header.  Reference:
   88  *
   89  *      http://www.microsoft.com/whdc/archive/pciirq.mspx
   90  */
   91 struct pcibios_pir_header {
   92         u_int32_t       signature;              /* $PIR */
   93         u_int16_t       version;
   94         u_int16_t       tablesize;
   95         u_int8_t        router_bus;
   96         u_int8_t        router_devfunc;
   97         u_int16_t       exclusive_irq;
   98         u_int32_t       compat_router;          /* PCI vendor/product */
   99         u_int32_t       miniport;
  100         u_int8_t        reserved[11];
  101         u_int8_t        checksum;
  102 } __packed;
  103 
  104 #define PIR_DEVFUNC_DEVICE(devfunc)     (((devfunc) >> 3) & 0x1f)
  105 #define PIR_DEVFUNC_FUNCTION(devfunc)   ((devfunc) & 7)
  106 #define PIR_DEVFUNC_COMPOSE(dev,func)   ((((dev) &0x1f) << 3) | ((func) & 7))
  107 
  108 void    pcibios_init(void);
  109 
  110 extern struct pcibios_pir_header pcibios_pir_header;
  111 extern struct pcibios_intr_routing *pcibios_pir_table;
  112 extern int pcibios_pir_table_nentries;
  113 
  114 extern int pcibios_flags;
  115 
  116 typedef void *pciintr_icu_handle_t;
  117 
  118 struct pciintr_icu {
  119         int     (*pi_getclink)(pciintr_icu_handle_t, int, int *);
  120         int     (*pi_get_intr)(pciintr_icu_handle_t, int, int *);
  121         int     (*pi_set_intr)(pciintr_icu_handle_t, int, int);
  122         int     (*pi_get_trigger)(pciintr_icu_handle_t, int, int *);
  123         int     (*pi_set_trigger)(pciintr_icu_handle_t, int, int);
  124 };
  125 
  126 typedef const struct pciintr_icu *pciintr_icu_tag_t;
  127 
  128 #define pciintr_icu_getclink(t, h, link, pirqp)                         \
  129         (*(t)->pi_getclink)((h), (link), (pirqp))
  130 #define pciintr_icu_get_intr(t, h, pirq, irqp)                          \
  131         (*(t)->pi_get_intr)((h), (pirq), (irqp))
  132 #define pciintr_icu_set_intr(t, h, pirq, irq)                           \
  133         (*(t)->pi_set_intr)((h), (pirq), (irq))
  134 #define pciintr_icu_get_trigger(t, h, irq, triggerp)                    \
  135         (*(t)->pi_get_trigger)((h), (irq), (triggerp))
  136 #define pciintr_icu_set_trigger(t, h, irq, trigger)                     \
  137         (*(t)->pi_set_trigger)((h), (irq), (trigger))
  138 
  139 #define PCIBIOS_PRINTV(arg) \
  140         do { \
  141                 if (pcibios_flags & PCIBIOS_VERBOSE) \
  142                         printf arg; \
  143         } while (0)
  144 
  145 #define PCIADDR_SEARCH_IO       0
  146 #define PCIADDR_SEARCH_MEM      1
  147 struct extent *pciaddr_search(int, bus_addr_t *, bus_size_t);
  148 
  149 #define PCI_INT_VIA_ISA         0x20000000 /* XXX see APIC_INT_VIA_APIC */
  150 
  151 int  pci_intr_fixup(struct pcibios_softc *, pci_chipset_tag_t, bus_space_tag_t);
  152 int  pci_bus_fixup(pci_chipset_tag_t, int);
  153 void pci_addr_fixup(struct pcibios_softc *, pci_chipset_tag_t, int);
  154 void pci_device_foreach(struct pcibios_softc *, pci_chipset_tag_t, int,
  155     void (*)(struct pcibios_softc *, pci_chipset_tag_t, pcitag_t));
  156 int  pci_intr_header_fixup(pci_chipset_tag_t, pcitag_t, pci_intr_handle_t *);
  157 int  pci_intr_route_link(pci_chipset_tag_t, pci_intr_handle_t *);
  158 int  pci_intr_post_fixup(void);
  159 
  160 /*
  161  * Init functions for our known PCI ICUs.
  162  */
  163 int     piix_init(pci_chipset_tag_t, bus_space_tag_t, pcitag_t,
  164             pciintr_icu_tag_t *, pciintr_icu_handle_t *);
  165 int     opti82c558_init(pci_chipset_tag_t, bus_space_tag_t, pcitag_t,
  166             pciintr_icu_tag_t *, pciintr_icu_handle_t *);
  167 int     opti82c700_init(pci_chipset_tag_t, bus_space_tag_t, pcitag_t,
  168             pciintr_icu_tag_t *, pciintr_icu_handle_t *);
  169 int     via82c586_init(pci_chipset_tag_t, bus_space_tag_t, pcitag_t,
  170             pciintr_icu_tag_t *, pciintr_icu_handle_t *);
  171 int     via8231_init(pci_chipset_tag_t, bus_space_tag_t, pcitag_t,
  172             pciintr_icu_tag_t *, pciintr_icu_handle_t *);
  173 int     sis85c503_init(pci_chipset_tag_t, bus_space_tag_t, pcitag_t,
  174             pciintr_icu_tag_t *, pciintr_icu_handle_t *);
  175 int     amd756_init(pci_chipset_tag_t, bus_space_tag_t, pcitag_t,
  176             pciintr_icu_tag_t *, pciintr_icu_handle_t *);
  177 int     ali1543_init(pci_chipset_tag_t, bus_space_tag_t, pcitag_t,
  178             pciintr_icu_tag_t *, pciintr_icu_handle_t *);
  179 int     osb4_init(pci_chipset_tag_t, bus_space_tag_t, pcitag_t,
  180             pciintr_icu_tag_t *, pciintr_icu_handle_t *);
  181 

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