root/dev/pci/if_wb.c

DEFINITIONS

1. wb_eeprom_putbyte
2. wb_eeprom_getword
3. wb_read_eeprom
4. wb_mii_sync
5. wb_mii_send
6. wb_mii_readreg
7. wb_mii_writereg
8. wb_miibus_readreg
9. wb_miibus_writereg
10. wb_miibus_statchg
11. wb_setmulti
12. wb_setcfg
13. wb_reset
14. wb_fixmedia
15. wb_probe
16. wb_attach
17. wb_list_tx_init
18. wb_list_rx_init
19. wb_bfree
20. wb_newbuf
21. wb_rxeof
22. wb_rxeoc
23. wb_txeof
24. wb_txeoc
25. wb_intr
26. wb_tick
27. wb_encap
28. wb_start
29. wb_init
30. wb_ifmedia_upd
31. wb_ifmedia_sts
32. wb_ioctl
33. wb_watchdog
34. wb_stop
35. wb_shutdown

    1 /*      $OpenBSD: if_wb.c,v 1.38 2007/05/26 00:36:03 krw Exp $  */
    3 /*
    4  * Copyright (c) 1997, 1998
    5  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. All advertising materials mentioning features or use of this software
   16  *    must display the following acknowledgement:
   17  *      This product includes software developed by Bill Paul.
   18  * 4. Neither the name of the author nor the names of any co-contributors
   19  *    may be used to endorse or promote products derived from this software
   20  *    without specific prior written permission.
   21  *
   22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   32  * THE POSSIBILITY OF SUCH DAMAGE.
   33  *
   34  * $FreeBSD: src/sys/pci/if_wb.c,v 1.26 1999/09/25 17:29:02 wpaul Exp $
   35  */
   37 /*
   38  * Winbond fast ethernet PCI NIC driver
   39  *
   40  * Supports various cheap network adapters based on the Winbond W89C840F
   41  * fast ethernet controller chip. This includes adapters manufactured by
   42  * Winbond itself and some made by Linksys.
   43  *
   44  * Written by Bill Paul <wpaul@ctr.columbia.edu>
   45  * Electrical Engineering Department
   46  * Columbia University, New York City
   47  */
   49 /*
   50  * The Winbond W89C840F chip is a bus master; in some ways it resembles
   51  * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has
   52  * one major difference which is that while the registers do many of
   53  * the same things as a tulip adapter, the offsets are different: where
   54  * tulip registers are typically spaced 8 bytes apart, the Winbond
   55  * registers are spaced 4 bytes apart. The receiver filter is also
   56  * programmed differently.
   57  * 
   58  * Like the tulip, the Winbond chip uses small descriptors containing
   59  * a status word, a control word and 32-bit areas that can either be used
   60  * to point to two external data blocks, or to point to a single block
   61  * and another descriptor in a linked list. Descriptors can be grouped
   62  * together in blocks to form fixed length rings or can be chained
   63  * together in linked lists. A single packet may be spread out over
   64  * several descriptors if necessary.
   65  *
   66  * For the receive ring, this driver uses a linked list of descriptors,
   67  * each pointing to a single mbuf cluster buffer, which us large enough
   68  * to hold an entire packet. The link list is looped back to created a
   69  * closed ring.
   70  *
   71  * For transmission, the driver creates a linked list of 'super descriptors'
   72  * which each contain several individual descriptors linked together.
   73  * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we
   74  * abuse as fragment pointers. This allows us to use a buffer management
   75  * scheme very similar to that used in the ThunderLAN and Etherlink XL
   76  * drivers.
   77  *
   78  * Autonegotiation is performed using the external PHY via the MII bus.
   79  * The sample boards I have all use a Davicom PHY.
   80  *
   81  * Note: the author of the Linux driver for the Winbond chip alludes
   82  * to some sort of flaw in the chip's design that seems to mandate some
   83  * drastic workaround which significantly impairs transmit performance.
   84  * I have no idea what he's on about: transmit performance with all
   85  * three of my test boards seems fine.
   86  */
   88 #include "bpfilter.h"
   90 #include <sys/param.h>
   91 #include <sys/systm.h>
   92 #include <sys/sockio.h>
   93 #include <sys/mbuf.h>
   94 #include <sys/malloc.h>
   95 #include <sys/kernel.h>
   96 #include <sys/socket.h>
   97 #include <sys/device.h>
   98 #include <sys/queue.h>
   99 #include <sys/timeout.h>
  101 #include <net/if.h>
  102 #include <net/if_dl.h>
  103 #include <net/if_types.h>
  105 #ifdef INET
  106 #include <netinet/in.h>
  107 #include <netinet/in_systm.h>
  108 #include <netinet/in_var.h>
  109 #include <netinet/ip.h>
  110 #include <netinet/if_ether.h>
  111 #endif
  113 #include <net/if_media.h>
  115 #if NBPFILTER > 0
  116 #include <net/bpf.h>
  117 #endif
  119 #include <uvm/uvm_extern.h>             /* for vtophys */
  120 #define VTOPHYS(v)      vtophys((vaddr_t)(v))
  122 #include <dev/mii/mii.h>
  123 #include <dev/mii/miivar.h>
  124 #include <dev/pci/pcireg.h>
  125 #include <dev/pci/pcivar.h>
  126 #include <dev/pci/pcidevs.h>
  128 #define WB_USEIOSPACE
  130 /* #define WB_BACKGROUND_AUTONEG */
  132 #include <dev/pci/if_wbreg.h>
  134 int wb_probe(struct device *, void *, void *);
  135 void wb_attach(struct device *, struct device *, void *);
  137 void wb_bfree(caddr_t, u_int, void *);
  138 int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *,
  139     struct mbuf *);
  140 int wb_encap(struct wb_softc *, struct wb_chain *,
  141     struct mbuf *);
  143 void wb_rxeof(struct wb_softc *);
  144 void wb_rxeoc(struct wb_softc *);
  145 void wb_txeof(struct wb_softc *);
  146 void wb_txeoc(struct wb_softc *);
  147 int wb_intr(void *);
  148 void wb_tick(void *);
  149 void wb_start(struct ifnet *);
  150 int wb_ioctl(struct ifnet *, u_long, caddr_t);
  151 void wb_init(void *);
  152 void wb_stop(struct wb_softc *);
  153 void wb_watchdog(struct ifnet *);
  154 void wb_shutdown(void *);
  155 int wb_ifmedia_upd(struct ifnet *);
  156 void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *);
  158 void wb_eeprom_putbyte(struct wb_softc *, int);
  159 void wb_eeprom_getword(struct wb_softc *, int, u_int16_t *);
  160 void wb_read_eeprom(struct wb_softc *, caddr_t, int, int, int);
  161 void wb_mii_sync(struct wb_softc *);
  162 void wb_mii_send(struct wb_softc *, u_int32_t, int);
  163 int wb_mii_readreg(struct wb_softc *, struct wb_mii_frame *);
  164 int wb_mii_writereg(struct wb_softc *, struct wb_mii_frame *);
  166 void wb_setcfg(struct wb_softc *, u_int32_t);
u_int8_t wb_calchash(caddr_t);
  168 void wb_setmulti(struct wb_softc *);
  169 void wb_reset(struct wb_softc *);
  170 void wb_fixmedia(struct wb_softc *);
  171 int wb_list_rx_init(struct wb_softc *);
  172 int wb_list_tx_init(struct wb_softc *);
  174 int wb_miibus_readreg(struct device *, int, int);
  175 void wb_miibus_writereg(struct device *, int, int, int);
  176 void wb_miibus_statchg(struct device *);
  178 #define WB_SETBIT(sc, reg, x)                           \
CSR_WRITE_4(sc, reg,                            \
CSR_READ_4(sc, reg) | x)
  182 #define WB_CLRBIT(sc, reg, x)                           \
CSR_WRITE_4(sc, reg,                            \
CSR_READ_4(sc, reg) & ~x)
  186 #define SIO_SET(x)                                      \
CSR_WRITE_4(sc, WB_SIO,                         \
CSR_READ_4(sc, WB_SIO) | x)
  190 #define SIO_CLR(x)                                      \
CSR_WRITE_4(sc, WB_SIO,                         \
CSR_READ_4(sc, WB_SIO) & ~x)
  194 /*
  195  * Send a read command and address to the EEPROM, check for ACK.
  196  */
  197 void wb_eeprom_putbyte(sc, addr)
  198         struct wb_softc         *sc;
  199         int                     addr;
  200 {
  201         int                     d, i;
d = addr | WB_EECMD_READ;
  205         /*
  206          * Feed in each bit and strobe the clock.
  207          */
  208         for (i = 0x400; i; i >>= 1) {
  209                 if (d & i) {
SIO_SET(WB_SIO_EE_DATAIN);
  211                 } else {
SIO_CLR(WB_SIO_EE_DATAIN);
  213                 }
DELAY(100);
SIO_SET(WB_SIO_EE_CLK);
DELAY(150);
SIO_CLR(WB_SIO_EE_CLK);
DELAY(100);
  219         }
  221         return;
  222 }
  224 /*
  225  * Read a word of data stored in the EEPROM at address 'addr.'
  226  */
  227 void wb_eeprom_getword(sc, addr, dest)
  228         struct wb_softc         *sc;
  229         int                     addr;
u_int16_t               *dest;
  231 {
  232         int                     i;
u_int16_t               word = 0;
  235         /* Enter EEPROM access mode. */
CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
  238         /*
  239          * Send address of word we want to read.
  240          */
wb_eeprom_putbyte(sc, addr);
CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
  245         /*
  246          * Start reading bits from EEPROM.
  247          */
  248         for (i = 0x8000; i; i >>= 1) {
SIO_SET(WB_SIO_EE_CLK);
DELAY(100);
  251                 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)
word |= i;
SIO_CLR(WB_SIO_EE_CLK);
DELAY(100);
  255         }
  257         /* Turn off EEPROM access mode. */
CSR_WRITE_4(sc, WB_SIO, 0);
  260         *dest = word;
  262         return;
  263 }
  265 /*
  266  * Read a sequence of words from the EEPROM.
  267  */
  268 void wb_read_eeprom(sc, dest, off, cnt, swap)
  269         struct wb_softc         *sc;
caddr_t                 dest;
  271         int                     off;
  272         int                     cnt;
  273         int                     swap;
  274 {
  275         int                     i;
u_int16_t               word = 0, *ptr;
  278         for (i = 0; i < cnt; i++) {
wb_eeprom_getword(sc, off + i, &word);
ptr = (u_int16_t *)(dest + (i * 2));
  281                 if (swap)
  282                         *ptr = ntohs(word);
  283                 else
  284                         *ptr = word;
  285         }
  287         return;
  288 }
  290 /*
  291  * Sync the PHYs by setting data bit and strobing the clock 32 times.
  292  */
  293 void wb_mii_sync(sc)
  294         struct wb_softc         *sc;
  295 {
  296         int                     i;
SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN);
  300         for (i = 0; i < 32; i++) {
SIO_SET(WB_SIO_MII_CLK);
DELAY(1);
SIO_CLR(WB_SIO_MII_CLK);
DELAY(1);
  305         }
  307         return;
  308 }
  310 /*
  311  * Clock a series of bits through the MII.
  312  */
  313 void wb_mii_send(sc, bits, cnt)
  314         struct wb_softc         *sc;
u_int32_t               bits;
  316         int                     cnt;
  317 {
  318         int                     i;
SIO_CLR(WB_SIO_MII_CLK);
  322         for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
  323                 if (bits & i) {
SIO_SET(WB_SIO_MII_DATAIN);
  325                 } else {
SIO_CLR(WB_SIO_MII_DATAIN);
  327                 }
DELAY(1);
SIO_CLR(WB_SIO_MII_CLK);
DELAY(1);
SIO_SET(WB_SIO_MII_CLK);
  332         }
  333 }
  335 /*
  336  * Read an PHY register through the MII.
  337  */
  338 int wb_mii_readreg(sc, frame)
  339         struct wb_softc         *sc;
  340         struct wb_mii_frame     *frame;
  342 {
  343         int                     i, ack, s;
s = splnet();
  347         /*
  348          * Set up frame for RX.
  349          */
frame->mii_stdelim = WB_MII_STARTDELIM;
frame->mii_opcode = WB_MII_READOP;
frame->mii_turnaround = 0;
frame->mii_data = 0;
CSR_WRITE_4(sc, WB_SIO, 0);
  357         /*
  358          * Turn on data xmit.
  359          */
SIO_SET(WB_SIO_MII_DIR);
wb_mii_sync(sc);
  364         /*
  365          * Send command/address info.
  366          */
wb_mii_send(sc, frame->mii_stdelim, 2);
wb_mii_send(sc, frame->mii_opcode, 2);
wb_mii_send(sc, frame->mii_phyaddr, 5);
wb_mii_send(sc, frame->mii_regaddr, 5);
  372         /* Idle bit */
SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN));
DELAY(1);
SIO_SET(WB_SIO_MII_CLK);
DELAY(1);
  378         /* Turn off xmit. */
SIO_CLR(WB_SIO_MII_DIR);
  380         /* Check for ack */
SIO_CLR(WB_SIO_MII_CLK);
DELAY(1);
ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT;
SIO_SET(WB_SIO_MII_CLK);
DELAY(1);
SIO_CLR(WB_SIO_MII_CLK);
DELAY(1);
SIO_SET(WB_SIO_MII_CLK);
DELAY(1);
  391         /*
  392          * Now try reading data bits. If the ack failed, we still
  393          * need to clock through 16 cycles to keep the PHY(s) in sync.
  394          */
  395         if (ack) {
  396                 for(i = 0; i < 16; i++) {
SIO_CLR(WB_SIO_MII_CLK);
DELAY(1);
SIO_SET(WB_SIO_MII_CLK);
DELAY(1);
  401                 }
  402                 goto fail;
  403         }
  405         for (i = 0x8000; i; i >>= 1) {
SIO_CLR(WB_SIO_MII_CLK);
DELAY(1);
  408                 if (!ack) {
  409                         if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT)
frame->mii_data |= i;
DELAY(1);
  412                 }
SIO_SET(WB_SIO_MII_CLK);
DELAY(1);
  415         }
fail:
SIO_CLR(WB_SIO_MII_CLK);
DELAY(1);
SIO_SET(WB_SIO_MII_CLK);
DELAY(1);
splx(s);
  426         if (ack)
  427                 return(1);
  428         return(0);
  429 }
  431 /*
  432  * Write to a PHY register through the MII.
  433  */
  434 int wb_mii_writereg(sc, frame)
  435         struct wb_softc         *sc;
  436         struct wb_mii_frame     *frame;
  438 {
  439         int                     s;
s = splnet();
  442         /*
  443          * Set up frame for TX.
  444          */
frame->mii_stdelim = WB_MII_STARTDELIM;
frame->mii_opcode = WB_MII_WRITEOP;
frame->mii_turnaround = WB_MII_TURNAROUND;
  450         /*
  451          * Turn on data output.
  452          */
SIO_SET(WB_SIO_MII_DIR);
wb_mii_sync(sc);
wb_mii_send(sc, frame->mii_stdelim, 2);
wb_mii_send(sc, frame->mii_opcode, 2);
wb_mii_send(sc, frame->mii_phyaddr, 5);
wb_mii_send(sc, frame->mii_regaddr, 5);
wb_mii_send(sc, frame->mii_turnaround, 2);
wb_mii_send(sc, frame->mii_data, 16);
  464         /* Idle bit. */
SIO_SET(WB_SIO_MII_CLK);
DELAY(1);
SIO_CLR(WB_SIO_MII_CLK);
DELAY(1);
  470         /*
  471          * Turn off xmit.
  472          */
SIO_CLR(WB_SIO_MII_DIR);
splx(s);
  477         return(0);
  478 }
  480 int
wb_miibus_readreg(dev, phy, reg)
  482         struct device *dev;
  483         int phy, reg;
  484 {
  485         struct wb_softc *sc = (struct wb_softc *)dev;
  486         struct wb_mii_frame frame;
bzero((char *)&frame, sizeof(frame));
frame.mii_phyaddr = phy;
frame.mii_regaddr = reg;
wb_mii_readreg(sc, &frame);
  494         return(frame.mii_data);
  495 }
  497 void
wb_miibus_writereg(dev, phy, reg, data)
  499         struct device *dev;
  500         int phy, reg, data;
  501 {
  502         struct wb_softc *sc = (struct wb_softc *)dev;
  503         struct wb_mii_frame frame;
bzero((char *)&frame, sizeof(frame));
frame.mii_phyaddr = phy;
frame.mii_regaddr = reg;
frame.mii_data = data;
wb_mii_writereg(sc, &frame);
  513         return;
  514 }
  516 void
wb_miibus_statchg(dev)
  518         struct device *dev;
  519 {
  520         struct wb_softc *sc = (struct wb_softc *)dev;
wb_setcfg(sc, sc->sc_mii.mii_media_active);
  523 }
  525 /*
  526  * Program the 64-bit multicast hash filter.
  527  */
  528 void wb_setmulti(sc)
  529         struct wb_softc         *sc;
  530 {
  531         struct ifnet            *ifp;
  532         int                     h = 0;
u_int32_t               hashes[2] = { 0, 0 };
  534         struct arpcom           *ac = &sc->arpcom;
  535         struct ether_multi      *enm;
  536         struct ether_multistep  step;
u_int32_t               rxfilt;
  538         int                     mcnt = 0;
ifp = &sc->arpcom.ac_if;
rxfilt = CSR_READ_4(sc, WB_NETCFG);
allmulti:
  545         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
rxfilt |= WB_NETCFG_RX_MULTI;
CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF);
CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF);
  550                 return;
  551         }
  553         /* first, zot all the existing hash bits */
CSR_WRITE_4(sc, WB_MAR0, 0);
CSR_WRITE_4(sc, WB_MAR1, 0);
  557         /* now program new ones */
ETHER_FIRST_MULTI(step, ac, enm);
  559         while (enm != NULL) {
  560                 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
ifp->if_flags |= IFF_ALLMULTI;
  562                         goto allmulti;
  563                 }
h = ~(ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26);
  565                 if (h < 32)
hashes[0] |= (1 << h);
  567                 else
hashes[1] |= (1 << (h - 32));
mcnt++;
ETHER_NEXT_MULTI(step, enm);
  571         }
  573         if (mcnt)
rxfilt |= WB_NETCFG_RX_MULTI;
  575         else
rxfilt &= ~WB_NETCFG_RX_MULTI;
CSR_WRITE_4(sc, WB_MAR0, hashes[0]);
CSR_WRITE_4(sc, WB_MAR1, hashes[1]);
CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
  582         return;
  583 }
  585 /*
  586  * The Winbond manual states that in order to fiddle with the
  587  * 'full-duplex' and '100Mbps' bits in the netconfig register, we
  588  * first have to put the transmit and/or receive logic in the idle state.
  589  */
  590 void
wb_setcfg(sc, media)
  592         struct wb_softc *sc;
u_int32_t media;
  594 {
  595         int                     i, restart = 0;
  597         if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) {
restart = 1;
WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON));
  601                 for (i = 0; i < WB_TIMEOUT; i++) {
DELAY(10);
  603                         if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&
  604                                 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE))
  605                                 break;
  606                 }
  608                 if (i == WB_TIMEOUT)
printf("%s: failed to force tx and "
  610                                 "rx to idle state\n", sc->sc_dev.dv_xname);
  611         }
  613         if (IFM_SUBTYPE(media) == IFM_10_T)
WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
  615         else
WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
  618         if ((media & IFM_GMASK) == IFM_FDX)
WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
  620         else
WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
  623         if (restart)
WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON);
  626         return;
  627 }
  629 void
wb_reset(sc)
  631         struct wb_softc *sc;
  632 {
  633         int i;
  634         struct mii_data *mii = &sc->sc_mii;
CSR_WRITE_4(sc, WB_NETCFG, 0);
CSR_WRITE_4(sc, WB_BUSCTL, 0);
CSR_WRITE_4(sc, WB_TXADDR, 0);
CSR_WRITE_4(sc, WB_RXADDR, 0);
WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
  644         for (i = 0; i < WB_TIMEOUT; i++) {
DELAY(10);
  646                 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET))
  647                         break;
  648         }
  649         if (i == WB_TIMEOUT)
printf("%s: reset never completed!\n", sc->sc_dev.dv_xname);
  652         /* Wait a little while for the chip to get its brains in order. */
DELAY(1000);
  655         if (mii->mii_instance) {
  656                 struct mii_softc *miisc;
LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
mii_phy_reset(miisc);
  659         }
  660 }
  662 void
wb_fixmedia(sc)
  664         struct wb_softc *sc;
  665 {
  666         struct mii_data *mii = &sc->sc_mii;
u_int32_t media;
  669         if (LIST_FIRST(&mii->mii_phys) == NULL)
  670                 return;
mii_pollstat(mii);
  673         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
media = mii->mii_media_active & ~IFM_10_T;
media |= IFM_100_TX;
  676         } if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
media = mii->mii_media_active & ~IFM_100_TX;
media |= IFM_10_T;
  679         } else
  680                 return;
ifmedia_set(&mii->mii_media, media);
  683 }
  685 const struct pci_matchid wb_devices[] = {
  686         { PCI_VENDOR_WINBOND, PCI_PRODUCT_WINBOND_W89C840F },
  687         { PCI_VENDOR_COMPEX, PCI_PRODUCT_COMPEX_RL100ATX },
  688 };
  690 /*
  691  * Probe for a Winbond chip. Check the PCI vendor and device
  692  * IDs against our list and return a device name if we find a match.
  693  */
  694 int
wb_probe(parent, match, aux)
  696         struct device *parent;
  697         void *match, *aux;
  698 {
  699         return (pci_matchbyid((struct pci_attach_args *)aux, wb_devices,
  700             sizeof(wb_devices)/sizeof(wb_devices[0])));
  701 }
  703 /*
  704  * Attach the interface. Allocate softc structures, do ifmedia
  705  * setup and ethernet/BPF attach.
  706  */
  707 void
wb_attach(parent, self, aux)
  709         struct device *parent, *self;
  710         void *aux;
  711 {
  712         struct wb_softc *sc = (struct wb_softc *)self;
  713         struct pci_attach_args *pa = aux;
pci_chipset_tag_t pc = pa->pa_pc;
pci_intr_handle_t ih;
  716         const char *intrstr = NULL;
  717         struct ifnet *ifp = &sc->arpcom.ac_if;
bus_size_t size;
  719         int rseg;
pcireg_t command;
bus_dma_segment_t seg;
bus_dmamap_t dmamap;
caddr_t kva;
  725         /*
  726          * Handle power management nonsense.
  727          */
command = pci_conf_read(pc, pa->pa_tag, WB_PCI_CAPID) & 0x000000FF;
  730         if (command == 0x01) {
command = pci_conf_read(pc, pa->pa_tag, WB_PCI_PWRMGMTCTRL);
  733                 if (command & WB_PSTATE_MASK) {
u_int32_t               io, mem, irq;
  736                         /* Save important PCI config data. */
io = pci_conf_read(pc, pa->pa_tag, WB_PCI_LOIO);
mem = pci_conf_read(pc, pa->pa_tag, WB_PCI_LOMEM);
irq = pci_conf_read(pc, pa->pa_tag, WB_PCI_INTLINE);
  741                         /* Reset the power state. */
printf("%s: chip is in D%d power mode "
  743                             "-- setting to D0\n", sc->sc_dev.dv_xname,
command & WB_PSTATE_MASK);
command &= 0xFFFFFFFC;
pci_conf_write(pc, pa->pa_tag, WB_PCI_PWRMGMTCTRL,
command);
  749                         /* Restore PCI config data. */
pci_conf_write(pc, pa->pa_tag, WB_PCI_LOIO, io);
pci_conf_write(pc, pa->pa_tag, WB_PCI_LOMEM, mem);
pci_conf_write(pc, pa->pa_tag, WB_PCI_INTLINE, irq);
  753                 }
  754         }
  756         /*
  757          * Map control/status registers.
  758          */
  760 #ifdef WB_USEIOSPACE
  761         if (pci_mapreg_map(pa, WB_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0,
  762             &sc->wb_btag, &sc->wb_bhandle, NULL, &size, 0)) {
printf(": can't map i/o space\n");
  764                 return;
  765         }
  766 #else
  767         if (pci_mapreg_map(pa, WB_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0,
  768             &sc->wb_btag, &sc->wb_bhandle, NULL, &size, 0)){
printf(": can't map mem space\n");
  770                 return;
  771         }
  772 #endif
  774         /* Allocate interrupt */
  775         if (pci_intr_map(pa, &ih)) {
printf(": couldn't map interrupt\n");
  777                 goto fail_1;
  778         }
intrstr = pci_intr_string(pc, ih);
sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wb_intr, sc,
self->dv_xname);
  782         if (sc->sc_ih == NULL) {
printf(": couldn't establish interrupt");
  784                 if (intrstr != NULL)
printf(" at %s", intrstr);
printf("\n");
  787                 goto fail_1;
  788         }
printf(": %s", intrstr);
sc->wb_cachesize = pci_conf_read(pc, pa->pa_tag, WB_PCI_CACHELEN)&0xff;
  793         /* Reset the adapter. */
wb_reset(sc);
  796         /*
  797          * Get station address from the EEPROM.
  798          */
wb_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0, 3, 0);
printf(", address %s\n", ether_sprintf(sc->arpcom.ac_enaddr));
  802         if (bus_dmamem_alloc(pa->pa_dmat, sizeof(struct wb_list_data),
PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
printf(": can't alloc list data\n");
  805                 goto fail_2;
  806         }
  807         if (bus_dmamem_map(pa->pa_dmat, &seg, rseg,
  808             sizeof(struct wb_list_data), &kva, BUS_DMA_NOWAIT)) {
printf(": can't map list data, size %d\n",
  810                     sizeof(struct wb_list_data));
  811                 goto fail_3;
  812         }
  813         if (bus_dmamap_create(pa->pa_dmat, sizeof(struct wb_list_data), 1,
  814             sizeof(struct wb_list_data), 0, BUS_DMA_NOWAIT, &dmamap)) {
printf(": can't create dma map\n");
  816                 goto fail_4;
  817         }
  818         if (bus_dmamap_load(pa->pa_dmat, dmamap, kva,
  819             sizeof(struct wb_list_data), NULL, BUS_DMA_NOWAIT)) {
printf(": can't load dma map\n");
  821                 goto fail_5;
  822         }
sc->wb_ldata = (struct wb_list_data *)kva;
bzero(sc->wb_ldata, sizeof(struct wb_list_data));
ifp->if_softc = sc;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_ioctl = wb_ioctl;
ifp->if_start = wb_start;
ifp->if_watchdog = wb_watchdog;
ifp->if_baudrate = 10000000;
IFQ_SET_MAXLEN(&ifp->if_snd, WB_TX_LIST_CNT - 1);
IFQ_SET_READY(&ifp->if_snd);
bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
  837         /*
  838          * Do ifmedia setup.
  839          */
wb_stop(sc);
ifmedia_init(&sc->sc_mii.mii_media, 0, wb_ifmedia_upd, wb_ifmedia_sts);
sc->sc_mii.mii_ifp = ifp;
sc->sc_mii.mii_readreg = wb_miibus_readreg;
sc->sc_mii.mii_writereg = wb_miibus_writereg;
sc->sc_mii.mii_statchg = wb_miibus_statchg;
mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY,
  848             0);
  849         if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE,0,NULL);
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
  852         } else
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
  855         /*
  856          * Call MI attach routines.
  857          */
if_attach(ifp);
ether_ifattach(ifp);
shutdownhook_establish(wb_shutdown, sc);
  862         return;
fail_5:
bus_dmamap_destroy(pa->pa_dmat, dmamap);
fail_4:
bus_dmamem_unmap(pa->pa_dmat, kva,
  869             sizeof(struct wb_list_data));
fail_3:
bus_dmamem_free(pa->pa_dmat, &seg, rseg);
fail_2:
pci_intr_disestablish(pc, sc->sc_ih);
fail_1:
bus_space_unmap(sc->wb_btag, sc->wb_bhandle, size);
  879 }
  881 /*
  882  * Initialize the transmit descriptors.
  883  */
  884 int wb_list_tx_init(sc)
  885         struct wb_softc         *sc;
  886 {
  887         struct wb_chain_data    *cd;
  888         struct wb_list_data     *ld;
  889         int                     i;
cd = &sc->wb_cdata;
ld = sc->wb_ldata;
  894         for (i = 0; i < WB_TX_LIST_CNT; i++) {
cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i];
  896                 if (i == (WB_TX_LIST_CNT - 1)) {
cd->wb_tx_chain[i].wb_nextdesc =
  898                                 &cd->wb_tx_chain[0];
  899                 } else {
cd->wb_tx_chain[i].wb_nextdesc =
  901                                 &cd->wb_tx_chain[i + 1];
  902                 }
  903         }
cd->wb_tx_free = &cd->wb_tx_chain[0];
cd->wb_tx_tail = cd->wb_tx_head = NULL;
  908         return(0);
  909 }
  912 /*
  913  * Initialize the RX descriptors and allocate mbufs for them. Note that
  914  * we arrange the descriptors in a closed ring, so that the last descriptor
  915  * points back to the first.
  916  */
  917 int wb_list_rx_init(sc)
  918         struct wb_softc         *sc;
  919 {
  920         struct wb_chain_data    *cd;
  921         struct wb_list_data     *ld;
  922         int                     i;
cd = &sc->wb_cdata;
ld = sc->wb_ldata;
  927         for (i = 0; i < WB_RX_LIST_CNT; i++) {
cd->wb_rx_chain[i].wb_ptr =
  929                         (struct wb_desc *)&ld->wb_rx_list[i];
cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i];
  931                 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS)
  932                         return(ENOBUFS);
  933                 if (i == (WB_RX_LIST_CNT - 1)) {
cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0];
ld->wb_rx_list[i].wb_next = 
VTOPHYS(&ld->wb_rx_list[0]);
  937                 } else {
cd->wb_rx_chain[i].wb_nextdesc =
  939                                         &cd->wb_rx_chain[i + 1];
ld->wb_rx_list[i].wb_next =
VTOPHYS(&ld->wb_rx_list[i + 1]);
  942                 }
  943         }
cd->wb_rx_head = &cd->wb_rx_chain[0];
  947         return(0);
  948 }
  950 void
wb_bfree(buf, size, arg)
caddr_t                 buf;
u_int                   size;
  954         void *arg;
  955 {
  956 }
  958 /*
  959  * Initialize an RX descriptor and attach an MBUF cluster.
  960  */
  961 int
wb_newbuf(sc, c, m)
  963         struct wb_softc *sc;
  964         struct wb_chain_onefrag *c;
  965         struct mbuf *m;
  966 {
  967         struct mbuf             *m_new = NULL;
  969         if (m == NULL) {
MGETHDR(m_new, M_DONTWAIT, MT_DATA);
  971                 if (m_new == NULL)
  972                         return(ENOBUFS);
m_new->m_data = m_new->m_ext.ext_buf = c->wb_buf;
m_new->m_flags |= M_EXT;
m_new->m_ext.ext_size = m_new->m_pkthdr.len =
m_new->m_len = WB_BUFBYTES;
m_new->m_ext.ext_free = wb_bfree;
m_new->m_ext.ext_arg = NULL;
MCLINITREFERENCE(m_new);
  980         } else {
m_new = m;
m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES;
m_new->m_data = m_new->m_ext.ext_buf;
  984         }
m_adj(m_new, sizeof(u_int64_t));
c->wb_mbuf = m_new;
c->wb_ptr->wb_data = VTOPHYS(mtod(m_new, caddr_t));
c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | ETHER_MAX_DIX_LEN;
c->wb_ptr->wb_status = WB_RXSTAT;
  993         return(0);
  994 }
  996 /*
  997  * A frame has been uploaded: pass the resulting mbuf chain up to
  998  * the higher level protocols.
  999  */
 1000 void wb_rxeof(sc)
 1001         struct wb_softc         *sc;
 1002 {
 1003         struct mbuf             *m = NULL;
 1004         struct ifnet            *ifp;
 1005         struct wb_chain_onefrag *cur_rx;
 1006         int                     total_len = 0;
u_int32_t               rxstat;
ifp = &sc->arpcom.ac_if;
 1011         while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) &
WB_RXSTAT_OWN)) {
 1013                 struct mbuf *m0 = NULL;
cur_rx = sc->wb_cdata.wb_rx_head;
sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc;
m = cur_rx->wb_mbuf;
 1020                 if ((rxstat & WB_RXSTAT_MIIERR) ||
 1021                     (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) ||
 1022                     (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > ETHER_MAX_DIX_LEN) ||
 1023                     !(rxstat & WB_RXSTAT_LASTFRAG) ||
 1024                     !(rxstat & WB_RXSTAT_RXCMP)) {
ifp->if_ierrors++;
wb_newbuf(sc, cur_rx, m);
printf("%s: receiver babbling: possible chip "
 1028                                 "bug, forcing reset\n", sc->sc_dev.dv_xname);
wb_fixmedia(sc);
wb_reset(sc);
wb_init(sc);
 1032                         return;
 1033                 }
 1035                 if (rxstat & WB_RXSTAT_RXERR) {
ifp->if_ierrors++;
wb_newbuf(sc, cur_rx, m);
 1038                         break;
 1039                 }
 1041                 /* No errors; receive the packet. */    
total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status);
 1044                 /*
 1045                  * XXX The Winbond chip includes the CRC with every
 1046                  * received frame, and there's no way to turn this
 1047                  * behavior off (at least, I can't find anything in
 1048                  * the manual that explains how to do it) so we have
 1049                  * to trim off the CRC manually.
 1050                  */
total_len -= ETHER_CRC_LEN;
m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
total_len + ETHER_ALIGN, 0, ifp, NULL);
wb_newbuf(sc, cur_rx, m);
 1056                 if (m0 == NULL) {
ifp->if_ierrors++;
 1058                         break;
 1059                 }
m_adj(m0, ETHER_ALIGN);
m = m0;
ifp->if_ipackets++;
 1065 #if NBPFILTER > 0
 1066                 /*
 1067                  * Handle BPF listeners. Let the BPF user see the packet.
 1068                  */
 1069                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN);
 1071 #endif
 1072                 /* pass it on. */
ether_input_mbuf(ifp, m);
 1074         }
 1076         return;
 1077 }
 1079 void wb_rxeoc(sc)
 1080         struct wb_softc         *sc;
 1081 {
wb_rxeof(sc);
WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
CSR_WRITE_4(sc, WB_RXADDR, VTOPHYS(&sc->wb_ldata->wb_rx_list[0]));
WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
 1087         if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND)
CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
 1090         return;
 1091 }
 1093 /*
 1094  * A frame was downloaded to the chip. It's safe for us to clean up
 1095  * the list buffers.
 1096  */
 1097 void wb_txeof(sc)
 1098         struct wb_softc         *sc;
 1099 {
 1100         struct wb_chain         *cur_tx;
 1101         struct ifnet            *ifp;
ifp = &sc->arpcom.ac_if;
 1105         /* Clear the timeout timer. */
ifp->if_timer = 0;
 1108         if (sc->wb_cdata.wb_tx_head == NULL)
 1109                 return;
 1111         /*
 1112          * Go through our tx list and free mbufs for those
 1113          * frames that have been transmitted.
 1114          */
 1115         while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) {
u_int32_t               txstat;
cur_tx = sc->wb_cdata.wb_tx_head;
txstat = WB_TXSTATUS(cur_tx);
 1121                 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT)
 1122                         break;
 1124                 if (txstat & WB_TXSTAT_TXERR) {
ifp->if_oerrors++;
 1126                         if (txstat & WB_TXSTAT_ABORT)
ifp->if_collisions++;
 1128                         if (txstat & WB_TXSTAT_LATECOLL)
ifp->if_collisions++;
 1130                 }
ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3;
ifp->if_opackets++;
m_freem(cur_tx->wb_mbuf);
cur_tx->wb_mbuf = NULL;
 1138                 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) {
sc->wb_cdata.wb_tx_head = NULL;
sc->wb_cdata.wb_tx_tail = NULL;
 1141                         break;
 1142                 }
sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc;
 1145         }
 1147         return;
 1148 }
 1150 /*
 1151  * TX 'end of channel' interrupt handler.
 1152  */
 1153 void wb_txeoc(sc)
 1154         struct wb_softc         *sc;
 1155 {
 1156         struct ifnet            *ifp;
ifp = &sc->arpcom.ac_if;
ifp->if_timer = 0;
 1162         if (sc->wb_cdata.wb_tx_head == NULL) {
ifp->if_flags &= ~IFF_OACTIVE;
sc->wb_cdata.wb_tx_tail = NULL;
 1165         } else {
 1166                 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) {
WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN;
ifp->if_timer = 5;
CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
 1170                 }
 1171         }
 1173         return;
 1174 }
 1176 int wb_intr(arg)
 1177         void                    *arg;
 1178 {
 1179         struct wb_softc         *sc;
 1180         struct ifnet            *ifp;
u_int32_t               status;
 1182         int                     r = 0;
sc = arg;
ifp = &sc->arpcom.ac_if;
 1187         if (!(ifp->if_flags & IFF_UP))
 1188                 return (r);
 1190         /* Disable interrupts. */
CSR_WRITE_4(sc, WB_IMR, 0x00000000);
 1193         for (;;) {
status = CSR_READ_4(sc, WB_ISR);
 1196                 if (status)
CSR_WRITE_4(sc, WB_ISR, status);
 1199                 if ((status & WB_INTRS) == 0)
 1200                         break;
r = 1;
 1204                 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) {
ifp->if_ierrors++;
wb_reset(sc);
 1207                         if (status & WB_ISR_RX_ERR)
wb_fixmedia(sc);
wb_init(sc);
 1210                         continue;
 1211                 }
 1213                 if (status & WB_ISR_RX_OK)
wb_rxeof(sc);
 1216                 if (status & WB_ISR_RX_IDLE)
wb_rxeoc(sc);
 1219                 if (status & WB_ISR_TX_OK)
wb_txeof(sc);
 1222                 if (status & WB_ISR_TX_NOBUF)
wb_txeoc(sc);
 1225                 if (status & WB_ISR_TX_IDLE) {
wb_txeof(sc);
 1227                         if (sc->wb_cdata.wb_tx_head != NULL) {
WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
 1230                         }
 1231                 }
 1233                 if (status & WB_ISR_TX_UNDERRUN) {
ifp->if_oerrors++;
wb_txeof(sc);
WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
 1237                         /* Jack up TX threshold */
sc->wb_txthresh += WB_TXTHRESH_CHUNK;
WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
 1242                 }
 1244                 if (status & WB_ISR_BUS_ERR) {
wb_reset(sc);
wb_init(sc);
 1247                 }
 1249         }
 1251         /* Re-enable interrupts. */
CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
 1254         if (!IFQ_IS_EMPTY(&ifp->if_snd)) {
wb_start(ifp);
 1256         }
 1258         return (r);
 1259 }
 1261 void
wb_tick(xsc)
 1263         void *xsc;
 1264 {
 1265         struct wb_softc *sc = xsc;
 1266         int s;
s = splnet();
mii_tick(&sc->sc_mii);
splx(s);
timeout_add(&sc->wb_tick_tmo, hz);
 1272 }
 1274 /*
 1275  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
 1276  * pointers to the fragment pointers.
 1277  */
 1278 int wb_encap(sc, c, m_head)
 1279         struct wb_softc         *sc;
 1280         struct wb_chain         *c;
 1281         struct mbuf             *m_head;
 1282 {
 1283         int                     frag = 0;
 1284         struct wb_desc          *f = NULL;
 1285         int                     total_len;
 1286         struct mbuf             *m;
 1288         /*
 1289          * Start packing the mbufs in this chain into
 1290          * the fragment pointers. Stop when we run out
 1291          * of fragments or hit the end of the mbuf chain.
 1292          */
m = m_head;
total_len = 0;
 1296         for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
 1297                 if (m->m_len != 0) {
 1298                         if (frag == WB_MAXFRAGS)
 1299                                 break;
total_len += m->m_len;
f = &c->wb_ptr->wb_frag[frag];
f->wb_ctl = WB_TXCTL_TLINK | m->m_len;
 1303                         if (frag == 0) {
f->wb_ctl |= WB_TXCTL_FIRSTFRAG;
f->wb_status = 0;
 1306                         } else
f->wb_status = WB_TXSTAT_OWN;
f->wb_next = VTOPHYS(&c->wb_ptr->wb_frag[frag + 1]);
f->wb_data = VTOPHYS(mtod(m, vaddr_t));
frag++;
 1311                 }
 1312         }
 1314         /*
 1315          * Handle special case: we used up all 16 fragments,
 1316          * but we have more mbufs left in the chain. Copy the
 1317          * data into an mbuf cluster. Note that we don't
 1318          * bother clearing the values in the other fragment
 1319          * pointers/counters; it wouldn't gain us anything,
 1320          * and would waste cycles.
 1321          */
 1322         if (m != NULL) {
 1323                 struct mbuf             *m_new = NULL;
MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 1326                 if (m_new == NULL)
 1327                         return(1);
 1328                 if (m_head->m_pkthdr.len > MHLEN) {
MCLGET(m_new, M_DONTWAIT);
 1330                         if (!(m_new->m_flags & M_EXT)) {
m_freem(m_new);
 1332                                 return(1);
 1333                         }
 1334                 }
m_copydata(m_head, 0, m_head->m_pkthdr.len,     
mtod(m_new, caddr_t));
m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
m_freem(m_head);
m_head = m_new;
f = &c->wb_ptr->wb_frag[0];
f->wb_status = 0;
f->wb_data = VTOPHYS(mtod(m_new, caddr_t));
f->wb_ctl = total_len = m_new->m_len;
f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG;
frag = 1;
 1346         }
 1348         if (total_len < WB_MIN_FRAMELEN) {
f = &c->wb_ptr->wb_frag[frag];
f->wb_ctl = WB_MIN_FRAMELEN - total_len;
f->wb_data = VTOPHYS(&sc->wb_cdata.wb_pad);
f->wb_ctl |= WB_TXCTL_TLINK;
f->wb_status = WB_TXSTAT_OWN;
frag++;
 1355         }
c->wb_mbuf = m_head;
c->wb_lastdesc = frag - 1;
WB_TXCTL(c) |= WB_TXCTL_LASTFRAG;
WB_TXNEXT(c) = VTOPHYS(&c->wb_nextdesc->wb_ptr->wb_frag[0]);
 1362         return(0);
 1363 }
 1365 /*
 1366  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
 1367  * to the mbuf data regions directly in the transmit lists. We also save a
 1368  * copy of the pointers since the transmit list fragment pointers are
 1369  * physical addresses.
 1370  */
 1372 void wb_start(ifp)
 1373         struct ifnet            *ifp;
 1374 {
 1375         struct wb_softc         *sc;
 1376         struct mbuf             *m_head = NULL;
 1377         struct wb_chain         *cur_tx = NULL, *start_tx;
sc = ifp->if_softc;
 1381         /*
 1382          * Check for an available queue slot. If there are none,
 1383          * punt.
 1384          */
 1385         if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) {
ifp->if_flags |= IFF_OACTIVE;
 1387                 return;
 1388         }
start_tx = sc->wb_cdata.wb_tx_free;
 1392         while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) {
IFQ_DEQUEUE(&ifp->if_snd, m_head);
 1394                 if (m_head == NULL)
 1395                         break;
 1397                 /* Pick a descriptor off the free list. */
cur_tx = sc->wb_cdata.wb_tx_free;
sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc;
 1401                 /* Pack the data into the descriptor. */
wb_encap(sc, cur_tx, m_head);
 1404                 if (cur_tx != start_tx)
WB_TXOWN(cur_tx) = WB_TXSTAT_OWN;
 1407 #if NBPFILTER > 0
 1408                 /*
 1409                  * If there's a BPF listener, bounce a copy of this frame
 1410                  * to him.
 1411                  */
 1412                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, cur_tx->wb_mbuf,
BPF_DIRECTION_OUT);
 1415 #endif
 1416         }
 1418         /*
 1419          * If there are no packets queued, bail.
 1420          */
 1421         if (cur_tx == NULL)
 1422                 return;
 1424         /*
 1425          * Place the request for the upload interrupt
 1426          * in the last descriptor in the chain. This way, if
 1427          * we're chaining several packets at once, we'll only
 1428          * get an interrupt once for the whole chain rather than
 1429          * once for each packet.
 1430          */
WB_TXCTL(cur_tx) |= WB_TXCTL_FINT;
cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT;
sc->wb_cdata.wb_tx_tail = cur_tx;
 1435         if (sc->wb_cdata.wb_tx_head == NULL) {
sc->wb_cdata.wb_tx_head = start_tx;
WB_TXOWN(start_tx) = WB_TXSTAT_OWN;
CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
 1439         } else {
 1440                 /*
 1441                  * We need to distinguish between the case where
 1442                  * the own bit is clear because the chip cleared it
 1443                  * and where the own bit is clear because we haven't
 1444                  * set it yet. The magic value WB_UNSET is just some
 1445                  * ramdomly chosen number which doesn't have the own
 1446                  * bit set. When we actually transmit the frame, the
 1447                  * status word will have _only_ the own bit set, so
 1448                  * the txeoc handler will be able to tell if it needs
 1449                  * to initiate another transmission to flush out pending
 1450                  * frames.
 1451                  */
WB_TXOWN(start_tx) = WB_UNSENT;
 1453         }
 1455         /*
 1456          * Set a timeout in case the chip goes out to lunch.
 1457          */
ifp->if_timer = 5;
 1460         return;
 1461 }
 1463 void wb_init(xsc)
 1464         void                    *xsc;
 1465 {
 1466         struct wb_softc *sc = xsc;
 1467         struct ifnet *ifp = &sc->arpcom.ac_if;
 1468         int s, i;
s = splnet();
 1472         /*
 1473          * Cancel pending I/O and free all RX/TX buffers.
 1474          */
wb_stop(sc);
wb_reset(sc);
sc->wb_txthresh = WB_TXTHRESH_INIT;
 1480         /*
 1481          * Set cache alignment and burst length.
 1482          */
 1483 #ifdef foo
CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG);
WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
 1487 #endif
CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION);
WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG);
 1491         switch(sc->wb_cachesize) {
 1492         case 32:
WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG);
 1494                 break;
 1495         case 16:
WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG);
 1497                 break;
 1498         case 8:
WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG);
 1500                 break;
 1501         case 0:
 1502         default:
WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE);
 1504                 break;
 1505         }
 1507         /* This doesn't tend to work too well at 100Mbps. */
WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON);
 1510         /* Init our MAC address */
 1511         for (i = 0; i < ETHER_ADDR_LEN; i++) {
CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]);
 1513         }
 1515         /* Init circular RX list. */
 1516         if (wb_list_rx_init(sc) == ENOBUFS) {
printf("%s: initialization failed: no "
 1518                         "memory for rx buffers\n", sc->sc_dev.dv_xname);
wb_stop(sc);
splx(s);
 1521                 return;
 1522         }
 1524         /* Init TX descriptors. */
wb_list_tx_init(sc);
 1527         /* If we want promiscuous mode, set the allframes bit. */
 1528         if (ifp->if_flags & IFF_PROMISC) {
WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
 1530         } else {
WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
 1532         }
 1534         /*
 1535          * Set capture broadcast bit to capture broadcast frames.
 1536          */
 1537         if (ifp->if_flags & IFF_BROADCAST) {
WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
 1539         } else {
WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
 1541         }
 1543         /*
 1544          * Program the multicast filter, if necessary.
 1545          */
wb_setmulti(sc);
 1548         /*
 1549          * Load the address of the RX list.
 1550          */
WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
CSR_WRITE_4(sc, WB_RXADDR, VTOPHYS(&sc->wb_ldata->wb_rx_list[0]));
 1554         /*
 1555          * Enable interrupts.
 1556          */
CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF);
 1560         /* Enable receiver and transmitter. */
WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
CSR_WRITE_4(sc, WB_TXADDR, VTOPHYS(&sc->wb_ldata->wb_tx_list[0]));
WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
splx(s);
timeout_set(&sc->wb_tick_tmo, wb_tick, sc);
timeout_add(&sc->wb_tick_tmo, hz);
 1576         return;
 1577 }
 1579 /*
 1580  * Set media options.
 1581  */
 1582 int
wb_ifmedia_upd(ifp)
 1584         struct ifnet *ifp;
 1585 {
 1586         struct wb_softc *sc = ifp->if_softc;
 1588         if (ifp->if_flags & IFF_UP)
wb_init(sc);
 1591         return(0);
 1592 }
 1594 /*
 1595  * Report current media status.
 1596  */
 1597 void
wb_ifmedia_sts(ifp, ifmr)
 1599         struct ifnet            *ifp;
 1600         struct ifmediareq       *ifmr;
 1601 {
 1602         struct wb_softc *sc = ifp->if_softc;
 1603         struct mii_data *mii = &sc->sc_mii;
mii_pollstat(mii);
ifmr->ifm_active = mii->mii_media_active;
ifmr->ifm_status = mii->mii_media_status;
 1608 }
 1610 int wb_ioctl(ifp, command, data)
 1611         struct ifnet            *ifp;
u_long                  command;
caddr_t                 data;
 1614 {
 1615         struct wb_softc         *sc = ifp->if_softc;
 1616         struct ifreq            *ifr = (struct ifreq *) data;
 1617         struct ifaddr           *ifa = (struct ifaddr *)data;
 1618         int                     s, error = 0;
s = splnet();
 1622         if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) {
splx(s);
 1624                 return (error);
 1625         }
 1627         switch(command) {
 1628         case SIOCSIFADDR:
ifp->if_flags |= IFF_UP;
 1630                 switch (ifa->ifa_addr->sa_family) {
 1631 #ifdef INET
 1632                 case AF_INET:
wb_init(sc);
arp_ifinit(&sc->arpcom, ifa);
 1635                         break;
 1636 #endif /* INET */
 1637                 default:
wb_init(sc);
 1639                 }
 1640                 break;
 1641         case SIOCSIFFLAGS:
 1642                 if (ifp->if_flags & IFF_UP) {
wb_init(sc);
 1644                 } else {
 1645                         if (ifp->if_flags & IFF_RUNNING)
wb_stop(sc);
 1647                 }
error = 0;
 1649                 break;
 1650         case SIOCADDMULTI:
 1651         case SIOCDELMULTI:
error = (command == SIOCADDMULTI) ?
ether_addmulti(ifr, &sc->arpcom) :
ether_delmulti(ifr, &sc->arpcom);
 1656                 if (error == ENETRESET) {
 1657                         /*
 1658                          * Multicast list has changed; set the hardware
 1659                          * filter accordingly.
 1660                          */
 1661                         if (ifp->if_flags & IFF_RUNNING)
wb_setmulti(sc);
error = 0;
 1664                 }
 1665                 break;
 1666         case SIOCGIFMEDIA:
 1667         case SIOCSIFMEDIA:
error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command);
 1669                 break;
 1670         default:
error = ENOTTY;
 1672                 break;
 1673         }
splx(s);
 1677         return(error);
 1678 }
 1680 void wb_watchdog(ifp)
 1681         struct ifnet            *ifp;
 1682 {
 1683         struct wb_softc         *sc;
sc = ifp->if_softc;
ifp->if_oerrors++;
printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname);
 1690 #ifdef foo
 1691         if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
printf("%s: no carrier - transceiver cable problem?\n",
sc->sc_dev.dv_xname);
 1694 #endif
wb_stop(sc);
wb_reset(sc);
wb_init(sc);
 1699         if (!IFQ_IS_EMPTY(&ifp->if_snd))
wb_start(ifp);
 1702         return;
 1703 }
 1705 /*
 1706  * Stop the adapter and free any mbufs allocated to the
 1707  * RX and TX lists.
 1708  */
 1709 void wb_stop(sc)
 1710         struct wb_softc         *sc;
 1711 {
 1712         int                     i;
 1713         struct ifnet            *ifp;
ifp = &sc->arpcom.ac_if;
ifp->if_timer = 0;
timeout_del(&sc->wb_tick_tmo);
ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON));
CSR_WRITE_4(sc, WB_IMR, 0x00000000);
CSR_WRITE_4(sc, WB_TXADDR, 0x00000000);
CSR_WRITE_4(sc, WB_RXADDR, 0x00000000);
 1727         /*
 1728          * Free data in the RX lists.
 1729          */
 1730         for (i = 0; i < WB_RX_LIST_CNT; i++) {
 1731                 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) {
m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf);
sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL;
 1734                 }
 1735         }
bzero((char *)&sc->wb_ldata->wb_rx_list,
 1737                 sizeof(sc->wb_ldata->wb_rx_list));
 1739         /*
 1740          * Free the TX list buffers.
 1741          */
 1742         for (i = 0; i < WB_TX_LIST_CNT; i++) {
 1743                 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) {
m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf);
sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL;
 1746                 }
 1747         }
bzero((char *)&sc->wb_ldata->wb_tx_list,
 1750                 sizeof(sc->wb_ldata->wb_tx_list));
 1751 }
 1753 /*
 1754  * Stop all chip I/O so that the kernel's probe routines don't
 1755  * get confused by errant DMAs when rebooting.
 1756  */
 1757 void wb_shutdown(arg)
 1758         void                    *arg;
 1759 {
 1760         struct wb_softc         *sc = (struct wb_softc *)arg;
wb_stop(sc);
 1764         return;
 1765 }
 1767 struct cfattach wb_ca = {
 1768         sizeof(struct wb_softc), wb_probe, wb_attach
 1769 };
 1771 struct cfdriver wb_cd = {
 1772         0, "wb", DV_IFNET
 1773 };