root/dev/ic/xl.c

DEFINITIONS

1. xl_power
2. xl_wait
3. xl_mii_sync
4. xl_mii_send
5. xl_mii_readreg
6. xl_mii_writereg
7. xl_miibus_readreg
8. xl_miibus_writereg
9. xl_miibus_statchg
10. xl_eeprom_wait
11. xl_read_eeprom
12. xl_setmulti
13. xl_setmulti_hash
14. xl_setpromisc
15. xl_testpacket
16. xl_setcfg
17. xl_setmode
18. xl_reset
19. xl_mediacheck
20. xl_choose_xcvr
21. xl_list_tx_init
22. xl_list_tx_init_90xB
23. xl_list_rx_init
24. xl_newbuf
25. xl_rx_resync
26. xl_rxeof
27. xl_txeof
28. xl_txeof_90xB
29. xl_txeoc
30. xl_intr
31. xl_stats_update
32. xl_encap
33. xl_start
34. xl_start_90xB
35. xl_init
36. xl_ifmedia_upd
37. xl_ifmedia_sts
38. xl_ioctl
39. xl_watchdog
40. xl_freetxrx
41. xl_stop
42. xl_attach
43. xl_shutdown

    1 /*      $OpenBSD: xl.c,v 1.78 2007/05/19 16:51:57 kettenis Exp $        */
    3 /*
    4  * Copyright (c) 1997, 1998, 1999
    5  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. All advertising materials mentioning features or use of this software
   16  *    must display the following acknowledgement:
   17  *      This product includes software developed by Bill Paul.
   18  * 4. Neither the name of the author nor the names of any co-contributors
   19  *    may be used to endorse or promote products derived from this software
   20  *    without specific prior written permission.
   21  *
   22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   32  * THE POSSIBILITY OF SUCH DAMAGE.
   33  *
   34  * $FreeBSD: if_xl.c,v 1.77 2000/08/28 20:40:03 wpaul Exp $
   35  */
   37 /*
   38  * 3Com 3c90x Etherlink XL PCI NIC driver
   39  *
   40  * Supports the 3Com "boomerang", "cyclone", and "hurricane" PCI
   41  * bus-master chips (3c90x cards and embedded controllers) including
   42  * the following:
   43  *
   44  * 3Com 3c900-TPO       10Mbps/RJ-45
   45  * 3Com 3c900-COMBO     10Mbps/RJ-45,AUI,BNC
   46  * 3Com 3c905-TX        10/100Mbps/RJ-45
   47  * 3Com 3c905-T4        10/100Mbps/RJ-45
   48  * 3Com 3c900B-TPO      10Mbps/RJ-45
   49  * 3Com 3c900B-COMBO    10Mbps/RJ-45,AUI,BNC
   50  * 3Com 3c900B-TPC      10Mbps/RJ-45,BNC
   51  * 3Com 3c900B-FL       10Mbps/Fiber-optic
   52  * 3Com 3c905B-COMBO    10/100Mbps/RJ-45,AUI,BNC
   53  * 3Com 3c905B-TX       10/100Mbps/RJ-45
   54  * 3Com 3c905B-FL/FX    10/100Mbps/Fiber-optic
   55  * 3Com 3c905C-TX       10/100Mbps/RJ-45 (Tornado ASIC)
   56  * 3Com 3c980-TX        10/100Mbps server adapter (Hurricane ASIC)
   57  * 3Com 3c980C-TX       10/100Mbps server adapter (Tornado ASIC)
   58  * 3Com 3cSOHO100-TX    10/100Mbps/RJ-45 (Hurricane ASIC)
   59  * 3Com 3c450-TX        10/100Mbps/RJ-45 (Tornado ASIC)
   60  * 3Com 3c555           10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane)
   61  * 3Com 3c556           10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
   62  * 3Com 3c556B          10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
   63  * 3Com 3c575TX         10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
   64  * 3Com 3c575B          10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
   65  * 3Com 3c575C          10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
   66  * 3Com 3cxfem656       10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
   67  * 3Com 3cxfem656b      10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
   68  * 3Com 3cxfem656c      10/100Mbps/RJ-45 (Cardbus, Tornado ASIC)
   69  * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
   70  * Dell on-board 3c920 10/100Mbps/RJ-45
   71  * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
   72  * Dell Latitude laptop docking station embedded 3c905-TX
   73  *
   74  * Written by Bill Paul <wpaul@ctr.columbia.edu>
   75  * Electrical Engineering Department
   76  * Columbia University, New York City
   77  */
   79 /*
   80  * The 3c90x series chips use a bus-master DMA interface for transfering
   81  * packets to and from the controller chip. Some of the "vortex" cards
   82  * (3c59x) also supported a bus master mode, however for those chips
   83  * you could only DMA packets to/from a contiguous memory buffer. For
   84  * transmission this would mean copying the contents of the queued mbuf
   85  * chain into an mbuf cluster and then DMAing the cluster. This extra
   86  * copy would sort of defeat the purpose of the bus master support for
   87  * any packet that doesn't fit into a single mbuf.
   88  *
   89  * By contrast, the 3c90x cards support a fragment-based bus master
   90  * mode where mbuf chains can be encapsulated using TX descriptors.
   91  * This is similar to other PCI chips such as the Texas Instruments
   92  * ThunderLAN and the Intel 82557/82558.
   93  *
   94  * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
   95  * bus master chips because they maintain the old PIO interface for
   96  * backwards compatibility, but starting with the 3c905B and the
   97  * "cyclone" chips, the compatibility interface has been dropped.
   98  * Since using bus master DMA is a big win, we use this driver to
   99  * support the PCI "boomerang" chips even though they work with the
  100  * "vortex" driver in order to obtain better performance.
  101  */
  103 #include "bpfilter.h"
  105 #include <sys/param.h>
  106 #include <sys/systm.h>
  107 #include <sys/mbuf.h>
  108 #include <sys/protosw.h>
  109 #include <sys/socket.h>
  110 #include <sys/ioctl.h>
  111 #include <sys/errno.h>
  112 #include <sys/malloc.h>
  113 #include <sys/kernel.h>
  114 #include <sys/proc.h>   /* only for declaration of wakeup() used by vm.h */
  115 #include <sys/device.h>
  117 #include <net/if.h>
  118 #include <net/if_dl.h>
  119 #include <net/if_types.h>
  120 #include <net/if_media.h>
  122 #ifdef INET
  123 #include <netinet/in.h>
  124 #include <netinet/in_systm.h>
  125 #include <netinet/in_var.h>
  126 #include <netinet/ip.h>
  127 #include <netinet/if_ether.h>
  128 #endif
  130 #include <dev/mii/mii.h>
  131 #include <dev/mii/miivar.h>
  133 #include <machine/bus.h>
  135 #if NBPFILTER > 0
  136 #include <net/bpf.h>
  137 #endif
  139 #include <dev/ic/xlreg.h>
  141 /* 
  142  * TX Checksumming is disabled by default for two reasons:
  143  * - TX Checksumming will occasionally produce corrupt packets
  144  * - TX Checksumming seems to reduce performance
  145  *
  146  * Only 905B/C cards were reported to have this problem, it is possible
  147  * that later chips _may_ be immune.
  148  */
  149 #define XL905B_TXCSUM_BROKEN    1
  151 int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *);
  152 void xl_stats_update(void *);
  153 int xl_encap(struct xl_softc *, struct xl_chain *,
  154     struct mbuf * );
  155 void xl_rxeof(struct xl_softc *);
  156 int xl_rx_resync(struct xl_softc *);
  157 void xl_txeof(struct xl_softc *);
  158 void xl_txeof_90xB(struct xl_softc *);
  159 void xl_txeoc(struct xl_softc *);
  160 int xl_intr(void *);
  161 void xl_start(struct ifnet *);
  162 void xl_start_90xB(struct ifnet *);
  163 int xl_ioctl(struct ifnet *, u_long, caddr_t);
  164 void xl_init(void *);
  165 void xl_stop(struct xl_softc *);
  166 void xl_freetxrx(struct xl_softc *);
  167 void xl_watchdog(struct ifnet *);
  168 void xl_shutdown(void *);
  169 int xl_ifmedia_upd(struct ifnet *);
  170 void xl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
  172 int xl_eeprom_wait(struct xl_softc *);
  173 int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int);
  174 void xl_mii_sync(struct xl_softc *);
  175 void xl_mii_send(struct xl_softc *, u_int32_t, int);
  176 int xl_mii_readreg(struct xl_softc *, struct xl_mii_frame *);
  177 int xl_mii_writereg(struct xl_softc *, struct xl_mii_frame *);
  179 void xl_setcfg(struct xl_softc *);
  180 void xl_setmode(struct xl_softc *, int);
  181 void xl_setmulti(struct xl_softc *);
  182 void xl_setmulti_hash(struct xl_softc *);
  183 void xl_setpromisc(struct xl_softc *);
  184 void xl_reset(struct xl_softc *);
  185 int xl_list_rx_init(struct xl_softc *);
  186 int xl_list_tx_init(struct xl_softc *);
  187 int xl_list_tx_init_90xB(struct xl_softc *);
  188 void xl_wait(struct xl_softc *);
  189 void xl_mediacheck(struct xl_softc *);
  190 void xl_choose_xcvr(struct xl_softc *, int);
  191 #ifdef notdef
  192 void xl_testpacket(struct xl_softc *);
  193 #endif
  195 int xl_miibus_readreg(struct device *, int, int);
  196 void xl_miibus_writereg(struct device *, int, int, int);
  197 void xl_miibus_statchg(struct device *);
  199 void xl_power(int, void *);
  201 void
xl_power(int why, void *arg)
  203 {
  204         struct xl_softc *sc = arg;
  205         struct ifnet *ifp;
  206         int s;
s = splnet();
  209         if (why != PWR_RESUME)
xl_stop(sc);
  211         else {
ifp = &sc->sc_arpcom.ac_if;
  213                 if (ifp->if_flags & IFF_UP) {
xl_reset(sc);
xl_init(sc);
  216                 }
  217         }
splx(s);
  219 }
  221 /*
  222  * Murphy's law says that it's possible the chip can wedge and
  223  * the 'command in progress' bit may never clear. Hence, we wait
  224  * only a finite amount of time to avoid getting caught in an
  225  * infinite loop. Normally this delay routine would be a macro,
  226  * but it isn't called during normal operation so we can afford
  227  * to make it a function.
  228  */
  229 void
xl_wait(struct xl_softc *sc)
  231 {
  232         int     i;
  234         for (i = 0; i < XL_TIMEOUT; i++) {
  235                 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
  236                         break;
  237         }
  239         if (i == XL_TIMEOUT)
printf("%s: command never completed!\n", sc->sc_dev.dv_xname);
  241 }
  243 /*
  244  * MII access routines are provided for adapters with external
  245  * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
  246  * autoneg logic that's faked up to look like a PHY (3c905B-TX).
  247  * Note: if you don't perform the MDIO operations just right,
  248  * it's possible to end up with code that works correctly with
  249  * some chips/CPUs/processor speeds/bus speeds/etc but not
  250  * with others.
  251  */
  252 #define MII_SET(x)                                      \
CSR_WRITE_2(sc, XL_W4_PHY_MGMT,                 \
CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x))
  256 #define MII_CLR(x)                                      \
CSR_WRITE_2(sc, XL_W4_PHY_MGMT,                 \
CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x))
  260 /*
  261  * Sync the PHYs by setting data bit and strobing the clock 32 times.
  262  */
  263 void
xl_mii_sync(struct xl_softc *sc)
  265 {
  266         int     i;
XL_SEL_WIN(4);
MII_SET(XL_MII_DIR|XL_MII_DATA);
  271         for (i = 0; i < 32; i++) {
MII_SET(XL_MII_CLK);
MII_SET(XL_MII_DATA);
MII_SET(XL_MII_DATA);
MII_CLR(XL_MII_CLK);
MII_SET(XL_MII_DATA);
MII_SET(XL_MII_DATA);
  278         }
  279 }
  281 /*
  282  * Clock a series of bits through the MII.
  283  */
  284 void
xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt)
  286 {
  287         int     i;
XL_SEL_WIN(4);
MII_CLR(XL_MII_CLK);
  292         for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
  293                 if (bits & i) {
MII_SET(XL_MII_DATA);
  295                 } else {
MII_CLR(XL_MII_DATA);
  297                 }
MII_CLR(XL_MII_CLK);
MII_SET(XL_MII_CLK);
  300         }
  301 }
  303 /*
  304  * Read an PHY register through the MII.
  305  */
  306 int
xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame)
  308 {
  309         int     i, ack, s;
s = splnet();
  313         /*
  314          * Set up frame for RX.
  315          */
frame->mii_stdelim = XL_MII_STARTDELIM;
frame->mii_opcode = XL_MII_READOP;
frame->mii_turnaround = 0;
frame->mii_data = 0;
  321         /*
  322          * Select register window 4.
  323          */
XL_SEL_WIN(4);
CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0);
  328         /*
  329          * Turn on data xmit.
  330          */
MII_SET(XL_MII_DIR);
xl_mii_sync(sc);
  335         /*
  336          * Send command/address info.
  337          */
xl_mii_send(sc, frame->mii_stdelim, 2);
xl_mii_send(sc, frame->mii_opcode, 2);
xl_mii_send(sc, frame->mii_phyaddr, 5);
xl_mii_send(sc, frame->mii_regaddr, 5);
  343         /* Idle bit */
MII_CLR((XL_MII_CLK|XL_MII_DATA));
MII_SET(XL_MII_CLK);
  347         /* Turn off xmit. */
MII_CLR(XL_MII_DIR);
  350         /* Check for ack */
MII_CLR(XL_MII_CLK);
ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;
MII_SET(XL_MII_CLK);
  355         /*
  356          * Now try reading data bits. If the ack failed, we still
  357          * need to clock through 16 cycles to keep the PHY(s) in sync.
  358          */
  359         if (ack) {
  360                 for(i = 0; i < 16; i++) {
MII_CLR(XL_MII_CLK);
MII_SET(XL_MII_CLK);
  363                 }
  364                 goto fail;
  365         }
  367         for (i = 0x8000; i; i >>= 1) {
MII_CLR(XL_MII_CLK);
  369                 if (!ack) {
  370                         if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA)
frame->mii_data |= i;
  372                 }
MII_SET(XL_MII_CLK);
  374         }
fail:
MII_CLR(XL_MII_CLK);
MII_SET(XL_MII_CLK);
splx(s);
  383         if (ack)
  384                 return (1);
  385         return (0);
  386 }
  388 /*
  389  * Write to a PHY register through the MII.
  390  */
  391 int
xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame)
  393 {
  394         int     s;
s = splnet();
  398         /*
  399          * Set up frame for TX.
  400          */
frame->mii_stdelim = XL_MII_STARTDELIM;
frame->mii_opcode = XL_MII_WRITEOP;
frame->mii_turnaround = XL_MII_TURNAROUND;
  406         /*
  407          * Select the window 4.
  408          */
XL_SEL_WIN(4);
  411         /*
  412          * Turn on data output.
  413          */
MII_SET(XL_MII_DIR);
xl_mii_sync(sc);
xl_mii_send(sc, frame->mii_stdelim, 2);
xl_mii_send(sc, frame->mii_opcode, 2);
xl_mii_send(sc, frame->mii_phyaddr, 5);
xl_mii_send(sc, frame->mii_regaddr, 5);
xl_mii_send(sc, frame->mii_turnaround, 2);
xl_mii_send(sc, frame->mii_data, 16);
  425         /* Idle bit. */
MII_SET(XL_MII_CLK);
MII_CLR(XL_MII_CLK);
  429         /*
  430          * Turn off xmit.
  431          */
MII_CLR(XL_MII_DIR);
splx(s);
  436         return (0);
  437 }
  439 int
xl_miibus_readreg(struct device *self, int phy, int reg)
  441 {
  442         struct xl_softc *sc = (struct xl_softc *)self;
  443         struct xl_mii_frame     frame;
  445         if (!(sc->xl_flags & XL_FLAG_PHYOK) && phy != 24)
  446                 return (0);
bzero((char *)&frame, sizeof(frame));
frame.mii_phyaddr = phy;
frame.mii_regaddr = reg;
xl_mii_readreg(sc, &frame);
  454         return (frame.mii_data);
  455 }
  457 void
xl_miibus_writereg(struct device *self, int phy, int reg, int data)
  459 {
  460         struct xl_softc *sc = (struct xl_softc *)self;
  461         struct xl_mii_frame     frame;
  463         if (!(sc->xl_flags & XL_FLAG_PHYOK) && phy != 24)
  464                 return;
bzero((char *)&frame, sizeof(frame));
frame.mii_phyaddr = phy;
frame.mii_regaddr = reg;
frame.mii_data = data;
xl_mii_writereg(sc, &frame);
  473 }
  475 void
xl_miibus_statchg(struct device *self)
  477 {
  478         struct xl_softc *sc = (struct xl_softc *)self;
xl_setcfg(sc);
  482         /* Set ASIC's duplex mode to match the PHY. */
XL_SEL_WIN(3);
  484         if ((sc->sc_mii.mii_media_active & IFM_GMASK) == IFM_FDX)
CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
  486         else
CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
  488                     (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
  489 }
  491 /*
  492  * The EEPROM is slow: give it time to come ready after issuing
  493  * it a command.
  494  */
  495 int
xl_eeprom_wait(struct xl_softc *sc)
  497 {
  498         int     i;
  500         for (i = 0; i < 100; i++) {
  501                 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
DELAY(162);
  503                 else
  504                         break;
  505         }
  507         if (i == 100) {
printf("%s: eeprom failed to come ready\n", sc->sc_dev.dv_xname);
  509                 return (1);
  510         }
  512         return (0);
  513 }
  515 /*
  516  * Read a sequence of words from the EEPROM. Note that ethernet address
  517  * data is stored in the EEPROM in network byte order.
  518  */
  519 int
xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap)
  521 {
  522         int             err = 0, i;
u_int16_t       word = 0, *ptr;
  524 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
  525 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
  526         /* WARNING! DANGER!
  527          * It's easy to accidentally overwrite the rom content!
  528          * Note: the 3c575 uses 8bit EEPROM offsets.
  529          */
XL_SEL_WIN(0);
  532         if (xl_eeprom_wait(sc))
  533                 return (1);
  535         if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
off += 0x30;
  538         for (i = 0; i < cnt; i++) {
  539                 if (sc->xl_flags & XL_FLAG_8BITROM)
CSR_WRITE_2(sc, XL_W0_EE_CMD,
XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
  542                 else
CSR_WRITE_2(sc, XL_W0_EE_CMD,
XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
err = xl_eeprom_wait(sc);
  546                 if (err)
  547                         break;
word = CSR_READ_2(sc, XL_W0_EE_DATA);
ptr = (u_int16_t *)(dest + (i * 2));
  550                 if (swap)
  551                         *ptr = ntohs(word);
  552                 else
  553                         *ptr = word;    
  554         }
  556         return (err ? 1 : 0);
  557 }
  559 /*
  560  * NICs older than the 3c905B have only one multicast option, which
  561  * is to enable reception of all multicast frames.
  562  */
  563 void
xl_setmulti(struct xl_softc *sc)
  565 {
  566         struct ifnet    *ifp;
  567         struct arpcom   *ac = &sc->sc_arpcom;
u_int8_t        rxfilt;
ifp = &sc->sc_arpcom.ac_if;
XL_SEL_WIN(5);
rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
  575         if (ifp->if_flags & IFF_ALLMULTI) {
rxfilt |= XL_RXFILTER_ALLMULTI;
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
  578                 return;
  579         }
  581         if (ac->ac_multicnt > 0)
rxfilt |= XL_RXFILTER_ALLMULTI;
  583         else
rxfilt &= ~XL_RXFILTER_ALLMULTI;
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
  587 }
  589 /*
  590  * 3c905B adapters have a hash filter that we can program.
  591  */
  592 void
xl_setmulti_hash(struct xl_softc *sc)
  594 {
  595         struct ifnet    *ifp;
  596         int             h = 0, i;
  597         struct arpcom   *ac = &sc->sc_arpcom;
  598         struct ether_multi *enm;
  599         struct ether_multistep step;
u_int8_t        rxfilt;
  601         int             mcnt = 0;
ifp = &sc->sc_arpcom.ac_if;
XL_SEL_WIN(5);
rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
  608         if (ifp->if_flags & IFF_ALLMULTI) {
allmulti:
rxfilt |= XL_RXFILTER_ALLMULTI;
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
  612                 return;
  613         } else
rxfilt &= ~XL_RXFILTER_ALLMULTI;
  617         /* first, zot all the existing hash bits */
  618         for (i = 0; i < XL_HASHFILT_SIZE; i++)
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i);
  621         /* now program new ones */
ETHER_FIRST_MULTI(step, ac, enm);
  623         while (enm != NULL) {
  624                 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
ifp->if_flags |= IFF_ALLMULTI;
  626                         goto allmulti;
  627                 }
h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) &
  629                     0x000000FF;
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h);
mcnt++;
ETHER_NEXT_MULTI(step, enm);
  633         }
  635         if (mcnt)
rxfilt |= XL_RXFILTER_MULTIHASH;
  637         else
rxfilt &= ~XL_RXFILTER_MULTIHASH;
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
  641 }
  643 void
xl_setpromisc(struct xl_softc *sc)
  645 {
  646         struct ifnet *ifp;
u_int8_t rxfilt;
ifp = &sc->sc_arpcom.ac_if;
XL_SEL_WIN(5);
rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
  654         if (ifp->if_flags & IFF_PROMISC)
rxfilt |= XL_RXFILTER_ALLFRAMES;
  656         else
rxfilt &= ~XL_RXFILTER_ALLFRAMES;
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
  660 }
  663 #ifdef notdef
  664 void
xl_testpacket(struct xl_softc *sc)
  666 {
  667         struct mbuf     *m;
  668         struct ifnet    *ifp;
  669         int             error;
ifp = &sc->sc_arpcom.ac_if;
MGETHDR(m, M_DONTWAIT, MT_DATA);
  675         if (m == NULL)
  676                 return;
bcopy(&sc->sc_arpcom.ac_enaddr,
mtod(m, struct ether_header *)->ether_dhost, ETHER_ADDR_LEN);
bcopy(&sc->sc_arpcom.ac_enaddr,
mtod(m, struct ether_header *)->ether_shost, ETHER_ADDR_LEN);
mtod(m, struct ether_header *)->ether_type = htons(3);
mtod(m, unsigned char *)[14] = 0;
mtod(m, unsigned char *)[15] = 0;
mtod(m, unsigned char *)[16] = 0xE3;
m->m_len = m->m_pkthdr.len = sizeof(struct ether_header) + 3;
IFQ_ENQUEUE(&ifp->if_snd, m, NULL, error);
xl_start(ifp);
  689 }
  690 #endif
  692 void
xl_setcfg(struct xl_softc *sc)
  694 {
u_int32_t icfg;
XL_SEL_WIN(3);
icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
icfg &= ~XL_ICFG_CONNECTOR_MASK;
  700         if (sc->xl_media & XL_MEDIAOPT_MII ||
sc->xl_media & XL_MEDIAOPT_BT4)
icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
  703         if (sc->xl_media & XL_MEDIAOPT_BTX)
icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
  708 }
  710 void
xl_setmode(struct xl_softc *sc, int media)
  712 {
  713         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
u_int32_t icfg;
u_int16_t mediastat;
XL_SEL_WIN(4);
mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
XL_SEL_WIN(3);
icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
  722         if (sc->xl_media & XL_MEDIAOPT_BT) {
  723                 if (IFM_SUBTYPE(media) == IFM_10_T) {
ifp->if_baudrate = IF_Mbps(10);
sc->xl_xcvr = XL_XCVR_10BT;
icfg &= ~XL_ICFG_CONNECTOR_MASK;
icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
mediastat |= XL_MEDIASTAT_LINKBEAT|
XL_MEDIASTAT_JABGUARD;
mediastat &= ~XL_MEDIASTAT_SQEENB;
  731                 }
  732         }
  734         if (sc->xl_media & XL_MEDIAOPT_BFX) {
  735                 if (IFM_SUBTYPE(media) == IFM_100_FX) {
ifp->if_baudrate = IF_Mbps(100);
sc->xl_xcvr = XL_XCVR_100BFX;
icfg &= ~XL_ICFG_CONNECTOR_MASK;
icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
mediastat |= XL_MEDIASTAT_LINKBEAT;
mediastat &= ~XL_MEDIASTAT_SQEENB;
  742                 }
  743         }
  745         if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
  746                 if (IFM_SUBTYPE(media) == IFM_10_5) {
ifp->if_baudrate = IF_Mbps(10);
sc->xl_xcvr = XL_XCVR_AUI;
icfg &= ~XL_ICFG_CONNECTOR_MASK;
icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
XL_MEDIASTAT_JABGUARD);
mediastat |= ~XL_MEDIASTAT_SQEENB;
  754                 }
  755                 if (IFM_SUBTYPE(media) == IFM_10_FL) {
ifp->if_baudrate = IF_Mbps(10);
sc->xl_xcvr = XL_XCVR_AUI;
icfg &= ~XL_ICFG_CONNECTOR_MASK;
icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
XL_MEDIASTAT_JABGUARD);
mediastat |= ~XL_MEDIASTAT_SQEENB;
  763                 }
  764         }
  766         if (sc->xl_media & XL_MEDIAOPT_BNC) {
  767                 if (IFM_SUBTYPE(media) == IFM_10_2) {
ifp->if_baudrate = IF_Mbps(10);
sc->xl_xcvr = XL_XCVR_COAX;
icfg &= ~XL_ICFG_CONNECTOR_MASK;
icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
mediastat &= ~(XL_MEDIASTAT_LINKBEAT|
XL_MEDIASTAT_JABGUARD|
XL_MEDIASTAT_SQEENB);
  775                 }
  776         }
  778         if ((media & IFM_GMASK) == IFM_FDX ||
IFM_SUBTYPE(media) == IFM_100_FX) {
XL_SEL_WIN(3);
CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
  782         } else {
XL_SEL_WIN(3);
CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
  785                         (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
  786         }
  788         if (IFM_SUBTYPE(media) == IFM_10_2)
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
  790         else
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
XL_SEL_WIN(4);
CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
DELAY(800);
XL_SEL_WIN(7);
  797 }
  799 void
xl_reset(struct xl_softc *sc)
  801 {
  802         int     i;
XL_SEL_WIN(0);
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
  806                     ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
XL_RESETOPT_DISADVFD:0));
  809         /*
  810          * Pause briefly after issuing the reset command before trying
  811          * to access any other registers. With my 3c575C cardbus card,
  812          * failing to do this results in the system locking up while
  813          * trying to poll the command busy bit in the status register.
  814          */
DELAY(100000);
  817         for (i = 0; i < XL_TIMEOUT; i++) {
DELAY(10);
  819                 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
  820                         break;
  821         }
  823         if (i == XL_TIMEOUT)
printf("%s: reset didn't complete\n", sc->sc_dev.dv_xname);
  826         /* Note: the RX reset takes an absurd amount of time
  827          * on newer versions of the Tornado chips such as those
  828          * on the 3c905CX and newer 3c908C cards. We wait an
  829          * extra amount of time so that xl_wait() doesn't complain
  830          * and annoy the users.
  831          */
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
DELAY(100000);
xl_wait(sc);
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
xl_wait(sc);
  838         if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 
sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
XL_SEL_WIN(2);
CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc,
XL_W2_RESET_OPTIONS) 
  843                     | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0)
  844                     | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0)
  845                     );
  846         }
  848         /* Wait a little while for the chip to get its brains in order. */
DELAY(100000);
  850 }
  852 /*
  853  * This routine is a kludge to work around possible hardware faults
  854  * or manufacturing defects that can cause the media options register
  855  * (or reset options register, as it's called for the first generation
  856  * 3c90x adapters) to return an incorrect result. I have encountered
  857  * one Dell Latitude laptop docking station with an integrated 3c905-TX
  858  * which doesn't have any of the 'mediaopt' bits set. This screws up
  859  * the attach routine pretty badly because it doesn't know what media
  860  * to look for. If we find ourselves in this predicament, this routine
  861  * will try to guess the media options values and warn the user of a
  862  * possible manufacturing defect with his adapter/system/whatever.
  863  */
  864 void
xl_mediacheck(struct xl_softc *sc)
  866 {
  867         /*
  868          * If some of the media options bits are set, assume they are
  869          * correct. If not, try to figure it out down below.
  870          * XXX I should check for 10baseFL, but I don't have an adapter
  871          * to test with.
  872          */
  873         if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
  874                 /*
  875                  * Check the XCVR value. If it's not in the normal range
  876                  * of values, we need to fake it up here.
  877                  */
  878                 if (sc->xl_xcvr <= XL_XCVR_AUTO)
  879                         return;
  880                 else {
printf("%s: bogus xcvr value "
  882                         "in EEPROM (%x)\n", sc->sc_dev.dv_xname, sc->xl_xcvr);
printf("%s: choosing new default based "
  884                                 "on card type\n", sc->sc_dev.dv_xname);
  885                 }
  886         } else {
  887                 if (sc->xl_type == XL_TYPE_905B &&
sc->xl_media & XL_MEDIAOPT_10FL)
  889                         return;
printf("%s: WARNING: no media options bits set in "
  891                         "the media options register!!\n", sc->sc_dev.dv_xname);
printf("%s: this could be a manufacturing defect in "
  893                         "your adapter or system\n", sc->sc_dev.dv_xname);
printf("%s: attempting to guess media type; you "
  895                         "should probably consult your vendor\n", sc->sc_dev.dv_xname);
  896         }
xl_choose_xcvr(sc, 1);
  899 }
  901 void
xl_choose_xcvr(struct xl_softc *sc, int verbose)
  903 {
u_int16_t devid;
  906         /*
  907          * Read the device ID from the EEPROM.
  908          * This is what's loaded into the PCI device ID register, so it has
  909          * to be correct otherwise we wouldn't have gotten this far.
  910          */
xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
  913         switch(devid) {
  914         case TC_DEVICEID_BOOMERANG_10BT:        /* 3c900-TPO */
  915         case TC_DEVICEID_KRAKATOA_10BT:         /* 3c900B-TPO */
sc->xl_media = XL_MEDIAOPT_BT;
sc->xl_xcvr = XL_XCVR_10BT;
  918                 if (verbose)
printf("%s: guessing 10BaseT transceiver\n",
sc->sc_dev.dv_xname);
  921                 break;
  922         case TC_DEVICEID_BOOMERANG_10BT_COMBO:  /* 3c900-COMBO */
  923         case TC_DEVICEID_KRAKATOA_10BT_COMBO:   /* 3c900B-COMBO */
sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
sc->xl_xcvr = XL_XCVR_10BT;
  926                 if (verbose)
printf("%s: guessing COMBO (AUI/BNC/TP)\n",
sc->sc_dev.dv_xname);
  929                 break;
  930         case TC_DEVICEID_KRAKATOA_10BT_TPC:     /* 3c900B-TPC */
sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
sc->xl_xcvr = XL_XCVR_10BT;
  933                 if (verbose)
printf("%s: guessing TPC (BNC/TP)\n", sc->sc_dev.dv_xname);
  935                 break;
  936         case TC_DEVICEID_CYCLONE_10FL:          /* 3c900B-FL */
sc->xl_media = XL_MEDIAOPT_10FL;
sc->xl_xcvr = XL_XCVR_AUI;
  939                 if (verbose)
printf("%s: guessing 10baseFL\n", sc->sc_dev.dv_xname);
  941                 break;
  942         case TC_DEVICEID_BOOMERANG_10_100BT:    /* 3c905-TX */
  943         case TC_DEVICEID_HURRICANE_555:         /* 3c555 */
  944         case TC_DEVICEID_HURRICANE_556:         /* 3c556 */
  945         case TC_DEVICEID_HURRICANE_556B:        /* 3c556B */
  946         case TC_DEVICEID_HURRICANE_575A:        /* 3c575TX */
  947         case TC_DEVICEID_HURRICANE_575B:        /* 3c575B */
  948         case TC_DEVICEID_HURRICANE_575C:        /* 3c575C */
  949         case TC_DEVICEID_HURRICANE_656:         /* 3c656 */
  950         case TC_DEVICEID_HURRICANE_656B:        /* 3c656B */
  951         case TC_DEVICEID_TORNADO_656C:          /* 3c656C */
  952         case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */
sc->xl_media = XL_MEDIAOPT_MII;
sc->xl_xcvr = XL_XCVR_MII;
  955                 if (verbose)
printf("%s: guessing MII\n", sc->sc_dev.dv_xname);
  957                 break;
  958         case TC_DEVICEID_BOOMERANG_100BT4:      /* 3c905-T4 */
  959         case TC_DEVICEID_CYCLONE_10_100BT4:     /* 3c905B-T4 */
sc->xl_media = XL_MEDIAOPT_BT4;
sc->xl_xcvr = XL_XCVR_MII;
  962                 if (verbose)
printf("%s: guessing 100BaseT4/MII\n", sc->sc_dev.dv_xname);
  964                 break;
  965         case TC_DEVICEID_HURRICANE_10_100BT:    /* 3c905B-TX */
  966         case TC_DEVICEID_HURRICANE_10_100BT_SERV:/* 3c980-TX */
  967         case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */
  968         case TC_DEVICEID_HURRICANE_SOHO100TX:   /* 3cSOHO100-TX */
  969         case TC_DEVICEID_TORNADO_10_100BT:      /* 3c905C-TX */
  970         case TC_DEVICEID_TORNADO_HOMECONNECT:   /* 3c450-TX */
sc->xl_media = XL_MEDIAOPT_BTX;
sc->xl_xcvr = XL_XCVR_AUTO;
  973                 if (verbose)
printf("%s: guessing 10/100 internal\n",
sc->sc_dev.dv_xname);
  976                 break;
  977         case TC_DEVICEID_CYCLONE_10_100_COMBO:  /* 3c905B-COMBO */
sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
sc->xl_xcvr = XL_XCVR_AUTO;
  980                 if (verbose)
printf("%s: guessing 10/100 plus BNC/AUI\n",
sc->sc_dev.dv_xname);
  983                 break;
  984         default:
printf("%s: unknown device ID: %x -- "
  986                         "defaulting to 10baseT\n", sc->sc_dev.dv_xname, devid);
sc->xl_media = XL_MEDIAOPT_BT;
  988                 break;
  989         }
  990 }
  992 /*
  993  * Initialize the transmit descriptors.
  994  */
  995 int
xl_list_tx_init(struct xl_softc *sc)
  997 {
  998         struct xl_chain_data    *cd;
  999         struct xl_list_data     *ld;
 1000         int                     i;
cd = &sc->xl_cdata;
ld = sc->xl_ldata;
 1004         for (i = 0; i < XL_TX_LIST_CNT; i++) {
cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
 1006                 if (i == (XL_TX_LIST_CNT - 1))
cd->xl_tx_chain[i].xl_next = NULL;
 1008                 else
cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
 1010         }
cd->xl_tx_free = &cd->xl_tx_chain[0];
cd->xl_tx_tail = cd->xl_tx_head = NULL;
 1015         return (0);
 1016 }
 1018 /*
 1019  * Initialize the transmit descriptors.
 1020  */
 1021 int
xl_list_tx_init_90xB(struct xl_softc *sc)
 1023 {
 1024         struct xl_chain_data    *cd;
 1025         struct xl_list_data     *ld;
 1026         int                     i, next, prev;
cd = &sc->xl_cdata;
ld = sc->xl_ldata;
 1030         for (i = 0; i < XL_TX_LIST_CNT; i++) {
 1031                 if (i == (XL_TX_LIST_CNT - 1))
next = 0;
 1033                 else
next = i + 1;
 1035                 if (i == 0)
prev = XL_TX_LIST_CNT - 1;
 1037                 else
prev = i - 1;
cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
cd->xl_tx_chain[i].xl_phys =
sc->sc_listmap->dm_segs[0].ds_addr +   
offsetof(struct xl_list_data, xl_tx_list[i]);
cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[next];
cd->xl_tx_chain[i].xl_prev = &cd->xl_tx_chain[prev];
 1045         }
bzero((char *)ld->xl_tx_list, sizeof(struct xl_list) * XL_TX_LIST_CNT);
ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY);
cd->xl_tx_prod = 1;
cd->xl_tx_cons = 1;
cd->xl_tx_cnt = 0;
 1054         return (0);
 1055 }
 1057 /*
 1058  * Initialize the RX descriptors and allocate mbufs for them. Note that
 1059  * we arrange the descriptors in a closed ring, so that the last descriptor
 1060  * points back to the first.
 1061  */
 1062 int
xl_list_rx_init(struct xl_softc *sc)
 1064 {
 1065         struct xl_chain_data    *cd;
 1066         struct xl_list_data     *ld;
 1067         int                     i, n;
bus_addr_t              next;
cd = &sc->xl_cdata;
ld = sc->xl_ldata;
 1073         for (i = 0; i < XL_RX_LIST_CNT; i++) {
cd->xl_rx_chain[i].xl_ptr =
 1075                         (struct xl_list_onefrag *)&ld->xl_rx_list[i];
 1076                 if (xl_newbuf(sc, &cd->xl_rx_chain[i]) == ENOBUFS)
 1077                         return(ENOBUFS);
 1078                 if (i == (XL_RX_LIST_CNT - 1))
n = 0;
 1080                 else
n = i + 1;
cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[n];
next = sc->sc_listmap->dm_segs[0].ds_addr +
offsetof(struct xl_list_data, xl_rx_list[n]);
ld->xl_rx_list[i].xl_next = htole32(next);
 1086         }
cd->xl_rx_head = &cd->xl_rx_chain[0];
 1090         return (0);
 1091 }
 1093 /*
 1094  * Initialize an RX descriptor and attach an MBUF cluster.
 1095  */
 1096 int
xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c)
 1098 {
 1099         struct mbuf     *m_new = NULL;
bus_dmamap_t    map;
MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 1103         if (m_new == NULL)
 1104                 return (ENOBUFS);
MCLGET(m_new, M_DONTWAIT);
 1107         if (!(m_new->m_flags & M_EXT)) {
m_freem(m_new);
 1109                 return (ENOBUFS);
 1110         }
m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 1113         if (bus_dmamap_load(sc->sc_dmat, sc->sc_rx_sparemap,
mtod(m_new, caddr_t), MCLBYTES, NULL, BUS_DMA_NOWAIT) != 0) {
m_freem(m_new);
 1116                 return (ENOBUFS);
 1117         }
 1119         /* sync the old map, and unload it (if necessary) */
 1120         if (c->map->dm_nsegs != 0) {
bus_dmamap_sync(sc->sc_dmat, c->map,
 1122                     0, c->map->dm_mapsize, BUS_DMASYNC_POSTREAD);
bus_dmamap_unload(sc->sc_dmat, c->map);
 1124         }
map = c->map;
c->map = sc->sc_rx_sparemap;
sc->sc_rx_sparemap = map;
 1130         /* Force longword alignment for packet payload. */
m_adj(m_new, ETHER_ALIGN);
bus_dmamap_sync(sc->sc_dmat, c->map, 0, c->map->dm_mapsize,
BUS_DMASYNC_PREREAD);
c->xl_mbuf = m_new;
c->xl_ptr->xl_frag.xl_addr =
htole32(c->map->dm_segs[0].ds_addr + ETHER_ALIGN);
c->xl_ptr->xl_frag.xl_len =
htole32(c->map->dm_segs[0].ds_len | XL_LAST_FRAG);
c->xl_ptr->xl_status = htole32(0);
bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
 1144             ((caddr_t)c->xl_ptr - sc->sc_listkva), sizeof(struct xl_list),
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 1147         return (0);
 1148 }
 1150 int
xl_rx_resync(struct xl_softc *sc)
 1152 {
 1153         struct xl_chain_onefrag *pos;
 1154         int i;
pos = sc->xl_cdata.xl_rx_head;
 1158         for (i = 0; i < XL_RX_LIST_CNT; i++) {
bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
 1160                     ((caddr_t)pos->xl_ptr - sc->sc_listkva),
 1161                     sizeof(struct xl_list),
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 1164                 if (pos->xl_ptr->xl_status)
 1165                         break;
pos = pos->xl_next;
 1167         }
 1169         if (i == XL_RX_LIST_CNT)
 1170                 return (0);
sc->xl_cdata.xl_rx_head = pos;
 1174         return (EAGAIN);
 1175 }
 1177 /*
 1178  * A frame has been uploaded: pass the resulting mbuf chain up to
 1179  * the higher level protocols.
 1180  */
 1181 void
xl_rxeof(struct xl_softc *sc)
 1183 {
 1184         struct mbuf             *m;
 1185         struct ifnet            *ifp;
 1186         struct xl_chain_onefrag *cur_rx;
 1187         int                     total_len = 0, sumflags = 0;
u_int32_t               rxstat;
ifp = &sc->sc_arpcom.ac_if;
again:
 1194         while ((rxstat = letoh32(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))
 1195             != 0) {
cur_rx = sc->xl_cdata.xl_rx_head;
sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
total_len = rxstat & XL_RXSTAT_LENMASK;
bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
 1201                     ((caddr_t)cur_rx->xl_ptr - sc->sc_listkva),
 1202                     sizeof(struct xl_list),
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 1205                 /*
 1206                  * Since we have told the chip to allow large frames,
 1207                  * we need to trap giant frame errors in software. We allow
 1208                  * a little more than the normal frame size to account for
 1209                  * frames with VLAN tags.
 1210                  */
 1211                 if (total_len > XL_MAX_FRAMELEN)
rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE);
 1214                 /*
 1215                  * If an error occurs, update stats, clear the
 1216                  * status word and leave the mbuf cluster in place:
 1217                  * it should simply get re-used next time this descriptor
 1218                  * comes up in the ring.
 1219                  */
 1220                 if (rxstat & XL_RXSTAT_UP_ERROR) {
ifp->if_ierrors++;
cur_rx->xl_ptr->xl_status = htole32(0);
 1223                         continue;
 1224                 }
 1226                 /*
 1227                  * If the error bit was not set, the upload complete
 1228                  * bit should be set which means we have a valid packet.
 1229                  * If not, something truly strange has happened.
 1230                  */
 1231                 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
printf("%s: bad receive status -- "
 1233                             "packet dropped\n", sc->sc_dev.dv_xname);
ifp->if_ierrors++;
cur_rx->xl_ptr->xl_status = htole32(0);
 1236                         continue;
 1237                 }
 1239                 /* No errors; receive the packet. */    
m = cur_rx->xl_mbuf;
 1242                 /*
 1243                  * Try to conjure up a new mbuf cluster. If that
 1244                  * fails, it means we have an out of memory condition and
 1245                  * should leave the buffer in place and continue. This will
 1246                  * result in a lost packet, but there's little else we
 1247                  * can do in this situation.
 1248                  */
 1249                 if (xl_newbuf(sc, cur_rx) == ENOBUFS) {
ifp->if_ierrors++;
cur_rx->xl_ptr->xl_status = htole32(0);
 1252                         continue;
 1253                 }
ifp->if_ipackets++;
m->m_pkthdr.rcvif = ifp;
m->m_pkthdr.len = m->m_len = total_len;
 1258 #if NBPFILTER > 0
 1259                 /*
 1260                  * Handle BPF listeners. Let the BPF user see the packet.
 1261                  */
 1262                 if (ifp->if_bpf) {
bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN);
 1264                 }
 1265 #endif
 1267                 if (sc->xl_type == XL_TYPE_905B) {
 1268                         if (!(rxstat & XL_RXSTAT_IPCKERR) &&
 1269                             (rxstat & XL_RXSTAT_IPCKOK))
sumflags |= M_IPV4_CSUM_IN_OK;
 1272                         if (!(rxstat & XL_RXSTAT_TCPCKERR) &&
 1273                             (rxstat & XL_RXSTAT_TCPCKOK))
sumflags |= M_TCP_CSUM_IN_OK;
 1276                         if (!(rxstat & XL_RXSTAT_UDPCKERR) &&
 1277                             (rxstat & XL_RXSTAT_UDPCKOK))
sumflags |= M_UDP_CSUM_IN_OK;
m->m_pkthdr.csum_flags = sumflags;
 1281                 }
ether_input_mbuf(ifp, m);
 1284         }
 1286         /*
 1287          * Handle the 'end of channel' condition. When the upload
 1288          * engine hits the end of the RX ring, it will stall. This
 1289          * is our cue to flush the RX ring, reload the uplist pointer
 1290          * register and unstall the engine.
 1291          * XXX This is actually a little goofy. With the ThunderLAN
 1292          * chip, you get an interrupt when the receiver hits the end
 1293          * of the receive ring, which tells you exactly when you
 1294          * you need to reload the ring pointer. Here we have to
 1295          * fake it. I'm mad at myself for not being clever enough
 1296          * to avoid the use of a goto here.
 1297          */
 1298         if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
xl_wait(sc);
CSR_WRITE_4(sc, XL_UPLIST_PTR,
sc->sc_listmap->dm_segs[0].ds_addr +
offsetof(struct xl_list_data, xl_rx_list[0]));
sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
 1307                 goto again;
 1308         }
 1309 }
 1311 /*
 1312  * A frame was downloaded to the chip. It's safe for us to clean up
 1313  * the list buffers.
 1314  */
 1315 void
xl_txeof(struct xl_softc *sc)
 1317 {
 1318         struct xl_chain         *cur_tx;
 1319         struct ifnet            *ifp;
ifp = &sc->sc_arpcom.ac_if;
 1323         /* Clear the timeout timer. */
ifp->if_timer = 0;
 1326         /*
 1327          * Go through our tx list and free mbufs for those
 1328          * frames that have been uploaded. Note: the 3c905B
 1329          * sets a special bit in the status word to let us
 1330          * know that a frame has been downloaded, but the
 1331          * original 3c900/3c905 adapters don't do that.
 1332          * Consequently, we have to use a different test if
 1333          * xl_type != XL_TYPE_905B.
 1334          */
 1335         while (sc->xl_cdata.xl_tx_head != NULL) {
cur_tx = sc->xl_cdata.xl_tx_head;
bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
 1339                     ((caddr_t)cur_tx->xl_ptr - sc->sc_listkva),
 1340                     sizeof(struct xl_list),
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 1343                 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
 1344                         break;
sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
ifp->if_opackets++;
 1348                 if (cur_tx->map->dm_nsegs != 0) {
bus_dmamap_t map = cur_tx->map;
bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->sc_dmat, map);
 1354                 }
 1355                 if (cur_tx->xl_mbuf != NULL) {
m_freem(cur_tx->xl_mbuf);
cur_tx->xl_mbuf = NULL;
 1358                 }
cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
sc->xl_cdata.xl_tx_free = cur_tx;
 1361         }
 1363         if (sc->xl_cdata.xl_tx_head == NULL) {
ifp->if_flags &= ~IFF_OACTIVE;
sc->xl_cdata.xl_tx_tail = NULL;
 1366         } else {
 1367                 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
 1368                         !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
sc->sc_listmap->dm_segs[0].ds_addr +
 1371                             ((caddr_t)sc->xl_cdata.xl_tx_head->xl_ptr -
sc->sc_listkva));
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
 1374                 }
 1375         }
 1376 }
 1378 void
xl_txeof_90xB(struct xl_softc *sc)
 1380 {
 1381         struct xl_chain *cur_tx = NULL;
 1382         struct ifnet *ifp;
 1383         int idx;
ifp = &sc->sc_arpcom.ac_if;
idx = sc->xl_cdata.xl_tx_cons;
 1388         while (idx != sc->xl_cdata.xl_tx_prod) {
cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
 1392                 if ((cur_tx->xl_ptr->xl_status &
htole32(XL_TXSTAT_DL_COMPLETE)) == 0)
 1394                         break;
 1396                 if (cur_tx->xl_mbuf != NULL) {
m_freem(cur_tx->xl_mbuf);
cur_tx->xl_mbuf = NULL;
 1399                 }
 1401                 if (cur_tx->map->dm_nsegs != 0) {
bus_dmamap_sync(sc->sc_dmat, cur_tx->map,
 1403                             0, cur_tx->map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->sc_dmat, cur_tx->map);
 1405                 }
ifp->if_opackets++;
sc->xl_cdata.xl_tx_cnt--;
XL_INC(idx, XL_TX_LIST_CNT);
ifp->if_timer = 0;
 1412         }
sc->xl_cdata.xl_tx_cons = idx;
 1416         if (cur_tx != NULL)
ifp->if_flags &= ~IFF_OACTIVE;
 1418 }
 1420 /*
 1421  * TX 'end of channel' interrupt handler. Actually, we should
 1422  * only get a 'TX complete' interrupt if there's a transmit error,
 1423  * so this is really TX error handler.
 1424  */
 1425 void
xl_txeoc(struct xl_softc *sc)
 1427 {
u_int8_t        txstat;
 1430         while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
 1431                 if (txstat & XL_TXSTATUS_UNDERRUN ||
txstat & XL_TXSTATUS_JABBER ||
txstat & XL_TXSTATUS_RECLAIM) {
 1434                         if (txstat != 0x90) {
printf("%s: transmission error: %x\n",
sc->sc_dev.dv_xname, txstat);
 1437                         }
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
xl_wait(sc);
 1440                         if (sc->xl_type == XL_TYPE_905B) {
 1441                                 if (sc->xl_cdata.xl_tx_cnt) {
 1442                                         int i;
 1443                                         struct xl_chain *c;
i = sc->xl_cdata.xl_tx_cons;
c = &sc->xl_cdata.xl_tx_chain[i];
CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
c->xl_phys);
CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
 1450                                 }
 1451                         } else {
 1452                                 if (sc->xl_cdata.xl_tx_head != NULL)
CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
sc->sc_listmap->dm_segs[0].ds_addr +
 1455                                             ((caddr_t)sc->xl_cdata.xl_tx_head->xl_ptr -
sc->sc_listkva));
 1457                         }
 1458                         /*
 1459                          * Remember to set this for the
 1460                          * first generation 3c90X chips.
 1461                          */
CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
 1463                         if (txstat & XL_TXSTATUS_UNDERRUN &&
sc->xl_tx_thresh < XL_PACKET_SIZE) {
sc->xl_tx_thresh += XL_MIN_FRAMELEN;
 1466 #ifdef notdef
printf("%s: tx underrun, increasing tx start"
 1468                                     " threshold to %d\n", sc->sc_dev.dv_xname,
sc->xl_tx_thresh);
 1470 #endif
 1471                         }
CSR_WRITE_2(sc, XL_COMMAND,
XL_CMD_TX_SET_START|sc->xl_tx_thresh);
 1474                         if (sc->xl_type == XL_TYPE_905B) {
CSR_WRITE_2(sc, XL_COMMAND,
XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
 1477                         }
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
 1480                 } else {
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
 1483                 }
 1484                 /*
 1485                  * Write an arbitrary byte to the TX_STATUS register
 1486                  * to clear this interrupt/error and advance to the next.
 1487                  */
CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
 1489         }
 1490 }
 1492 int
xl_intr(void *arg)
 1494 {
 1495         struct xl_softc         *sc;
 1496         struct ifnet            *ifp;
u_int16_t               status;
 1498         int                     claimed = 0;
sc = arg;
ifp = &sc->sc_arpcom.ac_if;
 1503         while ((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && status != 0xFFFF) {
claimed = 1;
CSR_WRITE_2(sc, XL_COMMAND,
XL_CMD_INTR_ACK|(status & XL_INTRS));
 1510                 if (sc->intr_ack)
 1511                         (*sc->intr_ack)(sc);
 1513                 if (status & XL_STAT_UP_COMPLETE) {
 1514                         int curpkts;
curpkts = ifp->if_ipackets;
xl_rxeof(sc);
 1518                         if (curpkts == ifp->if_ipackets) {
 1519                                 while (xl_rx_resync(sc))
xl_rxeof(sc);
 1521                         }
 1522                 }
 1524                 if (status & XL_STAT_DOWN_COMPLETE) {
 1525                         if (sc->xl_type == XL_TYPE_905B)
xl_txeof_90xB(sc);
 1527                         else
xl_txeof(sc);
 1529                 }
 1531                 if (status & XL_STAT_TX_COMPLETE) {
ifp->if_oerrors++;
xl_txeoc(sc);
 1534                 }
 1536                 if (status & XL_STAT_ADFAIL) {
xl_reset(sc);
xl_init(sc);
 1539                 }
 1541                 if (status & XL_STAT_STATSOFLOW) {
sc->xl_stats_no_timeout = 1;
xl_stats_update(sc);
sc->xl_stats_no_timeout = 0;
 1545                 }
 1546         }
 1548         if (!IFQ_IS_EMPTY(&ifp->if_snd))
 1549                 (*ifp->if_start)(ifp);
 1551         return (claimed);
 1552 }
 1554 void
xl_stats_update(void *xsc)
 1556 {
 1557         struct xl_softc         *sc;
 1558         struct ifnet            *ifp;
 1559         struct xl_stats         xl_stats;
u_int8_t                *p;
 1561         int                     i;
 1562         struct mii_data         *mii = NULL;
bzero((char *)&xl_stats, sizeof(struct xl_stats));
sc = xsc;
ifp = &sc->sc_arpcom.ac_if;
 1568         if (sc->xl_hasmii)
mii = &sc->sc_mii;
p = (u_int8_t *)&xl_stats;
 1573         /* Read all the stats registers. */
XL_SEL_WIN(6);
 1576         for (i = 0; i < 16; i++)
 1577                 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
ifp->if_ierrors += xl_stats.xl_rx_overrun;
ifp->if_collisions += xl_stats.xl_tx_multi_collision +
xl_stats.xl_tx_single_collision +
xl_stats.xl_tx_late_collision;
 1585         /*
 1586          * Boomerang and cyclone chips have an extra stats counter
 1587          * in window 4 (BadSSD). We have to read this too in order
 1588          * to clear out all the stats registers and avoid a statsoflow
 1589          * interrupt.
 1590          */
XL_SEL_WIN(4);
CSR_READ_1(sc, XL_W4_BADSSD);
 1594         if (mii != NULL && (!sc->xl_stats_no_timeout))
mii_tick(mii);
XL_SEL_WIN(7);
 1599         if (!sc->xl_stats_no_timeout)
timeout_add(&sc->xl_stsup_tmo, hz);
 1601 }
 1603 /*
 1604  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
 1605  * pointers to the fragment pointers.
 1606  */
 1607 int
xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf *m_head)
 1609 {
 1610         int             error, frag, total_len;
u_int32_t       status;
bus_dmamap_t    map;
map = sc->sc_tx_sparemap;
reload:
error = bus_dmamap_load_mbuf(sc->sc_dmat, map,
m_head, BUS_DMA_NOWAIT);
 1620         if (error && error != EFBIG) {
m_freem(m_head);
 1622                 return (1);
 1623         }
 1625         /*
 1626          * Start packing the mbufs in this chain into
 1627          * the fragment pointers. Stop when we run out
 1628          * of fragments or hit the end of the mbuf chain.
 1629          */
 1630         for (frag = 0, total_len = 0; frag < map->dm_nsegs; frag++) {
 1631                 if (frag == XL_MAXFRAGS)
 1632                         break;
total_len += map->dm_segs[frag].ds_len;
c->xl_ptr->xl_frag[frag].xl_addr =
htole32(map->dm_segs[frag].ds_addr);
c->xl_ptr->xl_frag[frag].xl_len =
htole32(map->dm_segs[frag].ds_len);
 1638         }
 1640         /*
 1641          * Handle special case: we used up all 63 fragments,
 1642          * but we have more mbufs left in the chain. Copy the
 1643          * data into an mbuf cluster. Note that we don't
 1644          * bother clearing the values in the other fragment
 1645          * pointers/counters; it wouldn't gain us anything,
 1646          * and would waste cycles.
 1647          */
 1648         if (error) {
 1649                 struct mbuf     *m_new = NULL;
MGETHDR(m_new, M_DONTWAIT, MT_DATA);
 1652                 if (m_new == NULL) {
m_freem(m_head);
 1654                         return (1);
 1655                 }
 1656                 if (m_head->m_pkthdr.len > MHLEN) {
MCLGET(m_new, M_DONTWAIT);
 1658                         if (!(m_new->m_flags & M_EXT)) {
m_freem(m_new);
m_freem(m_head);
 1661                                 return (1);
 1662                         }
 1663                 }
m_copydata(m_head, 0, m_head->m_pkthdr.len,     
mtod(m_new, caddr_t));
m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
m_freem(m_head);
m_head = m_new;
 1669                 goto reload;
 1670         }
bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
BUS_DMASYNC_PREWRITE);
 1675         if (c->map->dm_nsegs != 0) {
bus_dmamap_sync(sc->sc_dmat, c->map,
 1677                     0, c->map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->sc_dmat, c->map);
 1679         }
c->xl_mbuf = m_head;
sc->sc_tx_sparemap = c->map;
c->map = map;
c->xl_ptr->xl_frag[frag - 1].xl_len |= htole32(XL_LAST_FRAG);
c->xl_ptr->xl_status = htole32(total_len);
c->xl_ptr->xl_next = 0;
 1688         if (sc->xl_type == XL_TYPE_905B) {
status = XL_TXSTAT_RND_DEFEAT;
 1691 #ifndef XL905B_TXCSUM_BROKEN
 1692                 if (m_head->m_pkthdr.csum_flags) {
 1693                         if (m_head->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT)
status |= XL_TXSTAT_IPCKSUM;
 1695                         if (m_head->m_pkthdr.csum_flags & M_TCPV4_CSUM_OUT)
status |= XL_TXSTAT_TCPCKSUM;
 1697                         if (m_head->m_pkthdr.csum_flags & M_UDPV4_CSUM_OUT)
status |= XL_TXSTAT_UDPCKSUM;
 1699                 }
 1700 #endif
c->xl_ptr->xl_status = htole32(status);
 1702         }
bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
offsetof(struct xl_list_data, xl_tx_list[0]),
 1706             sizeof(struct xl_list) * XL_TX_LIST_CNT,
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 1709         return (0);
 1710 }
 1712 /*
 1713  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
 1714  * to the mbuf data regions directly in the transmit lists. We also save a
 1715  * copy of the pointers since the transmit list fragment pointers are
 1716  * physical addresses.
 1717  */
 1718 void
xl_start(struct ifnet *ifp)
 1720 {
 1721         struct xl_softc         *sc;
 1722         struct mbuf             *m_head = NULL;
 1723         struct xl_chain         *prev = NULL, *cur_tx = NULL, *start_tx;
 1724         struct xl_chain         *prev_tx;
 1725         int                     error;
sc = ifp->if_softc;
 1729         /*
 1730          * Check for an available queue slot. If there are none,
 1731          * punt.
 1732          */
 1733         if (sc->xl_cdata.xl_tx_free == NULL) {
xl_txeoc(sc);
xl_txeof(sc);
 1736                 if (sc->xl_cdata.xl_tx_free == NULL) {
ifp->if_flags |= IFF_OACTIVE;
 1738                         return;
 1739                 }
 1740         }
start_tx = sc->xl_cdata.xl_tx_free;
 1744         while (sc->xl_cdata.xl_tx_free != NULL) {
IFQ_DEQUEUE(&ifp->if_snd, m_head);
 1746                 if (m_head == NULL)
 1747                         break;
 1749                 /* Pick a descriptor off the free list. */
prev_tx = cur_tx;
cur_tx = sc->xl_cdata.xl_tx_free;
 1753                 /* Pack the data into the descriptor. */
error = xl_encap(sc, cur_tx, m_head);
 1755                 if (error) {
cur_tx = prev_tx;
 1757                         continue;
 1758                 }
sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
cur_tx->xl_next = NULL;
 1763                 /* Chain it together. */
 1764                 if (prev != NULL) {
prev->xl_next = cur_tx;
prev->xl_ptr->xl_next =
sc->sc_listmap->dm_segs[0].ds_addr +
 1768                             ((caddr_t)cur_tx->xl_ptr - sc->sc_listkva);
 1770                 }
prev = cur_tx;
 1773 #if NBPFILTER > 0
 1774                 /*
 1775                  * If there's a BPF listener, bounce a copy of this frame
 1776                  * to him.
 1777                  */
 1778                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, cur_tx->xl_mbuf,
BPF_DIRECTION_OUT);
 1781 #endif
 1782         }
 1784         /*
 1785          * If there are no packets queued, bail.
 1786          */
 1787         if (cur_tx == NULL)
 1788                 return;
 1790         /*
 1791          * Place the request for the upload interrupt
 1792          * in the last descriptor in the chain. This way, if
 1793          * we're chaining several packets at once, we'll only
 1794          * get an interrupt once for the whole chain rather than
 1795          * once for each packet.
 1796          */
cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR);
 1799         /*
 1800          * Queue the packets. If the TX channel is clear, update
 1801          * the downlist pointer register.
 1802          */
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
xl_wait(sc);
 1806         if (sc->xl_cdata.xl_tx_head != NULL) {
sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
sc->sc_listmap->dm_segs[0].ds_addr +
 1810                     ((caddr_t)start_tx->xl_ptr - sc->sc_listkva);
sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &=
htole32(~XL_TXSTAT_DL_INTR);
sc->xl_cdata.xl_tx_tail = cur_tx;
 1814         } else {
sc->xl_cdata.xl_tx_head = start_tx;
sc->xl_cdata.xl_tx_tail = cur_tx;
 1817         }
 1818         if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
sc->sc_listmap->dm_segs[0].ds_addr +
 1821                     ((caddr_t)start_tx->xl_ptr - sc->sc_listkva));
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
XL_SEL_WIN(7);
 1827         /*
 1828          * Set a timeout in case the chip goes out to lunch.
 1829          */
ifp->if_timer = 5;
 1832         /*
 1833          * XXX Under certain conditions, usually on slower machines
 1834          * where interrupts may be dropped, it's possible for the
 1835          * adapter to chew up all the buffers in the receive ring
 1836          * and stall, without us being able to do anything about it.
 1837          * To guard against this, we need to make a pass over the
 1838          * RX queue to make sure there aren't any packets pending.
 1839          * Doing it here means we can flush the receive ring at the
 1840          * same time the chip is DMAing the transmit descriptors we
 1841          * just gave it.
 1842          *
 1843          * 3Com goes to some lengths to emphasize the Parallel Tasking (tm)
 1844          * nature of their chips in all their marketing literature;
 1845          * we may as well take advantage of it. :)
 1846          */
xl_rxeof(sc);
 1848 }
 1850 void
xl_start_90xB(struct ifnet *ifp)
 1852 {
 1853         struct xl_softc *sc;
 1854         struct mbuf     *m_head = NULL;
 1855         struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx;
 1856         struct xl_chain *prev_tx;
 1857         int             error, idx;
sc = ifp->if_softc;
 1861         if (ifp->if_flags & IFF_OACTIVE)
 1862                 return;
idx = sc->xl_cdata.xl_tx_prod;
start_tx = &sc->xl_cdata.xl_tx_chain[idx];
 1867         while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) {
 1869                 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
ifp->if_flags |= IFF_OACTIVE;
 1871                         break;
 1872                 }
IFQ_DEQUEUE(&ifp->if_snd, m_head);
 1875                 if (m_head == NULL)
 1876                         break;
prev_tx = cur_tx;
cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
 1881                 /* Pack the data into the descriptor. */
error = xl_encap(sc, cur_tx, m_head);
 1883                 if (error) {
cur_tx = prev_tx;
 1885                         continue;
 1886                 }
 1888                 /* Chain it together. */
 1889                 if (prev != NULL)
prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
prev = cur_tx;
 1893 #if NBPFILTER > 0
 1894                 /*
 1895                  * If there's a BPF listener, bounce a copy of this frame
 1896                  * to him.
 1897                  */
 1898                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, cur_tx->xl_mbuf,
BPF_DIRECTION_OUT);
 1901 #endif
XL_INC(idx, XL_TX_LIST_CNT);
sc->xl_cdata.xl_tx_cnt++;
 1905         }
 1907         /*
 1908          * If there are no packets queued, bail.
 1909          */
 1910         if (cur_tx == NULL)
 1911                 return;
 1913         /*
 1914          * Place the request for the upload interrupt
 1915          * in the last descriptor in the chain. This way, if
 1916          * we're chaining several packets at once, we'll only
 1917          * get an interrupt once for the whole chain rather than
 1918          * once for each packet.
 1919          */
cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR);
 1922         /* Start transmission */
sc->xl_cdata.xl_tx_prod = idx;
start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys);
 1926         /*
 1927          * Set a timeout in case the chip goes out to lunch.
 1928          */
ifp->if_timer = 5;
 1930 }
 1932 void
xl_init(void *xsc)
 1934 {
 1935         struct xl_softc         *sc = xsc;
 1936         struct ifnet            *ifp = &sc->sc_arpcom.ac_if;
 1937         int                     s, i;
u_int16_t               rxfilt = 0;
 1939         struct mii_data         *mii = NULL;
s = splnet();
 1943         /*
 1944          * Cancel pending I/O and free all RX/TX buffers.
 1945          */
xl_stop(sc);
 1948         if (sc->xl_hasmii)
mii = &sc->sc_mii;
 1951         if (mii == NULL) {
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
xl_wait(sc);
 1954         }
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
xl_wait(sc);
DELAY(10000);
 1959         /* Init our MAC address */
XL_SEL_WIN(2);
 1961         for (i = 0; i < ETHER_ADDR_LEN; i++) {
CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
sc->sc_arpcom.ac_enaddr[i]);
 1964         }
 1966         /* Clear the station mask. */
 1967         for (i = 0; i < 3; i++)
CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
 1969 #ifdef notdef
 1970         /* Reset TX and RX. */
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
xl_wait(sc);
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
xl_wait(sc);
 1975 #endif
 1976         /* Init circular RX list. */
 1977         if (xl_list_rx_init(sc) == ENOBUFS) {
printf("%s: initialization failed: no "
 1979                         "memory for rx buffers\n", sc->sc_dev.dv_xname);
xl_stop(sc);
splx(s);
 1982                 return;
 1983         }
 1985         /* Init TX descriptors. */
 1986         if (sc->xl_type == XL_TYPE_905B)
xl_list_tx_init_90xB(sc);
 1988         else
xl_list_tx_init(sc);
 1991         /*
 1992          * Set the TX freethresh value.
 1993          * Note that this has no effect on 3c905B "cyclone"
 1994          * cards but is required for 3c900/3c905 "boomerang"
 1995          * cards in order to enable the download engine.
 1996          */
CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
 1999         /* Set the TX start threshold for best performance. */
sc->xl_tx_thresh = XL_MIN_FRAMELEN;
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
 2003         /*
 2004          * If this is a 3c905B, also set the tx reclaim threshold.
 2005          * This helps cut down on the number of tx reclaim errors
 2006          * that could happen on a busy network. The chip multiplies
 2007          * the register value by 16 to obtain the actual threshold
 2008          * in bytes, so we divide by 16 when setting the value here.
 2009          * The existing threshold value can be examined by reading
 2010          * the register at offset 9 in window 5.
 2011          */
 2012         if (sc->xl_type == XL_TYPE_905B) {
CSR_WRITE_2(sc, XL_COMMAND,
XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
 2015         }
 2017         /* Set RX filter bits. */
XL_SEL_WIN(5);
rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
 2021         /* Set the individual bit to receive frames for this host only. */
rxfilt |= XL_RXFILTER_INDIVIDUAL;
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
 2026         /* Set promiscuous mode. */
xl_setpromisc(sc);
rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
 2031         /*
 2032          * Set capture broadcast bit to capture broadcast frames.
 2033          */
 2034         if (ifp->if_flags & IFF_BROADCAST)
rxfilt |= XL_RXFILTER_BROADCAST;
 2036         else
rxfilt &= ~XL_RXFILTER_BROADCAST;
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt);
 2041         /*
 2042          * Program the multicast filter, if necessary.
 2043          */
 2044         if (sc->xl_type == XL_TYPE_905B)
xl_setmulti_hash(sc);
 2046         else
xl_setmulti(sc);
 2049         /*
 2050          * Load the address of the RX list. We have to
 2051          * stall the upload engine before we can manipulate
 2052          * the uplist pointer register, then unstall it when
 2053          * we're finished. We also have to wait for the
 2054          * stall command to complete before proceeding.
 2055          * Note that we have to do this after any RX resets
 2056          * have completed since the uplist register is cleared
 2057          * by a reset.
 2058          */
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
xl_wait(sc);
CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->sc_listmap->dm_segs[0].ds_addr +
offsetof(struct xl_list_data, xl_rx_list[0]));
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
xl_wait(sc);
 2066         if (sc->xl_type == XL_TYPE_905B) {
 2067                 /* Set polling interval */
CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
 2069                 /* Load the address of the TX list */
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
xl_wait(sc);
CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
sc->sc_listmap->dm_segs[0].ds_addr +
offsetof(struct xl_list_data, xl_tx_list[0]));
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
xl_wait(sc);
 2077         }
 2079         /*
 2080          * If the coax transceiver is on, make sure to enable
 2081          * the DC-DC converter.
 2082          */
XL_SEL_WIN(3);
 2084         if (sc->xl_xcvr == XL_XCVR_COAX)
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
 2086         else
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
 2089         /*
 2090          * increase packet size to allow reception of 802.1q or ISL packets.
 2091          * For the 3c90x chip, set the 'allow large packets' bit in the MAC
 2092          * control register. For 3c90xB/C chips, use the RX packet size
 2093          * register.
 2094          */
 2096         if (sc->xl_type == XL_TYPE_905B)
CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
 2098         else {
u_int8_t macctl;
macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
macctl |= XL_MACCTRL_ALLOW_LARGE_PACK;
CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
 2103         }
 2105         /* Clear out the stats counters. */
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
sc->xl_stats_no_timeout = 1;
xl_stats_update(sc);
sc->xl_stats_no_timeout = 0;
XL_SEL_WIN(4);
CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
 2114         /*
 2115          * Enable interrupts.
 2116          */
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
 2121         if (sc->intr_ack)
 2122                 (*sc->intr_ack)(sc);
 2124         /* Set the RX early threshold */
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
 2128         /* Enable receiver and transmitter. */
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
xl_wait(sc);
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
xl_wait(sc);
 2134         /* Restore state of BMCR */
 2135         if (mii != NULL)
mii_mediachg(mii);
 2138         /* Select window 7 for normal operations. */
XL_SEL_WIN(7);
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
splx(s);
timeout_add(&sc->xl_stsup_tmo, hz);
 2147 }
 2149 /*
 2150  * Set media options.
 2151  */
 2152 int
xl_ifmedia_upd(struct ifnet *ifp)
 2154 {
 2155         struct xl_softc         *sc;
 2156         struct ifmedia          *ifm = NULL;
 2157         struct mii_data         *mii = NULL;
sc = ifp->if_softc;
 2161         if (sc->xl_hasmii)
mii = &sc->sc_mii;
 2163         if (mii == NULL)
ifm = &sc->ifmedia;
 2165         else
ifm = &mii->mii_media;
 2168         switch(IFM_SUBTYPE(ifm->ifm_media)) {
 2169         case IFM_100_FX:
 2170         case IFM_10_FL:
 2171         case IFM_10_2:
 2172         case IFM_10_5:
xl_setmode(sc, ifm->ifm_media);
 2174                 return (0);
 2175                 break;
 2176         default:
 2177                 break;
 2178         }
 2180         if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
 2181                 || sc->xl_media & XL_MEDIAOPT_BT4) {
xl_init(sc);
 2183         } else {
xl_setmode(sc, ifm->ifm_media);
 2185         }
 2187         return (0);
 2188 }
 2190 /*
 2191  * Report current media status.
 2192  */
 2193 void
xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
 2195 {
 2196         struct xl_softc         *sc;
u_int32_t               icfg;
u_int16_t               status = 0;
 2199         struct mii_data         *mii = NULL;
sc = ifp->if_softc;
 2202         if (sc->xl_hasmii != 0)
mii = &sc->sc_mii;
XL_SEL_WIN(4);
status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
XL_SEL_WIN(3);
icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
icfg >>= XL_ICFG_CONNECTOR_BITS;
ifmr->ifm_active = IFM_ETHER;
ifmr->ifm_status = IFM_AVALID;
 2215         if ((status & XL_MEDIASTAT_CARRIER) == 0)
ifmr->ifm_status |= IFM_ACTIVE;
 2218         switch(icfg) {
 2219         case XL_XCVR_10BT:
ifmr->ifm_active = IFM_ETHER|IFM_10_T;
 2221                 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
ifmr->ifm_active |= IFM_FDX;
 2223                 else
ifmr->ifm_active |= IFM_HDX;
 2225                 break;
 2226         case XL_XCVR_AUI:
 2227                 if (sc->xl_type == XL_TYPE_905B &&
sc->xl_media == XL_MEDIAOPT_10FL) {
ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
 2230                         if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
ifmr->ifm_active |= IFM_FDX;
 2232                         else
ifmr->ifm_active |= IFM_FDX;
 2234                 } else
ifmr->ifm_active = IFM_ETHER|IFM_10_5;
 2236                 break;
 2237         case XL_XCVR_COAX:
ifmr->ifm_active = IFM_ETHER|IFM_10_2;
 2239                 break;
 2240         /*
 2241          * XXX MII and BTX/AUTO should be separate cases.
 2242          */
 2244         case XL_XCVR_100BTX:
 2245         case XL_XCVR_AUTO:
 2246         case XL_XCVR_MII:
 2247                 if (mii != NULL) {
mii_pollstat(mii);
ifmr->ifm_active = mii->mii_media_active;
ifmr->ifm_status = mii->mii_media_status;
 2251                 }
 2252                 break;
 2253         case XL_XCVR_100BFX:
ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
 2255                 break;
 2256         default:
printf("%s: unknown XCVR type: %d\n", sc->sc_dev.dv_xname, icfg);
 2258                 break;
 2259         }
 2260 }
 2262 int
xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
 2264 {
 2265         struct xl_softc *sc = ifp->if_softc;
 2266         struct ifreq *ifr = (struct ifreq *)data;
 2267         struct ifaddr *ifa = (struct ifaddr *)data;
 2268         int s, error = 0;
 2269         struct mii_data *mii = NULL;
s = splnet();
 2273         if ((error = ether_ioctl(ifp, &sc->sc_arpcom, command, data)) > 0) {
splx(s);
 2275                 return error;
 2276         }
 2278         switch(command) {
 2279         case SIOCSIFADDR:
ifp->if_flags |= IFF_UP;
 2281                 if (!(ifp->if_flags & IFF_RUNNING))
xl_init(sc);
 2283 #ifdef INET
 2284                 if (ifa->ifa_addr->sa_family == AF_INET)
arp_ifinit(&sc->sc_arpcom, ifa);
 2286 #endif /* INET */
 2287                 break;
 2289         case SIOCSIFMTU:
 2290                 if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN)
error = EINVAL;
 2292                 else if (ifp->if_mtu != ifr->ifr_mtu)
ifp->if_mtu = ifr->ifr_mtu;
 2294                 break;
 2296         case SIOCSIFFLAGS:
XL_SEL_WIN(5);
 2298                 if (ifp->if_flags & IFF_UP) {
 2299                         if (ifp->if_flags & IFF_RUNNING &&
 2300                             (ifp->if_flags ^ sc->xl_if_flags) &
IFF_PROMISC) {
xl_setpromisc(sc);
XL_SEL_WIN(7);
 2304                         } else {
 2305                                 if (!(ifp->if_flags & IFF_RUNNING))
xl_init(sc);
 2307                         }
 2308                 } else {
 2309                         if (ifp->if_flags & IFF_RUNNING)
xl_stop(sc);
 2311                 }
sc->xl_if_flags = ifp->if_flags;
 2313                 break;
 2314         case SIOCADDMULTI:
 2315         case SIOCDELMULTI:
error = (command == SIOCADDMULTI) ?
ether_addmulti(ifr, &sc->sc_arpcom) :
ether_delmulti(ifr, &sc->sc_arpcom);
 2320                 if (error == ENETRESET) {
 2321                         /*
 2322                          * Multicast list has changed; set the hardware
 2323                          * filter accordingly.
 2324                          */
 2325                         if (ifp->if_flags & IFF_RUNNING) {
 2326                                 if (sc->xl_type == XL_TYPE_905B)
xl_setmulti_hash(sc);
 2328                                 else
xl_setmulti(sc);
 2330                         }
error = 0;
 2332                 }
 2333                 break;
 2334         case SIOCGIFMEDIA:
 2335         case SIOCSIFMEDIA:
 2336                 if (sc->xl_hasmii != 0)
mii = &sc->sc_mii;
 2338                 if (mii == NULL)
error = ifmedia_ioctl(ifp, ifr,
 2340                             &sc->ifmedia, command);
 2341                 else
error = ifmedia_ioctl(ifp, ifr,
 2343                             &mii->mii_media, command);
 2344                 break;
 2345         default:
error = EINVAL;
 2347                 break;
 2348         }
splx(s);
 2352         return (error);
 2353 }
 2355 void
xl_watchdog(struct ifnet *ifp)
 2357 {
 2358         struct xl_softc         *sc;
u_int16_t               status = 0;
sc = ifp->if_softc;
ifp->if_oerrors++;
XL_SEL_WIN(4);
status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname);
 2368         if (status & XL_MEDIASTAT_CARRIER)
printf("%s: no carrier - transceiver cable problem?\n",
sc->sc_dev.dv_xname);
xl_txeoc(sc);
xl_txeof(sc);
xl_rxeof(sc);
xl_reset(sc);
xl_init(sc);
 2377         if (!IFQ_IS_EMPTY(&ifp->if_snd))
 2378                 (*ifp->if_start)(ifp);
 2379 }
 2381 void
xl_freetxrx(struct xl_softc *sc)
 2383 {
bus_dmamap_t    map;
 2385         int             i;
 2387         /*
 2388          * Free data in the RX lists.
 2389          */
 2390         for (i = 0; i < XL_RX_LIST_CNT; i++) {
 2391                 if (sc->xl_cdata.xl_rx_chain[i].map->dm_nsegs != 0) {
map = sc->xl_cdata.xl_rx_chain[i].map;
bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
BUS_DMASYNC_POSTREAD);
bus_dmamap_unload(sc->sc_dmat, map);
 2397                 }
 2398                 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
 2401                 }
 2402         }
bzero((char *)&sc->xl_ldata->xl_rx_list,
 2404                 sizeof(sc->xl_ldata->xl_rx_list));
 2405         /*
 2406          * Free the TX list buffers.
 2407          */
 2408         for (i = 0; i < XL_TX_LIST_CNT; i++) {
 2409                 if (sc->xl_cdata.xl_tx_chain[i].map->dm_nsegs != 0) {
map = sc->xl_cdata.xl_tx_chain[i].map;
bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->sc_dmat, map);
 2415                 }
 2416                 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
 2419                 }
 2420         }
bzero((char *)&sc->xl_ldata->xl_tx_list,
 2422                 sizeof(sc->xl_ldata->xl_tx_list));
 2423 }
 2425 /*
 2426  * Stop the adapter and free any mbufs allocated to the
 2427  * RX and TX lists.
 2428  */
 2429 void
xl_stop(struct xl_softc *sc)
 2431 {
 2432         struct ifnet *ifp;
ifp = &sc->sc_arpcom.ac_if;
ifp->if_timer = 0;
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
xl_wait(sc);
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
DELAY(800);
 2446 #ifdef foo
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
xl_wait(sc);
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
xl_wait(sc);
 2451 #endif
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
 2457         if (sc->intr_ack)
 2458                 (*sc->intr_ack)(sc);
 2460         /* Stop the stats updater. */
timeout_del(&sc->xl_stsup_tmo);
ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
xl_freetxrx(sc);
 2466 }
 2468 void
xl_attach(struct xl_softc *sc)
 2470 {
u_int8_t enaddr[ETHER_ADDR_LEN];
u_int16_t               xcvr[2];
 2473         struct ifnet *ifp = &sc->sc_arpcom.ac_if;
 2474         int i, media = IFM_ETHER|IFM_100_TX|IFM_FDX;
 2475         struct ifmedia *ifm;
i = splnet();
xl_reset(sc);
splx(i);
 2481         /*
 2482          * Get station address from the EEPROM.
 2483          */
 2484         if (xl_read_eeprom(sc, (caddr_t)&enaddr, XL_EE_OEM_ADR0, 3, 1)) {
printf("\n%s: failed to read station address\n",
sc->sc_dev.dv_xname);
 2487                 return;
 2488         }
bcopy(enaddr, (char *)&sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN);
 2491         if (bus_dmamem_alloc(sc->sc_dmat, sizeof(struct xl_list_data),
PAGE_SIZE, 0, sc->sc_listseg, 1, &sc->sc_listnseg,
BUS_DMA_NOWAIT) != 0) {
printf(": can't alloc list mem\n");
 2495                 return;
 2496         }
 2497         if (bus_dmamem_map(sc->sc_dmat, sc->sc_listseg, sc->sc_listnseg,
 2498             sizeof(struct xl_list_data), &sc->sc_listkva,
BUS_DMA_NOWAIT) != 0) {
printf(": can't map list mem\n");
 2501                 return;
 2502         }
 2503         if (bus_dmamap_create(sc->sc_dmat, sizeof(struct xl_list_data), 1,
 2504             sizeof(struct xl_list_data), 0, BUS_DMA_NOWAIT,
 2505             &sc->sc_listmap) != 0) {
printf(": can't alloc list map\n");
 2507                 return;
 2508         }
 2509         if (bus_dmamap_load(sc->sc_dmat, sc->sc_listmap, sc->sc_listkva,
 2510             sizeof(struct xl_list_data), NULL, BUS_DMA_NOWAIT) != 0) {
printf(": can't load list map\n");
 2512                 return;
 2513         }
sc->xl_ldata = (struct xl_list_data *)sc->sc_listkva;
bzero(sc->xl_ldata, sizeof(struct xl_list_data));
 2517         for (i = 0; i < XL_RX_LIST_CNT; i++) {
 2518                 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES,
 2519                     0, BUS_DMA_NOWAIT,
 2520                     &sc->xl_cdata.xl_rx_chain[i].map) != 0) {
printf(": can't create rx map\n");
 2522                         return;
 2523                 }
 2524         }
 2525         if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0,
BUS_DMA_NOWAIT, &sc->sc_rx_sparemap) != 0) {
printf(": can't create rx spare map\n");
 2528                 return;
 2529         }
 2531         for (i = 0; i < XL_TX_LIST_CNT; i++) {
 2532                 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES,
XL_TX_LIST_CNT - 3, MCLBYTES, 0, BUS_DMA_NOWAIT,
 2534                     &sc->xl_cdata.xl_tx_chain[i].map) != 0) {
printf(": can't create tx map\n");
 2536                         return;
 2537                 }
 2538         }
 2539         if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, XL_TX_LIST_CNT - 3,
MCLBYTES, 0, BUS_DMA_NOWAIT, &sc->sc_tx_sparemap) != 0) {
printf(": can't create tx spare map\n");
 2542                 return;
 2543         }
printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr));
 2547         if (sc->xl_flags & (XL_FLAG_INVERT_LED_PWR|XL_FLAG_INVERT_MII_PWR)) {
u_int16_t n;
XL_SEL_WIN(2);
n = CSR_READ_2(sc, 12);
 2553                 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR)
n |= 0x0010;
 2556                 if (sc->xl_flags & XL_FLAG_INVERT_MII_PWR)
n |= 0x4000;
CSR_WRITE_2(sc, 12, n);
 2560         }
 2562         /*
 2563          * Figure out the card type. 3c905B adapters have the
 2564          * 'supportsNoTxLength' bit set in the capabilities
 2565          * word in the EEPROM.
 2566          * Note: my 3c575C cardbus card lies. It returns a value
 2567          * of 0x1578 for its capabilities word, which is somewhat
 2568          * nonsensical. Another way to distinguish a 3c90x chip
 2569          * from a 3c90xB/C chip is to check for the 'supportsLargePackets'
 2570          * bit. This will only be set for 3c90x boomerage chips.
 2571          */
xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
 2573         if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
 2574             !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
sc->xl_type = XL_TYPE_905B;
 2576         else
sc->xl_type = XL_TYPE_90X;
timeout_set(&sc->xl_stsup_tmo, xl_stats_update, sc);
ifp->if_softc = sc;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_ioctl = xl_ioctl;
 2584         if (sc->xl_type == XL_TYPE_905B)
ifp->if_start = xl_start_90xB;
 2586         else
ifp->if_start = xl_start;
ifp->if_watchdog = xl_watchdog;
ifp->if_baudrate = 10000000;
IFQ_SET_MAXLEN(&ifp->if_snd, XL_TX_LIST_CNT - 1);
IFQ_SET_READY(&ifp->if_snd);
bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
ifp->if_capabilities = IFCAP_VLAN_MTU;
 2596 #ifndef XL905B_TXCSUM_BROKEN
ifp->if_capabilities |= IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|
IFCAP_CSUM_UDPv4;
 2599 #endif
XL_SEL_WIN(3);
sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
xl_mediacheck(sc);
 2611         if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
 2612             || sc->xl_media & XL_MEDIAOPT_BT4) {
ifmedia_init(&sc->sc_mii.mii_media, 0,
xl_ifmedia_upd, xl_ifmedia_sts);
sc->xl_hasmii = 1;
sc->sc_mii.mii_ifp = ifp;
sc->sc_mii.mii_readreg = xl_miibus_readreg;
sc->sc_mii.mii_writereg = xl_miibus_writereg;
sc->sc_mii.mii_statchg = xl_miibus_statchg;
xl_setcfg(sc);
mii_attach((struct device *)sc, &sc->sc_mii, 0xffffffff,
MII_PHY_ANY, MII_OFFSET_ANY, 0);
 2624                 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE,
 2626                             0, NULL);
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
 2628                 }
 2629                 else {
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
 2631                 }
ifm = &sc->sc_mii.mii_media;
 2633         }
 2634         else {
ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
sc->xl_hasmii = 0;
ifm = &sc->ifmedia;
 2638         }
 2640         /*
 2641          * Sanity check. If the user has selected "auto" and this isn't
 2642          * a 10/100 card of some kind, we need to force the transceiver
 2643          * type to something sane.
 2644          */
 2645         if (sc->xl_xcvr == XL_XCVR_AUTO) {
xl_choose_xcvr(sc, 0);
i = splnet();
xl_reset(sc);
splx(i);
 2650         }
 2652         if (sc->xl_media & XL_MEDIAOPT_BT) {
ifmedia_add(ifm, IFM_ETHER|IFM_10_T, 0, NULL);
ifmedia_add(ifm, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
 2655                 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
ifmedia_add(ifm, IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
 2657         }
 2659         if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
 2660                 /*
 2661                  * Check for a 10baseFL board in disguise.
 2662                  */
 2663                 if (sc->xl_type == XL_TYPE_905B &&
sc->xl_media == XL_MEDIAOPT_10FL) {
ifmedia_add(ifm, IFM_ETHER|IFM_10_FL, 0, NULL);
ifmedia_add(ifm, IFM_ETHER|IFM_10_FL|IFM_HDX,
 2667                             0, NULL);
 2668                         if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
ifmedia_add(ifm,
IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
 2671                 } else {
ifmedia_add(ifm, IFM_ETHER|IFM_10_5, 0, NULL);
 2673                 }
 2674         }
 2676         if (sc->xl_media & XL_MEDIAOPT_BNC) {
ifmedia_add(ifm, IFM_ETHER|IFM_10_2, 0, NULL);
 2678         }
 2680         if (sc->xl_media & XL_MEDIAOPT_BFX) {
ifp->if_baudrate = 100000000;
ifmedia_add(ifm, IFM_ETHER|IFM_100_FX, 0, NULL);
 2683         }
 2685         /* Choose a default media. */
 2686         switch(sc->xl_xcvr) {
 2687         case XL_XCVR_10BT:
media = IFM_ETHER|IFM_10_T;
xl_setmode(sc, media);
 2690                 break;
 2691         case XL_XCVR_AUI:
 2692                 if (sc->xl_type == XL_TYPE_905B &&
sc->xl_media == XL_MEDIAOPT_10FL) {
media = IFM_ETHER|IFM_10_FL;
xl_setmode(sc, media);
 2696                 } else {
media = IFM_ETHER|IFM_10_5;
xl_setmode(sc, media);
 2699                 }
 2700                 break;
 2701         case XL_XCVR_COAX:
media = IFM_ETHER|IFM_10_2;
xl_setmode(sc, media);
 2704                 break;
 2705         case XL_XCVR_AUTO:
 2706         case XL_XCVR_100BTX:
 2707         case XL_XCVR_MII:
 2708                 /* Chosen by miibus */
 2709                 break;
 2710         case XL_XCVR_100BFX:
media = IFM_ETHER|IFM_100_FX;
xl_setmode(sc, media);
 2713                 break;
 2714         default:
printf("%s: unknown XCVR type: %d\n", sc->sc_dev.dv_xname,
sc->xl_xcvr);
 2717                 /*
 2718                  * This will probably be wrong, but it prevents
 2719                  * the ifmedia code from panicking.
 2720                  */
media = IFM_ETHER | IFM_10_T;
 2722                 break;
 2723         }
 2725         if (sc->xl_hasmii == 0)
ifmedia_set(&sc->ifmedia, media);
 2728         if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
XL_SEL_WIN(0);
CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
 2731         }
 2733         /*
 2734          * Call MI attach routines.
 2735          */
if_attach(ifp);
ether_ifattach(ifp);
sc->sc_sdhook = shutdownhook_establish(xl_shutdown, sc);
sc->sc_pwrhook = powerhook_establish(xl_power, sc);
 2741 }
 2743 void
xl_shutdown(void *v)
 2745 {
 2746         struct xl_softc *sc = (struct xl_softc *)v;
xl_reset(sc);
xl_stop(sc);
 2750 }
 2752 struct cfdriver xl_cd = {
 2753         0, "xl", DV_IFNET
 2754 };