devid             175 arch/i386/i386/apm.c void apm_powmgt_engage(int onoff, u_int devid);
devid             295 arch/i386/include/apmvar.h int apm_set_powstate(u_int devid, u_int powstate);
devid             206 dev/ic/ath.c   ath_attach(u_int16_t devid, struct ath_softc *sc)
devid             215 dev/ic/ath.c   	DPRINTF(ATH_DEBUG_ANY, ("%s: devid 0x%x\n", __func__, devid));
devid             220 dev/ic/ath.c   	ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, sc->sc_64bit,
devid             237 dev/ic/ath.c   		    ar5k_printver(AR5K_VERSION_DEV, devid),
devid             432 dev/ic/ath.c   	if (ath_gpio_attach(sc, devid) == 0)
devid            3211 dev/ic/ath.c   ath_gpio_attach(struct ath_softc *sc, u_int16_t devid)
devid            3237 dev/ic/ath.c   	    (devid == PCI_PRODUCT_ATHEROS_AR5212_IBM)) {
devid             480 dev/ic/lm78.c  	int banksel, vendid, devid;
devid             495 dev/ic/lm78.c  	devid = sc->lm_readreg(sc, LM_CHIPID);
devid             553 dev/ic/lm78.c  		if (devid >= 0x10 && devid <= 0x29)
devid             554 dev/ic/lm78.c  			printf(": W83792D rev %c\n", 'A' + devid - 0x10);
devid             556 dev/ic/lm78.c  			printf(": W83792D rev 0x%x\n", devid);
devid             904 dev/ic/xl.c    	u_int16_t devid;
devid             911 dev/ic/xl.c    	xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
devid             913 dev/ic/xl.c    	switch(devid) {
devid             986 dev/ic/xl.c    			"defaulting to 10baseT\n", sc->sc_dev.dv_xname, devid);