root/dev/pci/if_sk.c

DEFINITIONS

1. sk_win_read_4
2. sk_win_read_2
3. sk_win_read_1
4. sk_win_write_4
5. sk_win_write_2
6. sk_win_write_1
7. sk_xmac_miibus_readreg
8. sk_xmac_miibus_writereg
9. sk_xmac_miibus_statchg
10. sk_marv_miibus_readreg
11. sk_marv_miibus_writereg
12. sk_marv_miibus_statchg
13. sk_xmac_hash
14. sk_yukon_hash
15. sk_setfilt
16. sk_setmulti
17. sk_setpromisc
18. sk_init_rx_ring
19. sk_init_tx_ring
20. sk_newbuf
21. sk_alloc_jumbo_mem
22. sk_jalloc
23. sk_jfree
24. sk_ifmedia_upd
25. sk_ifmedia_sts
26. sk_ioctl
27. skc_probe
28. sk_reset
29. sk_probe
30. sk_attach
31. skcprint
32. skc_attach
33. sk_encap
34. sk_start
35. sk_watchdog
36. skc_shutdown
37. sk_rxvalid
38. sk_rxeof
39. sk_rxcsum
40. sk_txeof
41. sk_tick
42. sk_yukon_tick
43. sk_intr_bcom
44. sk_intr_xmac
45. sk_intr_yukon
46. sk_intr
47. sk_init_xmac
48. sk_init_yukon
49. sk_init
50. sk_stop
51. sk_dump_txdesc
52. sk_dump_bytes
53. sk_dump_mbuf

    1 /*      $OpenBSD: if_sk.c,v 1.142 2007/05/26 16:44:21 reyk Exp $        */
    3 /*
    4  * Copyright (c) 1997, 1998, 1999, 2000
    5  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. All advertising materials mentioning features or use of this software
   16  *    must display the following acknowledgement:
   17  *      This product includes software developed by Bill Paul.
   18  * 4. Neither the name of the author nor the names of any co-contributors
   19  *    may be used to endorse or promote products derived from this software
   20  *    without specific prior written permission.
   21  *
   22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   32  * THE POSSIBILITY OF SUCH DAMAGE.
   33  *
   34  * $FreeBSD: /c/ncvs/src/sys/pci/if_sk.c,v 1.20 2000/04/22 02:16:37 wpaul Exp $
   35  */
   37 /*
   38  * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
   39  *
   40  * Permission to use, copy, modify, and distribute this software for any
   41  * purpose with or without fee is hereby granted, provided that the above
   42  * copyright notice and this permission notice appear in all copies.
   43  *
   44  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   45  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   46  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
   47  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
   48  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
   49  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
   50  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
   51  */
   53 /*
   54  * SysKonnect SK-NET gigabit ethernet driver for FreeBSD. Supports
   55  * the SK-984x series adapters, both single port and dual port.
   56  * References:
   57  *      The XaQti XMAC II datasheet,
   58  * http://www.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
   59  *      The SysKonnect GEnesis manual, http://www.syskonnect.com
   60  *
   61  * Note: XaQti has been acquired by Vitesse, and Vitesse does not have the
   62  * XMAC II datasheet online. I have put my copy at people.freebsd.org as a
   63  * convenience to others until Vitesse corrects this problem:
   64  *
   65  * http://people.freebsd.org/~wpaul/SysKonnect/xmacii_datasheet_rev_c_9-29.pdf
   66  *
   67  * Written by Bill Paul <wpaul@ee.columbia.edu>
   68  * Department of Electrical Engineering
   69  * Columbia University, New York City
   70  */
   72 /*
   73  * The SysKonnect gigabit ethernet adapters consist of two main
   74  * components: the SysKonnect GEnesis controller chip and the XaQti Corp.
   75  * XMAC II gigabit ethernet MAC. The XMAC provides all of the MAC
   76  * components and a PHY while the GEnesis controller provides a PCI
   77  * interface with DMA support. Each card may have between 512K and
   78  * 2MB of SRAM on board depending on the configuration.
   79  *
   80  * The SysKonnect GEnesis controller can have either one or two XMAC
   81  * chips connected to it, allowing single or dual port NIC configurations.
   82  * SysKonnect has the distinction of being the only vendor on the market
   83  * with a dual port gigabit ethernet NIC. The GEnesis provides dual FIFOs,
   84  * dual DMA queues, packet/MAC/transmit arbiters and direct access to the
   85  * XMAC registers. This driver takes advantage of these features to allow
   86  * both XMACs to operate as independent interfaces.
   87  */
   89 #include "bpfilter.h"
   91 #include <sys/param.h>
   92 #include <sys/systm.h>
   93 #include <sys/sockio.h>
   94 #include <sys/mbuf.h>
   95 #include <sys/malloc.h>
   96 #include <sys/kernel.h>
   97 #include <sys/socket.h>
   98 #include <sys/timeout.h>
   99 #include <sys/device.h>
  100 #include <sys/queue.h>
  102 #include <net/if.h>
  103 #include <net/if_dl.h>
  104 #include <net/if_types.h>
  106 #ifdef INET
  107 #include <netinet/in.h>
  108 #include <netinet/in_systm.h>
  109 #include <netinet/in_var.h>
  110 #include <netinet/ip.h>
  111 #include <netinet/udp.h>
  112 #include <netinet/tcp.h>
  113 #include <netinet/if_ether.h>
  114 #endif
  116 #include <net/if_media.h>
  117 #include <net/if_vlan_var.h>
  119 #if NBPFILTER > 0
  120 #include <net/bpf.h>
  121 #endif
  123 #include <dev/mii/mii.h>
  124 #include <dev/mii/miivar.h>
  125 #include <dev/mii/brgphyreg.h>
  127 #include <dev/pci/pcireg.h>
  128 #include <dev/pci/pcivar.h>
  129 #include <dev/pci/pcidevs.h>
  131 #include <dev/pci/if_skreg.h>
  132 #include <dev/pci/if_skvar.h>
  134 int skc_probe(struct device *, void *, void *);
  135 void skc_attach(struct device *, struct device *self, void *aux);
  136 void skc_shutdown(void *);
  137 int sk_probe(struct device *, void *, void *);
  138 void sk_attach(struct device *, struct device *self, void *aux);
  139 int skcprint(void *, const char *);
  140 int sk_intr(void *);
  141 void sk_intr_bcom(struct sk_if_softc *);
  142 void sk_intr_xmac(struct sk_if_softc *);
  143 void sk_intr_yukon(struct sk_if_softc *);
  144 static __inline int sk_rxvalid(struct sk_softc *, u_int32_t, u_int32_t);
  145 void sk_rxeof(struct sk_if_softc *);
  146 void sk_txeof(struct sk_if_softc *);
  147 int sk_encap(struct sk_if_softc *, struct mbuf *, u_int32_t *);
  148 void sk_start(struct ifnet *);
  149 int sk_ioctl(struct ifnet *, u_long, caddr_t);
  150 void sk_init(void *);
  151 void sk_init_xmac(struct sk_if_softc *);
  152 void sk_init_yukon(struct sk_if_softc *);
  153 void sk_stop(struct sk_if_softc *);
  154 void sk_watchdog(struct ifnet *);
  155 int sk_ifmedia_upd(struct ifnet *);
  156 void sk_ifmedia_sts(struct ifnet *, struct ifmediareq *);
  157 void sk_reset(struct sk_softc *);
  158 int sk_newbuf(struct sk_if_softc *, int, struct mbuf *, bus_dmamap_t);
  159 int sk_alloc_jumbo_mem(struct sk_if_softc *);
  160 void *sk_jalloc(struct sk_if_softc *);
  161 void sk_jfree(caddr_t, u_int, void *);
  162 int sk_init_rx_ring(struct sk_if_softc *);
  163 int sk_init_tx_ring(struct sk_if_softc *);
  165 int sk_xmac_miibus_readreg(struct device *, int, int);
  166 void sk_xmac_miibus_writereg(struct device *, int, int, int);
  167 void sk_xmac_miibus_statchg(struct device *);
  169 int sk_marv_miibus_readreg(struct device *, int, int);
  170 void sk_marv_miibus_writereg(struct device *, int, int, int);
  171 void sk_marv_miibus_statchg(struct device *);
u_int32_t sk_xmac_hash(caddr_t);
u_int32_t sk_yukon_hash(caddr_t);
  175 void sk_setfilt(struct sk_if_softc *, caddr_t, int);
  176 void sk_setmulti(struct sk_if_softc *);
  177 void sk_setpromisc(struct sk_if_softc *);
  178 void sk_tick(void *);
  179 void sk_yukon_tick(void *);
  180 void sk_rxcsum(struct ifnet *, struct mbuf *, const u_int16_t, const u_int16_t);
  182 #ifdef SK_DEBUG
  183 #define DPRINTF(x)      if (skdebug) printf x
  184 #define DPRINTFN(n,x)   if (skdebug >= (n)) printf x
  185 int     skdebug = 0;
  187 void sk_dump_txdesc(struct sk_tx_desc *, int);
  188 void sk_dump_mbuf(struct mbuf *);
  189 void sk_dump_bytes(const char *, int);
  190 #else
  191 #define DPRINTF(x)
  192 #define DPRINTFN(n,x)
  193 #endif
  195 /* supported device vendors */
  196 const struct pci_matchid skc_devices[] = {
  197         { PCI_VENDOR_3COM,              PCI_PRODUCT_3COM_3C940 },
  198         { PCI_VENDOR_3COM,              PCI_PRODUCT_3COM_3C940B },
  199         { PCI_VENDOR_CNET,              PCI_PRODUCT_CNET_GIGACARD },
  200         { PCI_VENDOR_DLINK,             PCI_PRODUCT_DLINK_DGE530T_A1 },
  201         { PCI_VENDOR_DLINK,             PCI_PRODUCT_DLINK_DGE530T_B1 },
  202         { PCI_VENDOR_LINKSYS,           PCI_PRODUCT_LINKSYS_EG1064 },
  203         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON },
  204         { PCI_VENDOR_MARVELL,           PCI_PRODUCT_MARVELL_YUKON_BELKIN },
  205         { PCI_VENDOR_SCHNEIDERKOCH,     PCI_PRODUCT_SCHNEIDERKOCH_SK98XX },
  206         { PCI_VENDOR_SCHNEIDERKOCH,     PCI_PRODUCT_SCHNEIDERKOCH_SK98XX2 },
  207 };
  209 #define SK_LINKSYS_EG1032_SUBID 0x00151737
  211 static inline u_int32_t
sk_win_read_4(struct sk_softc *sc, u_int32_t reg)
  213 {
  214         return CSR_READ_4(sc, reg);
  215 }
  217 static inline u_int16_t
sk_win_read_2(struct sk_softc *sc, u_int32_t reg)
  219 {
  220         return CSR_READ_2(sc, reg);
  221 }
  223 static inline u_int8_t
sk_win_read_1(struct sk_softc *sc, u_int32_t reg)
  225 {
  226         return CSR_READ_1(sc, reg);
  227 }
  229 static inline void
sk_win_write_4(struct sk_softc *sc, u_int32_t reg, u_int32_t x)
  231 {
CSR_WRITE_4(sc, reg, x);
  233 }
  235 static inline void
sk_win_write_2(struct sk_softc *sc, u_int32_t reg, u_int16_t x)
  237 {
CSR_WRITE_2(sc, reg, x);
  239 }
  241 static inline void
sk_win_write_1(struct sk_softc *sc, u_int32_t reg, u_int8_t x)
  243 {
CSR_WRITE_1(sc, reg, x);
  245 }
  247 int
sk_xmac_miibus_readreg(struct device *dev, int phy, int reg)
  249 {
  250         struct sk_if_softc *sc_if = (struct sk_if_softc *)dev;
  251         int i;
DPRINTFN(9, ("sk_xmac_miibus_readreg\n"));
  255         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC && phy != 0)
  256                 return (0);
SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
SK_XM_READ_2(sc_if, XM_PHY_DATA);
  260         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
  261                 for (i = 0; i < SK_TIMEOUT; i++) {
DELAY(1);
  263                         if (SK_XM_READ_2(sc_if, XM_MMUCMD) &
XM_MMUCMD_PHYDATARDY)
  265                                 break;
  266                 }
  268                 if (i == SK_TIMEOUT) {
printf("%s: phy failed to come ready\n",
sc_if->sk_dev.dv_xname);
  271                         return (0);
  272                 }
  273         }
DELAY(1);
  275         return (SK_XM_READ_2(sc_if, XM_PHY_DATA));
  276 }
  278 void
sk_xmac_miibus_writereg(struct device *dev, int phy, int reg, int val)
  280 {
  281         struct sk_if_softc *sc_if = (struct sk_if_softc *)dev;
  282         int i;
DPRINTFN(9, ("sk_xmac_miibus_writereg\n"));
SK_XM_WRITE_2(sc_if, XM_PHY_ADDR, reg|(phy << 8));
  287         for (i = 0; i < SK_TIMEOUT; i++) {
  288                 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
  289                         break;
  290         }
  292         if (i == SK_TIMEOUT) {
printf("%s: phy failed to come ready\n",
sc_if->sk_dev.dv_xname);
  295                 return;
  296         }
SK_XM_WRITE_2(sc_if, XM_PHY_DATA, val);
  299         for (i = 0; i < SK_TIMEOUT; i++) {
DELAY(1);
  301                 if (!(SK_XM_READ_2(sc_if, XM_MMUCMD) & XM_MMUCMD_PHYBUSY))
  302                         break;
  303         }
  305         if (i == SK_TIMEOUT)
printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname);
  307 }
  309 void
sk_xmac_miibus_statchg(struct device *dev)
  311 {
  312         struct sk_if_softc *sc_if = (struct sk_if_softc *)dev;
  313         struct mii_data *mii = &sc_if->sk_mii;
DPRINTFN(9, ("sk_xmac_miibus_statchg\n"));
  317         /*
  318          * If this is a GMII PHY, manually set the XMAC's
  319          * duplex mode accordingly.
  320          */
  321         if (sc_if->sk_phytype != SK_PHYTYPE_XMAC) {
  322                 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
  324                 else
SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_GMIIFDX);
  326         }
  327 }
  329 int
sk_marv_miibus_readreg(struct device *dev, int phy, int reg)
  331 {
  332         struct sk_if_softc *sc_if = (struct sk_if_softc *)dev;
u_int16_t val;
  334         int i;
  336         if (phy != 0 ||
  337             (sc_if->sk_phytype != SK_PHYTYPE_MARV_COPPER &&
sc_if->sk_phytype != SK_PHYTYPE_MARV_FIBER)) {
DPRINTFN(9, ("sk_marv_miibus_readreg (skip) phy=%d, reg=%#x\n",
phy, reg));
  341                 return (0);
  342         }
SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
YU_SMICR_REGAD(reg) | YU_SMICR_OP_READ);
  347         for (i = 0; i < SK_TIMEOUT; i++) {
DELAY(1);
val = SK_YU_READ_2(sc_if, YUKON_SMICR);
  350                 if (val & YU_SMICR_READ_VALID)
  351                         break;
  352         }
  354         if (i == SK_TIMEOUT) {
printf("%s: phy failed to come ready\n",
sc_if->sk_dev.dv_xname);
  357                 return (0);
  358         }
DPRINTFN(9, ("sk_marv_miibus_readreg: i=%d, timeout=%d\n", i,
SK_TIMEOUT));
val = SK_YU_READ_2(sc_if, YUKON_SMIDR);
DPRINTFN(9, ("sk_marv_miibus_readreg phy=%d, reg=%#x, val=%#x\n",
phy, reg, val));
  368         return (val);
  369 }
  371 void
sk_marv_miibus_writereg(struct device *dev, int phy, int reg, int val)
  373 {
  374         struct sk_if_softc *sc_if = (struct sk_if_softc *)dev;
  375         int i;
DPRINTFN(9, ("sk_marv_miibus_writereg phy=%d reg=%#x val=%#x\n",
phy, reg, val));
SK_YU_WRITE_2(sc_if, YUKON_SMIDR, val);
SK_YU_WRITE_2(sc_if, YUKON_SMICR, YU_SMICR_PHYAD(phy) |
YU_SMICR_REGAD(reg) | YU_SMICR_OP_WRITE);
  384         for (i = 0; i < SK_TIMEOUT; i++) {
DELAY(1);
  386                 if (!(SK_YU_READ_2(sc_if, YUKON_SMICR) & YU_SMICR_BUSY))
  387                         break;
  388         }
  390         if (i == SK_TIMEOUT)
printf("%s: phy write timed out\n", sc_if->sk_dev.dv_xname);
  392 }
  394 void
sk_marv_miibus_statchg(struct device *dev)
  396 {
DPRINTFN(9, ("sk_marv_miibus_statchg: gpcr=%x\n",
SK_YU_READ_2(((struct sk_if_softc *)dev), YUKON_GPCR)));
  399 }
u_int32_t
sk_xmac_hash(caddr_t addr)
  403 {
u_int32_t crc;
crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
  407         return (~crc & ((1 << SK_HASH_BITS) - 1));
  408 }
u_int32_t
sk_yukon_hash(caddr_t addr)
  412 {
u_int32_t crc;
crc = ether_crc32_be(addr, ETHER_ADDR_LEN);
  416         return (crc & ((1 << SK_HASH_BITS) - 1));
  417 }
  419 void
sk_setfilt(struct sk_if_softc *sc_if, caddr_t addr, int slot)
  421 {
  422         int base = XM_RXFILT_ENTRY(slot);
SK_XM_WRITE_2(sc_if, base, letoh16(*(u_int16_t *)(&addr[0])));
SK_XM_WRITE_2(sc_if, base + 2, letoh16(*(u_int16_t *)(&addr[2])));
SK_XM_WRITE_2(sc_if, base + 4, letoh16(*(u_int16_t *)(&addr[4])));
  427 }
  429 void
sk_setmulti(struct sk_if_softc *sc_if)
  431 {
  432         struct sk_softc *sc = sc_if->sk_softc;
  433         struct ifnet *ifp= &sc_if->arpcom.ac_if;
u_int32_t hashes[2] = { 0, 0 };
  435         int h, i;
  436         struct arpcom *ac = &sc_if->arpcom;
  437         struct ether_multi *enm;
  438         struct ether_multistep step;
u_int8_t dummy[] = { 0, 0, 0, 0, 0 ,0 };
  441         /* First, zot all the existing filters. */
  442         switch(sc->sk_type) {
  443         case SK_GENESIS:
  444                 for (i = 1; i < XM_RXFILT_MAX; i++)
sk_setfilt(sc_if, (caddr_t)&dummy, i);
SK_XM_WRITE_4(sc_if, XM_MAR0, 0);
SK_XM_WRITE_4(sc_if, XM_MAR2, 0);
  449                 break;
  450         case SK_YUKON:
  451         case SK_YUKON_LITE:
  452         case SK_YUKON_LP:
SK_YU_WRITE_2(sc_if, YUKON_MCAH1, 0);
SK_YU_WRITE_2(sc_if, YUKON_MCAH2, 0);
SK_YU_WRITE_2(sc_if, YUKON_MCAH3, 0);
SK_YU_WRITE_2(sc_if, YUKON_MCAH4, 0);
  457                 break;
  458         }
  460         /* Now program new ones. */
allmulti:
  462         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
hashes[0] = 0xFFFFFFFF;
hashes[1] = 0xFFFFFFFF;
  465         } else {
i = 1;
  467                 /* First find the tail of the list. */
ETHER_FIRST_MULTI(step, ac, enm);
  469                 while (enm != NULL) {
  470                         if (bcmp(enm->enm_addrlo, enm->enm_addrhi,
ETHER_ADDR_LEN)) {
ifp->if_flags |= IFF_ALLMULTI;
  473                                 goto allmulti;
  474                         }
  475                         /*
  476                          * Program the first XM_RXFILT_MAX multicast groups
  477                          * into the perfect filter. For all others,
  478                          * use the hash table.
  479                          */
  480                         if (SK_IS_GENESIS(sc) && i < XM_RXFILT_MAX) {
sk_setfilt(sc_if, enm->enm_addrlo, i);
i++;
  483                         }
  484                         else {
  485                                 switch(sc->sk_type) {
  486                                 case SK_GENESIS:
h = sk_xmac_hash(enm->enm_addrlo);
  488                                         break;
  490                                 case SK_YUKON:
  491                                 case SK_YUKON_LITE:
  492                                 case SK_YUKON_LP:
h = sk_yukon_hash(enm->enm_addrlo);
  494                                         break;
  495                                 }
  496                                 if (h < 32)
hashes[0] |= (1 << h);
  498                                 else
hashes[1] |= (1 << (h - 32));
  500                         }
ETHER_NEXT_MULTI(step, enm);
  503                 }
  504         }
  506         switch(sc->sk_type) {
  507         case SK_GENESIS:
SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_HASH|
XM_MODE_RX_USE_PERFECT);
SK_XM_WRITE_4(sc_if, XM_MAR0, hashes[0]);
SK_XM_WRITE_4(sc_if, XM_MAR2, hashes[1]);
  512                 break;
  513         case SK_YUKON:
  514         case SK_YUKON_LITE:
  515         case SK_YUKON_LP:
SK_YU_WRITE_2(sc_if, YUKON_MCAH1, hashes[0] & 0xffff);
SK_YU_WRITE_2(sc_if, YUKON_MCAH2, (hashes[0] >> 16) & 0xffff);
SK_YU_WRITE_2(sc_if, YUKON_MCAH3, hashes[1] & 0xffff);
SK_YU_WRITE_2(sc_if, YUKON_MCAH4, (hashes[1] >> 16) & 0xffff);
  520                 break;
  521         }
  522 }
  524 void
sk_setpromisc(struct sk_if_softc *sc_if)
  526 {
  527         struct sk_softc *sc = sc_if->sk_softc;
  528         struct ifnet *ifp= &sc_if->arpcom.ac_if;
  530         switch(sc->sk_type) {
  531         case SK_GENESIS:
  532                 if (ifp->if_flags & IFF_PROMISC)
SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
  534                 else
SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_PROMISC);
  536                 break;
  537         case SK_YUKON:
  538         case SK_YUKON_LITE:
  539         case SK_YUKON_LP:
  540                 if (ifp->if_flags & IFF_PROMISC) {
SK_YU_CLRBIT_2(sc_if, YUKON_RCR,
YU_RCR_UFLEN | YU_RCR_MUFLEN);
  543                 } else {
SK_YU_SETBIT_2(sc_if, YUKON_RCR,
YU_RCR_UFLEN | YU_RCR_MUFLEN);
  546                 }
  547                 break;
  548         }
  549 }
  551 int
sk_init_rx_ring(struct sk_if_softc *sc_if)
  553 {
  554         struct sk_chain_data    *cd = &sc_if->sk_cdata;
  555         struct sk_ring_data     *rd = sc_if->sk_rdata;
  556         int                     i, nexti;
bzero((char *)rd->sk_rx_ring,
  559             sizeof(struct sk_rx_desc) * SK_RX_RING_CNT);
  561         for (i = 0; i < SK_RX_RING_CNT; i++) {
cd->sk_rx_chain[i].sk_desc = &rd->sk_rx_ring[i];
  563                 if (i == (SK_RX_RING_CNT - 1))
nexti = 0;
  565                 else
nexti = i + 1;
cd->sk_rx_chain[i].sk_next = &cd->sk_rx_chain[nexti];
rd->sk_rx_ring[i].sk_next = htole32(SK_RX_RING_ADDR(sc_if, nexti));
rd->sk_rx_ring[i].sk_csum1_start = htole16(ETHER_HDR_LEN);
rd->sk_rx_ring[i].sk_csum2_start = htole16(ETHER_HDR_LEN +
  571                     sizeof(struct ip));
  572         }
  574         for (i = 0; i < SK_RX_RING_CNT; i++) {
  575                 if (sk_newbuf(sc_if, i, NULL,
sc_if->sk_cdata.sk_rx_jumbo_map) == ENOBUFS) {
printf("%s: failed alloc of %dth mbuf\n",
sc_if->sk_dev.dv_xname, i);
  579                         return (ENOBUFS);
  580                 }
  581         }
sc_if->sk_cdata.sk_rx_prod = 0;
sc_if->sk_cdata.sk_rx_cons = 0;
  586         return (0);
  587 }
  589 int
sk_init_tx_ring(struct sk_if_softc *sc_if)
  591 {
  592         struct sk_softc         *sc = sc_if->sk_softc;
  593         struct sk_chain_data    *cd = &sc_if->sk_cdata;
  594         struct sk_ring_data     *rd = sc_if->sk_rdata;
bus_dmamap_t            dmamap;
  596         struct sk_txmap_entry   *entry;
  597         int                     i, nexti;
bzero((char *)sc_if->sk_rdata->sk_tx_ring,
  600             sizeof(struct sk_tx_desc) * SK_TX_RING_CNT);
SIMPLEQ_INIT(&sc_if->sk_txmap_head);
  603         for (i = 0; i < SK_TX_RING_CNT; i++) {
cd->sk_tx_chain[i].sk_desc = &rd->sk_tx_ring[i];
  605                 if (i == (SK_TX_RING_CNT - 1))
nexti = 0;
  607                 else
nexti = i + 1;
cd->sk_tx_chain[i].sk_next = &cd->sk_tx_chain[nexti];
rd->sk_tx_ring[i].sk_next = htole32(SK_TX_RING_ADDR(sc_if, nexti));
  612                 if (bus_dmamap_create(sc->sc_dmatag, SK_JLEN, SK_NTXSEG,
SK_JLEN, 0, BUS_DMA_NOWAIT, &dmamap))
  614                         return (ENOBUFS);
entry = malloc(sizeof(*entry), M_DEVBUF, M_NOWAIT);
  617                 if (!entry) {
bus_dmamap_destroy(sc->sc_dmatag, dmamap);
  619                         return (ENOBUFS);
  620                 }
entry->dmamap = dmamap;
SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head, entry, link);
  623         }
sc_if->sk_cdata.sk_tx_prod = 0;
sc_if->sk_cdata.sk_tx_cons = 0;
sc_if->sk_cdata.sk_tx_cnt = 0;
SK_CDTXSYNC(sc_if, 0, SK_TX_RING_CNT,
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
  632         return (0);
  633 }
  635 int
sk_newbuf(struct sk_if_softc *sc_if, int i, struct mbuf *m,
bus_dmamap_t dmamap)
  638 {
  639         struct mbuf             *m_new = NULL;
  640         struct sk_chain         *c;
  641         struct sk_rx_desc       *r;
  643         if (m == NULL) {
caddr_t buf = NULL;
MGETHDR(m_new, M_DONTWAIT, MT_DATA);
  647                 if (m_new == NULL)
  648                         return (ENOBUFS);
  650                 /* Allocate the jumbo buffer */
buf = sk_jalloc(sc_if);
  652                 if (buf == NULL) {
m_freem(m_new);
DPRINTFN(1, ("%s jumbo allocation failed -- packet "
  655                             "dropped!\n", sc_if->arpcom.ac_if.if_xname));
  656                         return (ENOBUFS);
  657                 }
  659                 /* Attach the buffer to the mbuf */
m_new->m_len = m_new->m_pkthdr.len = SK_JLEN;
MEXTADD(m_new, buf, SK_JLEN, 0, sk_jfree, sc_if);
  662         } else {
  663                 /*
  664                  * We're re-using a previously allocated mbuf;
  665                  * be sure to re-init pointers and lengths to
  666                  * default values.
  667                  */
m_new = m;
m_new->m_len = m_new->m_pkthdr.len = SK_JLEN;
m_new->m_data = m_new->m_ext.ext_buf;
  671         }
m_adj(m_new, ETHER_ALIGN);
c = &sc_if->sk_cdata.sk_rx_chain[i];
r = c->sk_desc;
c->sk_mbuf = m_new;
r->sk_data_lo = htole32(dmamap->dm_segs[0].ds_addr +
  678             (((vaddr_t)m_new->m_data
  679              - (vaddr_t)sc_if->sk_cdata.sk_jumbo_buf)));
r->sk_ctl = htole32(SK_JLEN | SK_RXSTAT);
SK_CDRXSYNC(sc_if, i, BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
  684         return (0);
  685 }
  687 /*
  688  * Memory management for jumbo frames.
  689  */
  691 int
sk_alloc_jumbo_mem(struct sk_if_softc *sc_if)
  693 {
  694         struct sk_softc         *sc = sc_if->sk_softc;
caddr_t                 ptr, kva;
bus_dma_segment_t       seg;
  697         int             i, rseg, state, error;
  698         struct sk_jpool_entry   *entry;
state = error = 0;
  702         /* Grab a big chunk o' storage. */
  703         if (bus_dmamem_alloc(sc->sc_dmatag, SK_JMEM, PAGE_SIZE, 0,
  704                              &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
printf(": can't alloc rx buffers");
  706                 return (ENOBUFS);
  707         }
state = 1;
  710         if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg, SK_JMEM, &kva,
BUS_DMA_NOWAIT)) {
printf(": can't map dma buffers (%d bytes)", SK_JMEM);
error = ENOBUFS;
  714                 goto out;
  715         }
state = 2;
  718         if (bus_dmamap_create(sc->sc_dmatag, SK_JMEM, 1, SK_JMEM, 0,
BUS_DMA_NOWAIT, &sc_if->sk_cdata.sk_rx_jumbo_map)) {
printf(": can't create dma map");
error = ENOBUFS;
  722                 goto out;
  723         }
state = 3;
  726         if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_cdata.sk_rx_jumbo_map,
kva, SK_JMEM, NULL, BUS_DMA_NOWAIT)) {
printf(": can't load dma map");
error = ENOBUFS;
  730                 goto out;
  731         }
state = 4;
sc_if->sk_cdata.sk_jumbo_buf = (caddr_t)kva;
DPRINTFN(1,("sk_jumbo_buf = 0x%08X\n", sc_if->sk_cdata.sk_jumbo_buf));
LIST_INIT(&sc_if->sk_jfree_listhead);
LIST_INIT(&sc_if->sk_jinuse_listhead);
  740         /*
  741          * Now divide it up into 9K pieces and save the addresses
  742          * in an array.
  743          */
ptr = sc_if->sk_cdata.sk_jumbo_buf;
  745         for (i = 0; i < SK_JSLOTS; i++) {
sc_if->sk_cdata.sk_jslots[i] = ptr;
ptr += SK_JLEN;
entry = malloc(sizeof(struct sk_jpool_entry),
M_DEVBUF, M_NOWAIT);
  750                 if (entry == NULL) {
sc_if->sk_cdata.sk_jumbo_buf = NULL;
printf(": no memory for jumbo buffer queue!");
error = ENOBUFS;
  754                         goto out;
  755                 }
entry->slot = i;
LIST_INSERT_HEAD(&sc_if->sk_jfree_listhead,
entry, jpool_entries);
  759         }
out:
  761         if (error != 0) {
  762                 switch (state) {
  763                 case 4:
bus_dmamap_unload(sc->sc_dmatag,
sc_if->sk_cdata.sk_rx_jumbo_map);
  766                 case 3:
bus_dmamap_destroy(sc->sc_dmatag,
sc_if->sk_cdata.sk_rx_jumbo_map);
  769                 case 2:
bus_dmamem_unmap(sc->sc_dmatag, kva, SK_JMEM);
  771                 case 1:
bus_dmamem_free(sc->sc_dmatag, &seg, rseg);
  773                         break;
  774                 default:
  775                         break;
  776                 }
  777         }
  779         return (error);
  780 }
  782 /*
  783  * Allocate a jumbo buffer.
  784  */
  785 void *
sk_jalloc(struct sk_if_softc *sc_if)
  787 {
  788         struct sk_jpool_entry   *entry;
entry = LIST_FIRST(&sc_if->sk_jfree_listhead);
  792         if (entry == NULL)
  793                 return (NULL);
LIST_REMOVE(entry, jpool_entries);
LIST_INSERT_HEAD(&sc_if->sk_jinuse_listhead, entry, jpool_entries);
  797         return (sc_if->sk_cdata.sk_jslots[entry->slot]);
  798 }
  800 /*
  801  * Release a jumbo buffer.
  802  */
  803 void
sk_jfree(caddr_t buf, u_int size, void  *arg)
  805 {
  806         struct sk_jpool_entry *entry;
  807         struct sk_if_softc *sc;
  808         int i;
  810         /* Extract the softc struct pointer. */
sc = (struct sk_if_softc *)arg;
  813         if (sc == NULL)
panic("sk_jfree: can't find softc pointer!");
  816         /* calculate the slot this buffer belongs to */
i = ((vaddr_t)buf
  818              - (vaddr_t)sc->sk_cdata.sk_jumbo_buf) / SK_JLEN;
  820         if ((i < 0) || (i >= SK_JSLOTS))
panic("sk_jfree: asked to free buffer that we don't manage!");
entry = LIST_FIRST(&sc->sk_jinuse_listhead);
  824         if (entry == NULL)
panic("sk_jfree: buffer not in use!");
entry->slot = i;
LIST_REMOVE(entry, jpool_entries);
LIST_INSERT_HEAD(&sc->sk_jfree_listhead, entry, jpool_entries);
  829 }
  831 /*
  832  * Set media options.
  833  */
  834 int
sk_ifmedia_upd(struct ifnet *ifp)
  836 {
  837         struct sk_if_softc *sc_if = ifp->if_softc;
mii_mediachg(&sc_if->sk_mii);
  840         return (0);
  841 }
  843 /*
  844  * Report current media status.
  845  */
  846 void
sk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
  848 {
  849         struct sk_if_softc *sc_if = ifp->if_softc;
mii_pollstat(&sc_if->sk_mii);
ifmr->ifm_active = sc_if->sk_mii.mii_media_active;
ifmr->ifm_status = sc_if->sk_mii.mii_media_status;
  854 }
  856 int
sk_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
  858 {
  859         struct sk_if_softc *sc_if = ifp->if_softc;
  860         struct ifreq *ifr = (struct ifreq *) data;
  861         struct ifaddr *ifa = (struct ifaddr *) data;
  862         struct mii_data *mii;
  863         int s, error = 0;
s = splnet();
  867         if ((error = ether_ioctl(ifp, &sc_if->arpcom, command, data)) > 0) {
splx(s);
  869                 return (error);
  870         }
  872         switch(command) {
  873         case SIOCSIFADDR:
ifp->if_flags |= IFF_UP;
  875                 if (!(ifp->if_flags & IFF_RUNNING))
sk_init(sc_if);
  877 #ifdef INET
  878                 if (ifa->ifa_addr->sa_family == AF_INET)
arp_ifinit(&sc_if->arpcom, ifa);
  880 #endif /* INET */
  881                 break;
  882         case SIOCSIFMTU:
  883                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ifp->if_hardmtu)
error = EINVAL;
  885                 else if (ifp->if_mtu != ifr->ifr_mtu)
ifp->if_mtu = ifr->ifr_mtu;
  887                 break;
  888         case SIOCSIFFLAGS:
  889                 if (ifp->if_flags & IFF_UP) {
  890                         if (ifp->if_flags & IFF_RUNNING &&
  891                             (ifp->if_flags ^ sc_if->sk_if_flags)
  892                              & IFF_PROMISC) {
sk_setpromisc(sc_if);
sk_setmulti(sc_if);
  895                         } else {
  896                                 if (!(ifp->if_flags & IFF_RUNNING))
sk_init(sc_if);
  898                         }
  899                 } else {
  900                         if (ifp->if_flags & IFF_RUNNING)
sk_stop(sc_if);
  902                 }
sc_if->sk_if_flags = ifp->if_flags;
  904                 break;
  905         case SIOCADDMULTI:
  906         case SIOCDELMULTI:
error = (command == SIOCADDMULTI) ?
ether_addmulti(ifr, &sc_if->arpcom) :
ether_delmulti(ifr, &sc_if->arpcom);
  911                 if (error == ENETRESET) {
  912                         /*
  913                          * Multicast list has changed; set the hardware
  914                          * filter accordingly.
  915                          */
  916                         if (ifp->if_flags & IFF_RUNNING)
sk_setmulti(sc_if);
error = 0;
  919                 }
  920                 break;
  921         case SIOCGIFMEDIA:
  922         case SIOCSIFMEDIA:
mii = &sc_if->sk_mii;
error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
  925                 break;
  926         default:
error = ENOTTY;
  928                 break;
  929         }
splx(s);
  933         return (error);
  934 }
  936 /*
  937  * Probe for a SysKonnect GEnesis chip. Check the PCI vendor and device
  938  * IDs against our list and return a device name if we find a match.
  939  */
  940 int
skc_probe(struct device *parent, void *match, void *aux)
  942 {
  943         struct pci_attach_args *pa = aux;
pci_chipset_tag_t pc = pa->pa_pc;
pcireg_t subid;
subid = pci_conf_read(pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
  949         if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS &&
PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 &&
subid == SK_LINKSYS_EG1032_SUBID)
  952                 return (1);
  954         return (pci_matchbyid((struct pci_attach_args *)aux, skc_devices,
  955             sizeof(skc_devices)/sizeof(skc_devices[0])));
  956 }
  958 /*
  959  * Force the GEnesis into reset, then bring it out of reset.
  960  */
  961 void
sk_reset(struct sk_softc *sc)
  963 {
u_int32_t imtimer_ticks;
DPRINTFN(2, ("sk_reset\n"));
CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET);
CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET);
  970         if (SK_IS_YUKON(sc))
CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET);
DELAY(1000);
CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET);
DELAY(2);
CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET);
  977         if (SK_IS_YUKON(sc))
CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR);
DPRINTFN(2, ("sk_reset: sk_csr=%x\n", CSR_READ_2(sc, SK_CSR)));
DPRINTFN(2, ("sk_reset: sk_link_ctrl=%x\n",
CSR_READ_2(sc, SK_LINK_CTRL)));
  984         if (SK_IS_GENESIS(sc)) {
  985                 /* Configure packet arbiter */
sk_win_write_2(sc, SK_PKTARB_CTL, SK_PKTARBCTL_UNRESET);
sk_win_write_2(sc, SK_RXPA1_TINIT, SK_PKTARB_TIMEOUT);
sk_win_write_2(sc, SK_TXPA1_TINIT, SK_PKTARB_TIMEOUT);
sk_win_write_2(sc, SK_RXPA2_TINIT, SK_PKTARB_TIMEOUT);
sk_win_write_2(sc, SK_TXPA2_TINIT, SK_PKTARB_TIMEOUT);
  991         }
  993         /* Enable RAM interface */
sk_win_write_4(sc, SK_RAMCTL, SK_RAMCTL_UNRESET);
  996         /*
  997          * Configure interrupt moderation. The moderation timer
  998          * defers interrupts specified in the interrupt moderation
  999          * timer mask based on the timeout specified in the interrupt
 1000          * moderation timer init register. Each bit in the timer
 1001          * register represents one tick, so to specify a timeout in
 1002          * microseconds, we have to multiply by the correct number of
 1003          * ticks-per-microsecond.
 1004          */
 1005         switch (sc->sk_type) {
 1006         case SK_GENESIS:
imtimer_ticks = SK_IMTIMER_TICKS_GENESIS;
 1008                 break;
 1009         default:
imtimer_ticks = SK_IMTIMER_TICKS_YUKON;
 1011         }
sk_win_write_4(sc, SK_IMTIMERINIT, SK_IM_USECS(100));
sk_win_write_4(sc, SK_IMMR, SK_ISR_TX1_S_EOF|SK_ISR_TX2_S_EOF|
SK_ISR_RX1_EOF|SK_ISR_RX2_EOF);
sk_win_write_1(sc, SK_IMTIMERCTL, SK_IMCTL_START);
 1016 }
 1018 int
sk_probe(struct device *parent, void *match, void *aux)
 1020 {
 1021         struct skc_attach_args *sa = aux;
 1023         if (sa->skc_port != SK_PORT_A && sa->skc_port != SK_PORT_B)
 1024                 return (0);
 1026         switch (sa->skc_type) {
 1027         case SK_GENESIS:
 1028         case SK_YUKON:
 1029         case SK_YUKON_LITE:
 1030         case SK_YUKON_LP:
 1031                 return (1);
 1032         }
 1034         return (0);
 1035 }
 1037 /*
 1038  * Each XMAC chip is attached as a separate logical IP interface.
 1039  * Single port cards will have only one logical interface of course.
 1040  */
 1041 void
sk_attach(struct device *parent, struct device *self, void *aux)
 1043 {
 1044         struct sk_if_softc *sc_if = (struct sk_if_softc *) self;
 1045         struct sk_softc *sc = (struct sk_softc *)parent;
 1046         struct skc_attach_args *sa = aux;
 1047         struct ifnet *ifp;
caddr_t kva;
bus_dma_segment_t seg;
 1050         int i, rseg;
sc_if->sk_port = sa->skc_port;
sc_if->sk_softc = sc;
sc->sk_if[sa->skc_port] = sc_if;
 1056         if (sa->skc_port == SK_PORT_A)
sc_if->sk_tx_bmu = SK_BMU_TXS_CSR0;
 1058         if (sa->skc_port == SK_PORT_B)
sc_if->sk_tx_bmu = SK_BMU_TXS_CSR1;
DPRINTFN(2, ("begin sk_attach: port=%d\n", sc_if->sk_port));
 1063         /*
 1064          * Get station address for this interface. Note that
 1065          * dual port cards actually come with three station
 1066          * addresses: one for each port, plus an extra. The
 1067          * extra one is used by the SysKonnect driver software
 1068          * as a 'virtual' station address for when both ports
 1069          * are operating in failover mode. Currently we don't
 1070          * use this extra address.
 1071          */
 1072         for (i = 0; i < ETHER_ADDR_LEN; i++)
sc_if->arpcom.ac_enaddr[i] =
sk_win_read_1(sc, SK_MAC0_0 + (sa->skc_port * 8) + i);
printf(": address %s\n",
ether_sprintf(sc_if->arpcom.ac_enaddr));
 1079         /*
 1080          * Set up RAM buffer addresses. The NIC will have a certain
 1081          * amount of SRAM on it, somewhere between 512K and 2MB. We
 1082          * need to divide this up a) between the transmitter and
 1083          * receiver and b) between the two XMACs, if this is a
 1084          * dual port NIC. Our algorithm is to divide up the memory
 1085          * evenly so that everyone gets a fair share.
 1086          */
 1087         if (sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC) {
u_int32_t               chunk, val;
chunk = sc->sk_ramsize / 2;
val = sc->sk_rboff / sizeof(u_int64_t);
sc_if->sk_rx_ramstart = val;
val += (chunk / sizeof(u_int64_t));
sc_if->sk_rx_ramend = val - 1;
sc_if->sk_tx_ramstart = val;
val += (chunk / sizeof(u_int64_t));
sc_if->sk_tx_ramend = val - 1;
 1098         } else {
u_int32_t               chunk, val;
chunk = sc->sk_ramsize / 4;
val = (sc->sk_rboff + (chunk * 2 * sc_if->sk_port)) /
 1103                     sizeof(u_int64_t);
sc_if->sk_rx_ramstart = val;
val += (chunk / sizeof(u_int64_t));
sc_if->sk_rx_ramend = val - 1;
sc_if->sk_tx_ramstart = val;
val += (chunk / sizeof(u_int64_t));
sc_if->sk_tx_ramend = val - 1;
 1110         }
DPRINTFN(2, ("sk_attach: rx_ramstart=%#x rx_ramend=%#x\n"
 1113                      "           tx_ramstart=%#x tx_ramend=%#x\n",
sc_if->sk_rx_ramstart, sc_if->sk_rx_ramend,
sc_if->sk_tx_ramstart, sc_if->sk_tx_ramend));
 1117         /* Read and save PHY type */
sc_if->sk_phytype = sk_win_read_1(sc, SK_EPROM1) & 0xF;
 1120         /* Set PHY address */
 1121         if (SK_IS_GENESIS(sc)) {
 1122                 switch (sc_if->sk_phytype) {
 1123                         case SK_PHYTYPE_XMAC:
sc_if->sk_phyaddr = SK_PHYADDR_XMAC;
 1125                                 break;
 1126                         case SK_PHYTYPE_BCOM:
sc_if->sk_phyaddr = SK_PHYADDR_BCOM;
 1128                                 break;
 1129                         default:
printf("%s: unsupported PHY type: %d\n",
sc->sk_dev.dv_xname, sc_if->sk_phytype);
 1132                                 return;
 1133                 }
 1134         }
 1136         if (SK_IS_YUKON(sc)) {
 1137                 if ((sc_if->sk_phytype < SK_PHYTYPE_MARV_COPPER &&
sc->sk_pmd != 'L' && sc->sk_pmd != 'S')) {
 1139                         /* not initialized, punt */
sc_if->sk_phytype = SK_PHYTYPE_MARV_COPPER;
sc->sk_coppertype = 1;
 1143                 }
sc_if->sk_phyaddr = SK_PHYADDR_MARV;
 1147                 if (!(sc->sk_coppertype))
sc_if->sk_phytype = SK_PHYTYPE_MARV_FIBER;
 1149         }
 1151         /* Allocate the descriptor queues. */
 1152         if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct sk_ring_data),
PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
printf(": can't alloc rx buffers\n");
 1155                 goto fail;
 1156         }
 1157         if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg,
 1158             sizeof(struct sk_ring_data), &kva, BUS_DMA_NOWAIT)) {
printf(": can't map dma buffers (%lu bytes)\n",
 1160                        (ulong)sizeof(struct sk_ring_data));
 1161                 goto fail_1;
 1162         }
 1163         if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct sk_ring_data), 1,
 1164             sizeof(struct sk_ring_data), 0, BUS_DMA_NOWAIT,
 1165             &sc_if->sk_ring_map)) {
printf(": can't create dma map\n");
 1167                 goto fail_2;
 1168         }
 1169         if (bus_dmamap_load(sc->sc_dmatag, sc_if->sk_ring_map, kva,
 1170             sizeof(struct sk_ring_data), NULL, BUS_DMA_NOWAIT)) {
printf(": can't load dma map\n");
 1172                 goto fail_3;
 1173         }
sc_if->sk_rdata = (struct sk_ring_data *)kva;
bzero(sc_if->sk_rdata, sizeof(struct sk_ring_data));
 1177         /* Try to allocate memory for jumbo buffers. */
 1178         if (sk_alloc_jumbo_mem(sc_if)) {
printf(": jumbo buffer allocation failed\n");
 1180                 goto fail_3;
 1181         }
ifp = &sc_if->arpcom.ac_if;
ifp->if_softc = sc_if;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_ioctl = sk_ioctl;
ifp->if_start = sk_start;
ifp->if_watchdog = sk_watchdog;
ifp->if_baudrate = 1000000000;
ifp->if_hardmtu = SK_JUMBO_MTU;
IFQ_SET_MAXLEN(&ifp->if_snd, SK_TX_RING_CNT - 1);
IFQ_SET_READY(&ifp->if_snd);
bcopy(sc_if->sk_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
ifp->if_capabilities = IFCAP_VLAN_MTU;
 1197         /*
 1198          * Do miibus setup.
 1199          */
 1200         switch (sc->sk_type) {
 1201         case SK_GENESIS:
sk_init_xmac(sc_if);
 1203                 break;
 1204         case SK_YUKON:
 1205         case SK_YUKON_LITE:
 1206         case SK_YUKON_LP:
sk_init_yukon(sc_if);
 1208                 break;
 1209         default:
printf(": unknown device type %d\n", sc->sk_type);
 1211                 /* dealloc jumbo on error */
 1212                 goto fail_3;
 1213         }
DPRINTFN(2, ("sk_attach: 1\n"));
sc_if->sk_mii.mii_ifp = ifp;
 1218         if (SK_IS_GENESIS(sc)) {
sc_if->sk_mii.mii_readreg = sk_xmac_miibus_readreg;
sc_if->sk_mii.mii_writereg = sk_xmac_miibus_writereg;
sc_if->sk_mii.mii_statchg = sk_xmac_miibus_statchg;
 1222         } else {
sc_if->sk_mii.mii_readreg = sk_marv_miibus_readreg;
sc_if->sk_mii.mii_writereg = sk_marv_miibus_writereg;
sc_if->sk_mii.mii_statchg = sk_marv_miibus_statchg;
 1226         }
ifmedia_init(&sc_if->sk_mii.mii_media, 0,
sk_ifmedia_upd, sk_ifmedia_sts);
 1230         if (SK_IS_GENESIS(sc)) {
mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY,
MII_OFFSET_ANY, 0);
 1233         } else {
mii_attach(self, &sc_if->sk_mii, 0xffffffff, MII_PHY_ANY,
MII_OFFSET_ANY, MIIF_DOPAUSE);
 1236         }
 1237         if (LIST_FIRST(&sc_if->sk_mii.mii_phys) == NULL) {
printf("%s: no PHY found!\n", sc_if->sk_dev.dv_xname);
ifmedia_add(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL,
 1240                             0, NULL);
ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_MANUAL);
 1242         } else
ifmedia_set(&sc_if->sk_mii.mii_media, IFM_ETHER|IFM_AUTO);
 1245         if (SK_IS_GENESIS(sc)) {
timeout_set(&sc_if->sk_tick_ch, sk_tick, sc_if);
timeout_add(&sc_if->sk_tick_ch, hz);
 1248         } else
timeout_set(&sc_if->sk_tick_ch, sk_yukon_tick, sc_if);
 1251         /*
 1252          * Call MI attach routines.
 1253          */
if_attach(ifp);
ether_ifattach(ifp);
shutdownhook_establish(skc_shutdown, sc);
DPRINTFN(2, ("sk_attach: end\n"));
 1260         return;
fail_3:
bus_dmamap_destroy(sc->sc_dmatag, sc_if->sk_ring_map);
fail_2:
bus_dmamem_unmap(sc->sc_dmatag, kva, sizeof(struct sk_ring_data));
fail_1:
bus_dmamem_free(sc->sc_dmatag, &seg, rseg);
fail:
sc->sk_if[sa->skc_port] = NULL;
 1270 }
 1272 int
skcprint(void *aux, const char *pnp)
 1274 {
 1275         struct skc_attach_args *sa = aux;
 1277         if (pnp)
printf("sk port %c at %s",
 1279                     (sa->skc_port == SK_PORT_A) ? 'A' : 'B', pnp);
 1280         else
printf(" port %c", (sa->skc_port == SK_PORT_A) ? 'A' : 'B');
 1282         return (UNCONF);
 1283 }
 1285 /*
 1286  * Attach the interface. Allocate softc structures, do ifmedia
 1287  * setup and ethernet/BPF attach.
 1288  */
 1289 void
skc_attach(struct device *parent, struct device *self, void *aux)
 1291 {
 1292         struct sk_softc *sc = (struct sk_softc *)self;
 1293         struct pci_attach_args *pa = aux;
 1294         struct skc_attach_args skca;
pci_chipset_tag_t pc = pa->pa_pc;
pcireg_t command, memtype;
pci_intr_handle_t ih;
 1298         const char *intrstr = NULL;
bus_size_t size;
u_int8_t skrs;
 1301         char *revstr = NULL;
DPRINTFN(2, ("begin skc_attach\n"));
 1305         /*
 1306          * Handle power management nonsense.
 1307          */
command = pci_conf_read(pc, pa->pa_tag, SK_PCI_CAPID) & 0x000000FF;
 1310         if (command == 0x01) {
command = pci_conf_read(pc, pa->pa_tag, SK_PCI_PWRMGMTCTRL);
 1312                 if (command & SK_PSTATE_MASK) {
u_int32_t               iobase, membase, irq;
 1315                         /* Save important PCI config data. */
iobase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOIO);
membase = pci_conf_read(pc, pa->pa_tag, SK_PCI_LOMEM);
irq = pci_conf_read(pc, pa->pa_tag, SK_PCI_INTLINE);
 1320                         /* Reset the power state. */
printf("%s chip is in D%d power mode "
 1322                             "-- setting to D0\n", sc->sk_dev.dv_xname,
command & SK_PSTATE_MASK);
command &= 0xFFFFFFFC;
pci_conf_write(pc, pa->pa_tag,
SK_PCI_PWRMGMTCTRL, command);
 1328                         /* Restore PCI config data. */
pci_conf_write(pc, pa->pa_tag, SK_PCI_LOIO, iobase);
pci_conf_write(pc, pa->pa_tag, SK_PCI_LOMEM, membase);
pci_conf_write(pc, pa->pa_tag, SK_PCI_INTLINE, irq);
 1332                 }
 1333         }
 1335         /*
 1336          * Map control/status registers.
 1337          */
memtype = pci_mapreg_type(pc, pa->pa_tag, SK_PCI_LOMEM);
 1340         switch (memtype) {
 1341         case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
 1342         case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
 1343                 if (pci_mapreg_map(pa, SK_PCI_LOMEM,
memtype, 0, &sc->sk_btag, &sc->sk_bhandle,
NULL, &size, 0) == 0)
 1346                         break;
 1347         default:
printf(": can't map mem space\n");
 1349                 return;
 1350         }
sc->sc_dmatag = pa->pa_dmat;
sc->sk_type = sk_win_read_1(sc, SK_CHIPVER);
sc->sk_rev = (sk_win_read_1(sc, SK_CONFIG) >> 4);
 1357         /* bail out here if chip is not recognized */
 1358         if (! SK_IS_GENESIS(sc) && ! SK_IS_YUKON(sc)) {
printf(": unknown chip type: %d\n", sc->sk_type);
 1360                 goto fail_1;
 1361         }
DPRINTFN(2, ("skc_attach: allocate interrupt\n"));
 1364         /* Allocate interrupt */
 1365         if (pci_intr_map(pa, &ih)) {
printf(": couldn't map interrupt\n");
 1367                 goto fail_1;
 1368         }
intrstr = pci_intr_string(pc, ih);
sc->sk_intrhand = pci_intr_establish(pc, ih, IPL_NET, sk_intr, sc,
self->dv_xname);
 1373         if (sc->sk_intrhand == NULL) {
printf(": couldn't establish interrupt");
 1375                 if (intrstr != NULL)
printf(" at %s", intrstr);
printf("\n");
 1378                 goto fail_1;
 1379         }
 1381         /* Reset the adapter. */
sk_reset(sc);
skrs = sk_win_read_1(sc, SK_EPROM0);
 1385         if (SK_IS_GENESIS(sc)) {
 1386                 /* Read and save RAM size and RAMbuffer offset */
 1387                 switch(skrs) {
 1388                 case SK_RAMSIZE_512K_64:
sc->sk_ramsize = 0x80000;
sc->sk_rboff = SK_RBOFF_0;
 1391                         break;
 1392                 case SK_RAMSIZE_1024K_64:
sc->sk_ramsize = 0x100000;
sc->sk_rboff = SK_RBOFF_80000;
 1395                         break;
 1396                 case SK_RAMSIZE_1024K_128:
sc->sk_ramsize = 0x100000;
sc->sk_rboff = SK_RBOFF_0;
 1399                         break;
 1400                 case SK_RAMSIZE_2048K_128:
sc->sk_ramsize = 0x200000;
sc->sk_rboff = SK_RBOFF_0;
 1403                         break;
 1404                 default:
printf(": unknown ram size: %d\n", skrs);
 1406                         goto fail_2;
 1407                         break;
 1408                 }
 1409         } else {
 1410                 if (skrs == 0x00)
sc->sk_ramsize = 0x20000;
 1412                 else
sc->sk_ramsize = skrs * (1<<12);
sc->sk_rboff = SK_RBOFF_0;
 1415         }
DPRINTFN(2, ("skc_attach: ramsize=%d (%dk), rboff=%d\n",
sc->sk_ramsize, sc->sk_ramsize / 1024,
sc->sk_rboff));
 1421         /* Read and save physical media type */
sc->sk_pmd = sk_win_read_1(sc, SK_PMDTYPE);
 1424         if (sc->sk_pmd == 'T' || sc->sk_pmd == '1')
sc->sk_coppertype = 1;
 1426         else
sc->sk_coppertype = 0;
 1429         switch (sc->sk_type) {
 1430         case SK_GENESIS:
sc->sk_name = "GEnesis";
 1432                 break;
 1433         case SK_YUKON:
sc->sk_name = "Yukon";
 1435                 break;
 1436         case SK_YUKON_LITE:
sc->sk_name = "Yukon Lite";
 1438                 break;
 1439         case SK_YUKON_LP:
sc->sk_name = "Yukon LP";
 1441                 break;
 1442         default:
sc->sk_name = "Yukon (Unknown)";
 1444         }
 1446         /* Yukon Lite Rev A0 needs special test, from sk98lin driver */
 1447         if (sc->sk_type == SK_YUKON || sc->sk_type == SK_YUKON_LP) {
u_int32_t flashaddr;
u_int8_t testbyte;
flashaddr = sk_win_read_4(sc, SK_EP_ADDR);
 1453                 /* test Flash-Address Register */
sk_win_write_1(sc, SK_EP_ADDR+3, 0xff);
testbyte = sk_win_read_1(sc, SK_EP_ADDR+3);
 1457                 if (testbyte != 0) {
 1458                         /* This is a Yukon Lite Rev A0 */
sc->sk_type = SK_YUKON_LITE;
sc->sk_rev = SK_YUKON_LITE_REV_A0;
 1461                         /* restore Flash-Address Register */
sk_win_write_4(sc, SK_EP_ADDR, flashaddr);
 1463                 }
 1464         }
 1466         if (sc->sk_type == SK_YUKON_LITE) {
 1467                 switch (sc->sk_rev) {
 1468                 case SK_YUKON_LITE_REV_A0:
revstr = "A0";
 1470                         break;
 1471                 case SK_YUKON_LITE_REV_A1:
revstr = "A1";
 1473                         break;
 1474                 case SK_YUKON_LITE_REV_A3:
revstr = "A3";
 1476                         break;
 1477                 default:
 1478                         ;
 1479                 }
 1480         }
 1482         /* Announce the product name. */
printf(", %s", sc->sk_name);
 1484         if (revstr != NULL)
printf(" rev. %s", revstr);
printf(" (0x%x): %s\n", sc->sk_rev, intrstr);
sc->sk_macs = 1;
 1490         if (!(sk_win_read_1(sc, SK_CONFIG) & SK_CONFIG_SINGLEMAC))
sc->sk_macs++;
skca.skc_port = SK_PORT_A;
skca.skc_type = sc->sk_type;
skca.skc_rev = sc->sk_rev;
 1496         (void)config_found(&sc->sk_dev, &skca, skcprint);
 1498         if (sc->sk_macs > 1) {
skca.skc_port = SK_PORT_B;
skca.skc_type = sc->sk_type;
skca.skc_rev = sc->sk_rev;
 1502                 (void)config_found(&sc->sk_dev, &skca, skcprint);
 1503         }
 1505         /* Turn on the 'driver is loaded' LED. */
CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON);
 1508         return;
fail_2:
pci_intr_disestablish(pc, sc->sk_intrhand);
fail_1:
bus_space_unmap(sc->sk_btag, sc->sk_bhandle, size);
 1514 }
 1516 int
sk_encap(struct sk_if_softc *sc_if, struct mbuf *m_head, u_int32_t *txidx)
 1518 {
 1519         struct sk_softc         *sc = sc_if->sk_softc;
 1520         struct sk_tx_desc       *f = NULL;
u_int32_t               frag, cur, sk_ctl;
 1522         int                     i;
 1523         struct sk_txmap_entry   *entry;
bus_dmamap_t            txmap;
DPRINTFN(2, ("sk_encap\n"));
entry = SIMPLEQ_FIRST(&sc_if->sk_txmap_head);
 1529         if (entry == NULL) {
DPRINTFN(2, ("sk_encap: no txmap available\n"));
 1531                 return (ENOBUFS);
 1532         }
txmap = entry->dmamap;
cur = frag = *txidx;
 1537 #ifdef SK_DEBUG
 1538         if (skdebug >= 2)
sk_dump_mbuf(m_head);
 1540 #endif
 1542         /*
 1543          * Start packing the mbufs in this chain into
 1544          * the fragment pointers. Stop when we run out
 1545          * of fragments or hit the end of the mbuf chain.
 1546          */
 1547         if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head,
BUS_DMA_NOWAIT)) {
DPRINTFN(2, ("sk_encap: dmamap failed\n"));
 1550                 return (ENOBUFS);
 1551         }
 1553         if (txmap->dm_nsegs > (SK_TX_RING_CNT - sc_if->sk_cdata.sk_tx_cnt - 2)) {
DPRINTFN(2, ("sk_encap: too few descriptors free\n"));
bus_dmamap_unload(sc->sc_dmatag, txmap);
 1556                 return (ENOBUFS);
 1557         }
DPRINTFN(2, ("sk_encap: dm_nsegs=%d\n", txmap->dm_nsegs));
 1561         /* Sync the DMA map. */
bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize,
BUS_DMASYNC_PREWRITE);
 1565         for (i = 0; i < txmap->dm_nsegs; i++) {
f = &sc_if->sk_rdata->sk_tx_ring[frag];
f->sk_data_lo = htole32(txmap->dm_segs[i].ds_addr);
sk_ctl = txmap->dm_segs[i].ds_len | SK_OPCODE_DEFAULT;
 1569                 if (i == 0)
sk_ctl |= SK_TXCTL_FIRSTFRAG;
 1571                 else
sk_ctl |= SK_TXCTL_OWN;
f->sk_ctl = htole32(sk_ctl);
cur = frag;
SK_INC(frag, SK_TX_RING_CNT);
 1576         }
sc_if->sk_cdata.sk_tx_chain[cur].sk_mbuf = m_head;
SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link);
sc_if->sk_cdata.sk_tx_map[cur] = entry;
sc_if->sk_rdata->sk_tx_ring[cur].sk_ctl |=
htole32(SK_TXCTL_LASTFRAG|SK_TXCTL_EOF_INTR);
 1585         /* Sync descriptors before handing to chip */
SK_CDTXSYNC(sc_if, *txidx, txmap->dm_nsegs,
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
sc_if->sk_rdata->sk_tx_ring[*txidx].sk_ctl |=
htole32(SK_TXCTL_OWN);
 1592         /* Sync first descriptor to hand it off */
SK_CDTXSYNC(sc_if, *txidx, 1, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
sc_if->sk_cdata.sk_tx_cnt += txmap->dm_nsegs;
 1597 #ifdef SK_DEBUG
 1598         if (skdebug >= 2) {
 1599                 struct sk_tx_desc *desc;
u_int32_t idx;
 1601                 for (idx = *txidx; idx != frag; SK_INC(idx, SK_TX_RING_CNT)) {
desc = &sc_if->sk_rdata->sk_tx_ring[idx];
sk_dump_txdesc(desc, idx);
 1604                 }
 1605         }
 1606 #endif
 1608         *txidx = frag;
DPRINTFN(2, ("sk_encap: completed successfully\n"));
 1612         return (0);
 1613 }
 1615 void
sk_start(struct ifnet *ifp)
 1617 {
 1618         struct sk_if_softc      *sc_if = ifp->if_softc;
 1619         struct sk_softc         *sc = sc_if->sk_softc;
 1620         struct mbuf             *m_head = NULL;
u_int32_t               idx = sc_if->sk_cdata.sk_tx_prod;
 1622         int                     pkts = 0;
DPRINTFN(2, ("sk_start\n"));
 1626         while (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf == NULL) {
IFQ_POLL(&ifp->if_snd, m_head);
 1628                 if (m_head == NULL)
 1629                         break;
 1631                 /*
 1632                  * Pack the data into the transmit ring. If we
 1633                  * don't have room, set the OACTIVE flag and wait
 1634                  * for the NIC to drain the ring.
 1635                  */
 1636                 if (sk_encap(sc_if, m_head, &idx)) {
ifp->if_flags |= IFF_OACTIVE;
 1638                         break;
 1639                 }
 1641                 /* now we are committed to transmit the packet */
IFQ_DEQUEUE(&ifp->if_snd, m_head);
pkts++;
 1645                 /*
 1646                  * If there's a BPF listener, bounce a copy of this frame
 1647                  * to him.
 1648                  */
 1649 #if NBPFILTER > 0
 1650                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT);
 1652 #endif
 1653         }
 1654         if (pkts == 0)
 1655                 return;
 1657         /* Transmit */
 1658         if (idx != sc_if->sk_cdata.sk_tx_prod) {
sc_if->sk_cdata.sk_tx_prod = idx;
CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
 1662                 /* Set a timeout in case the chip goes out to lunch. */
ifp->if_timer = 5;
 1664         }
 1665 }
 1668 void
sk_watchdog(struct ifnet *ifp)
 1670 {
 1671         struct sk_if_softc *sc_if = ifp->if_softc;
 1673         /*
 1674          * Reclaim first as there is a possibility of losing Tx completion
 1675          * interrupts.
 1676          */
sk_txeof(sc_if);
 1678         if (sc_if->sk_cdata.sk_tx_cnt != 0) {
printf("%s: watchdog timeout\n", sc_if->sk_dev.dv_xname);
ifp->if_oerrors++;
sk_init(sc_if);
 1684         }
 1685 }
 1687 void
skc_shutdown(void *v)
 1689 {
 1690         struct sk_softc         *sc = v;
DPRINTFN(2, ("sk_shutdown\n"));
 1694         /* Turn off the 'driver is loaded' LED. */
CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF);
 1697         /*
 1698          * Reset the GEnesis controller. Doing this should also
 1699          * assert the resets on the attached XMAC(s).
 1700          */
sk_reset(sc);
 1702 }
 1704 static __inline int
sk_rxvalid(struct sk_softc *sc, u_int32_t stat, u_int32_t len)
 1706 {
 1707         if (sc->sk_type == SK_GENESIS) {
 1708                 if ((stat & XM_RXSTAT_ERRFRAME) == XM_RXSTAT_ERRFRAME ||
XM_RXSTAT_BYTES(stat) != len)
 1710                         return (0);
 1711         } else {
 1712                 if ((stat & (YU_RXSTAT_CRCERR | YU_RXSTAT_LONGERR |
YU_RXSTAT_MIIERR | YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC |
YU_RXSTAT_JABBER)) != 0 ||
 1715                     (stat & YU_RXSTAT_RXOK) != YU_RXSTAT_RXOK ||
YU_RXSTAT_BYTES(stat) != len)
 1717                         return (0);
 1718         }
 1720         return (1);
 1721 }
 1723 void
sk_rxeof(struct sk_if_softc *sc_if)
 1725 {
 1726         struct sk_softc         *sc = sc_if->sk_softc;
 1727         struct ifnet            *ifp = &sc_if->arpcom.ac_if;
 1728         struct mbuf             *m;
 1729         struct sk_chain         *cur_rx;
 1730         struct sk_rx_desc       *cur_desc;
 1731         int                     i, cur, total_len = 0;
u_int32_t               rxstat, sk_ctl;
bus_dmamap_t            dmamap;
u_int16_t               csum1, csum2;
DPRINTFN(2, ("sk_rxeof\n"));
i = sc_if->sk_cdata.sk_rx_prod;
 1740         for (;;) {
cur = i;
 1743                 /* Sync the descriptor */
SK_CDRXSYNC(sc_if, cur,
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
sk_ctl = letoh32(sc_if->sk_rdata->sk_rx_ring[i].sk_ctl);
 1748                 if ((sk_ctl & SK_RXCTL_OWN) != 0) {
 1749                         /* Invalidate the descriptor -- it's not ready yet */
SK_CDRXSYNC(sc_if, cur, BUS_DMASYNC_PREREAD);
sc_if->sk_cdata.sk_rx_prod = i;
 1752                         break;
 1753                 }
cur_rx = &sc_if->sk_cdata.sk_rx_chain[cur];
cur_desc = &sc_if->sk_rdata->sk_rx_ring[cur];
dmamap = sc_if->sk_cdata.sk_rx_jumbo_map;
bus_dmamap_sync(sc_if->sk_softc->sc_dmatag, dmamap, 0,
dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
rxstat = letoh32(cur_desc->sk_xmac_rxstat);
m = cur_rx->sk_mbuf;
cur_rx->sk_mbuf = NULL;
total_len = SK_RXBYTES(letoh32(cur_desc->sk_ctl));
csum1 = letoh16(sc_if->sk_rdata->sk_rx_ring[i].sk_csum1);
csum2 = letoh16(sc_if->sk_rdata->sk_rx_ring[i].sk_csum2);
SK_INC(i, SK_RX_RING_CNT);
 1772                 if ((sk_ctl & (SK_RXCTL_STATUS_VALID | SK_RXCTL_FIRSTFRAG |
SK_RXCTL_LASTFRAG)) != (SK_RXCTL_STATUS_VALID |
SK_RXCTL_FIRSTFRAG | SK_RXCTL_LASTFRAG) ||
total_len < SK_MIN_FRAMELEN ||
total_len > SK_JUMBO_FRAMELEN ||
sk_rxvalid(sc, rxstat, total_len) == 0) {
ifp->if_ierrors++;
sk_newbuf(sc_if, cur, m, dmamap);
 1780                         continue;
 1781                 }
 1783                 /*
 1784                  * Try to allocate a new jumbo buffer. If that
 1785                  * fails, copy the packet to mbufs and put the
 1786                  * jumbo buffer back in the ring so it can be
 1787                  * re-used. If allocating mbufs fails, then we
 1788                  * have to drop the packet.
 1789                  */
 1790                 if (sk_newbuf(sc_if, cur, NULL, dmamap) == ENOBUFS) {
 1791                         struct mbuf             *m0;
m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
total_len + ETHER_ALIGN, 0, ifp, NULL);
sk_newbuf(sc_if, cur, m, dmamap);
 1795                         if (m0 == NULL) {
ifp->if_ierrors++;
 1797                                 continue;
 1798                         }
m_adj(m0, ETHER_ALIGN);
m = m0;
 1801                 } else {
m->m_pkthdr.rcvif = ifp;
m->m_pkthdr.len = m->m_len = total_len;
 1804                 }
ifp->if_ipackets++;
sk_rxcsum(ifp, m, csum1, csum2);
 1810 #if NBPFILTER > 0
 1811                 if (ifp->if_bpf)
bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN);
 1813 #endif
 1815                 /* pass it on. */
ether_input_mbuf(ifp, m);
 1817         }
 1818 }
 1820 void
sk_rxcsum(struct ifnet *ifp, struct mbuf *m, const u_int16_t csum1, const u_int16_t csum2)
 1822 {
 1823         struct ether_header *eh;
 1824         struct ip *ip;
u_int8_t *pp;
 1826         int hlen, len, plen;
u_int16_t iph_csum, ipo_csum, ipd_csum, csum;
pp = mtod(m, u_int8_t *);
plen = m->m_pkthdr.len;
 1831         if (plen < sizeof(*eh))
 1832                 return;
eh = (struct ether_header *)pp;
iph_csum = in_cksum_addword(csum1, (~csum2 & 0xffff));
 1836         if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
u_int16_t *xp = (u_int16_t *)pp;
xp = (u_int16_t *)pp;
 1840                 if (xp[1] != htons(ETHERTYPE_IP))
 1841                         return;
iph_csum = in_cksum_addword(iph_csum, (~xp[0] & 0xffff));
iph_csum = in_cksum_addword(iph_csum, (~xp[1] & 0xffff));
xp = (u_int16_t *)(pp + sizeof(struct ip));
iph_csum = in_cksum_addword(iph_csum, xp[0]);
iph_csum = in_cksum_addword(iph_csum, xp[1]);
pp += EVL_ENCAPLEN;
 1848         } else if (eh->ether_type != htons(ETHERTYPE_IP))
 1849                 return;
pp += sizeof(*eh);
plen -= sizeof(*eh);
ip = (struct ip *)pp;
 1856         if (ip->ip_v != IPVERSION)
 1857                 return;
hlen = ip->ip_hl << 2;
 1860         if (hlen < sizeof(struct ip))
 1861                 return;
 1862         if (hlen > ntohs(ip->ip_len))
 1863                 return;
 1865         /* Don't deal with truncated or padded packets. */
 1866         if (plen != ntohs(ip->ip_len))
 1867                 return;
len = hlen - sizeof(struct ip);
 1870         if (len > 0) {
u_int16_t *p;
p = (u_int16_t *)(ip + 1);
ipo_csum = 0;
 1875                 for (ipo_csum = 0; len > 0; len -= sizeof(*p), p++)
ipo_csum = in_cksum_addword(ipo_csum, *p);
iph_csum = in_cksum_addword(iph_csum, ipo_csum);
ipd_csum = in_cksum_addword(csum2, (~ipo_csum & 0xffff));
 1879         } else
ipd_csum = csum2;
 1882         if (iph_csum != 0xffff)
 1883                 return;
m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK;
 1886         if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
 1887                 return;                 /* ip frag, we're done for now */
pp += hlen;
 1891         /* Only know checksum protocol for udp/tcp */
 1892         if (ip->ip_p == IPPROTO_UDP) {
 1893                 struct udphdr *uh = (struct udphdr *)pp;
 1895                 if (uh->uh_sum == 0)    /* udp with no checksum */
 1896                         return;
 1897         } else if (ip->ip_p != IPPROTO_TCP)
 1898                 return;
csum = in_cksum_phdr(ip->ip_src.s_addr, ip->ip_dst.s_addr,
htonl(ntohs(ip->ip_len) - hlen + ip->ip_p) + ipd_csum);
 1902         if (csum == 0xffff) {
m->m_pkthdr.csum_flags |= (ip->ip_p == IPPROTO_TCP) ?
M_TCP_CSUM_IN_OK : M_UDP_CSUM_IN_OK;
 1905         }
 1906 }
 1908 void
sk_txeof(struct sk_if_softc *sc_if)
 1910 {
 1911         struct sk_softc         *sc = sc_if->sk_softc;
 1912         struct sk_tx_desc       *cur_tx;
 1913         struct ifnet            *ifp = &sc_if->arpcom.ac_if;
u_int32_t               idx, sk_ctl;
 1915         struct sk_txmap_entry   *entry;
DPRINTFN(2, ("sk_txeof\n"));
 1919         /*
 1920          * Go through our tx ring and free mbufs for those
 1921          * frames that have been sent.
 1922          */
idx = sc_if->sk_cdata.sk_tx_cons;
 1924         while (idx != sc_if->sk_cdata.sk_tx_prod) {
SK_CDTXSYNC(sc_if, idx, 1,
BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
cur_tx = &sc_if->sk_rdata->sk_tx_ring[idx];
sk_ctl = letoh32(cur_tx->sk_ctl);
 1930 #ifdef SK_DEBUG
 1931                 if (skdebug >= 2)
sk_dump_txdesc(cur_tx, idx);
 1933 #endif
 1934                 if (sk_ctl & SK_TXCTL_OWN) {
SK_CDTXSYNC(sc_if, idx, 1, BUS_DMASYNC_PREREAD);
 1936                         break;
 1937                 }
 1938                 if (sk_ctl & SK_TXCTL_LASTFRAG)
ifp->if_opackets++;
 1940                 if (sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf != NULL) {
entry = sc_if->sk_cdata.sk_tx_map[idx];
m_freem(sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf);
sc_if->sk_cdata.sk_tx_chain[idx].sk_mbuf = NULL;
bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0,
entry->dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
bus_dmamap_unload(sc->sc_dmatag, entry->dmamap);
SIMPLEQ_INSERT_TAIL(&sc_if->sk_txmap_head, entry,
link);
sc_if->sk_cdata.sk_tx_map[idx] = NULL;
 1953                 }
sc_if->sk_cdata.sk_tx_cnt--;
SK_INC(idx, SK_TX_RING_CNT);
 1956         }
ifp->if_timer = sc_if->sk_cdata.sk_tx_cnt > 0 ? 5 : 0;
 1959         if (sc_if->sk_cdata.sk_tx_cnt < SK_TX_RING_CNT - 2)
ifp->if_flags &= ~IFF_OACTIVE;
sc_if->sk_cdata.sk_tx_cons = idx;
 1963 }
 1965 void
sk_tick(void *xsc_if)
 1967 {
 1968         struct sk_if_softc *sc_if = xsc_if;
 1969         struct mii_data *mii = &sc_if->sk_mii;
 1970         struct ifnet *ifp = &sc_if->arpcom.ac_if;
 1971         int i;
DPRINTFN(2, ("sk_tick\n"));
 1975         if (!(ifp->if_flags & IFF_UP))
 1976                 return;
 1978         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
sk_intr_bcom(sc_if);
 1980                 return;
 1981         }
 1983         /*
 1984          * According to SysKonnect, the correct way to verify that
 1985          * the link has come back up is to poll bit 0 of the GPIO
 1986          * register three times. This pin has the signal from the
 1987          * link sync pin connected to it; if we read the same link
 1988          * state 3 times in a row, we know the link is up.
 1989          */
 1990         for (i = 0; i < 3; i++) {
 1991                 if (SK_XM_READ_2(sc_if, XM_GPIO) & XM_GPIO_GP0_SET)
 1992                         break;
 1993         }
 1995         if (i != 3) {
timeout_add(&sc_if->sk_tick_ch, hz);
 1997                 return;
 1998         }
 2000         /* Turn the GP0 interrupt back on. */
SK_XM_CLRBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
SK_XM_READ_2(sc_if, XM_ISR);
mii_tick(mii);
timeout_del(&sc_if->sk_tick_ch);
 2005 }
 2007 void
sk_yukon_tick(void *xsc_if)
 2009 {
 2010         struct sk_if_softc *sc_if = xsc_if;  
 2011         struct mii_data *mii = &sc_if->sk_mii;
mii_tick(mii);
timeout_add(&sc_if->sk_tick_ch, hz);
 2015 }
 2017 void
sk_intr_bcom(struct sk_if_softc *sc_if)
 2019 {
 2020         struct mii_data *mii = &sc_if->sk_mii;
 2021         struct ifnet *ifp = &sc_if->arpcom.ac_if;
 2022         int status;
DPRINTFN(2, ("sk_intr_bcom\n"));
SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
 2028         /*
 2029          * Read the PHY interrupt register to make sure
 2030          * we clear any pending interrupts.
 2031          */
status = sk_xmac_miibus_readreg((struct device *)sc_if,
SK_PHYADDR_BCOM, BRGPHY_MII_ISR);
 2035         if (!(ifp->if_flags & IFF_RUNNING)) {
sk_init_xmac(sc_if);
 2037                 return;
 2038         }
 2040         if (status & (BRGPHY_ISR_LNK_CHG|BRGPHY_ISR_AN_PR)) {
 2041                 int lstat;
lstat = sk_xmac_miibus_readreg((struct device *)sc_if,
SK_PHYADDR_BCOM, BRGPHY_MII_AUXSTS);
 2045                 if (!(lstat & BRGPHY_AUXSTS_LINK) && sc_if->sk_link) {
mii_mediachg(mii);
 2047                         /* Turn off the link LED. */
SK_IF_WRITE_1(sc_if, 0,
SK_LINKLED1_CTL, SK_LINKLED_OFF);
sc_if->sk_link = 0;
 2051                 } else if (status & BRGPHY_ISR_LNK_CHG) {
sk_xmac_miibus_writereg((struct device *)sc_if,
SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFF00);
mii_tick(mii);
sc_if->sk_link = 1;
 2056                         /* Turn on the link LED. */
SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
SK_LINKLED_ON|SK_LINKLED_LINKSYNC_OFF|
SK_LINKLED_BLINK_OFF);
 2060                 } else {
mii_tick(mii);
timeout_add(&sc_if->sk_tick_ch, hz);
 2063                 }
 2064         }
SK_XM_SETBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
 2067 }
 2069 void
sk_intr_xmac(struct sk_if_softc *sc_if)
 2071 {
u_int16_t status = SK_XM_READ_2(sc_if, XM_ISR);
DPRINTFN(2, ("sk_intr_xmac\n"));
 2076         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC) {
 2077                 if (status & XM_ISR_GP0_SET) {
SK_XM_SETBIT_2(sc_if, XM_IMR, XM_IMR_GP0_SET);
timeout_add(&sc_if->sk_tick_ch, hz);
 2080                 }
 2082                 if (status & XM_ISR_AUTONEG_DONE) {
timeout_add(&sc_if->sk_tick_ch, hz);
 2084                 }
 2085         }
 2087         if (status & XM_IMR_TX_UNDERRUN)
SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_TXFIFO);
 2090         if (status & XM_IMR_RX_OVERRUN)
SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_FLUSH_RXFIFO);
 2092 }
 2094 void
sk_intr_yukon(struct sk_if_softc *sc_if)
 2096 {
u_int8_t status;
status = SK_IF_READ_1(sc_if, 0, SK_GMAC_ISR);
 2100         /* RX overrun */
 2101         if ((status & SK_GMAC_INT_RX_OVER) != 0) {
SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST,
SK_RFCTL_RX_FIFO_OVER);
 2104         }
 2105         /* TX underrun */
 2106         if ((status & SK_GMAC_INT_TX_UNDER) != 0) {
SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST,
SK_TFCTL_TX_FIFO_UNDER);
 2109         }
DPRINTFN(2, ("sk_intr_yukon status=%#x\n", status));
 2112 }
 2114 int
sk_intr(void *xsc)
 2116 {
 2117         struct sk_softc         *sc = xsc;
 2118         struct sk_if_softc      *sc_if0 = sc->sk_if[SK_PORT_A];
 2119         struct sk_if_softc      *sc_if1 = sc->sk_if[SK_PORT_B];
 2120         struct ifnet            *ifp0 = NULL, *ifp1 = NULL;
u_int32_t               status;
 2122         int                     claimed = 0;
status = CSR_READ_4(sc, SK_ISSR);
 2125         if (status == 0 || status == 0xffffffff)
 2126                 return (0);
 2128         if (sc_if0 != NULL)
ifp0 = &sc_if0->arpcom.ac_if;
 2130         if (sc_if1 != NULL)
ifp1 = &sc_if1->arpcom.ac_if;
 2133         for (; (status &= sc->sk_intrmask) != 0;) {
claimed = 1;
 2136                 /* Handle receive interrupts first. */
 2137                 if (sc_if0 && (status & SK_ISR_RX1_EOF)) {
sk_rxeof(sc_if0);
CSR_WRITE_4(sc, SK_BMU_RX_CSR0,
SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
 2141                 }
 2142                 if (sc_if1 && (status & SK_ISR_RX2_EOF)) {
sk_rxeof(sc_if1);
CSR_WRITE_4(sc, SK_BMU_RX_CSR1,
SK_RXBMU_CLR_IRQ_EOF|SK_RXBMU_RX_START);
 2146                 }
 2148                 /* Then transmit interrupts. */
 2149                 if (sc_if0 && (status & SK_ISR_TX1_S_EOF)) {
sk_txeof(sc_if0);
CSR_WRITE_4(sc, SK_BMU_TXS_CSR0,
SK_TXBMU_CLR_IRQ_EOF);
 2153                 }
 2154                 if (sc_if1 && (status & SK_ISR_TX2_S_EOF)) {
sk_txeof(sc_if1);
CSR_WRITE_4(sc, SK_BMU_TXS_CSR1,
SK_TXBMU_CLR_IRQ_EOF);
 2158                 }
 2160                 /* Then MAC interrupts. */
 2161                 if (sc_if0 && (status & SK_ISR_MAC1) &&
 2162                     (ifp0->if_flags & IFF_RUNNING)) {
 2163                         if (SK_IS_GENESIS(sc))
sk_intr_xmac(sc_if0);
 2165                         else
sk_intr_yukon(sc_if0);
 2167                 }
 2169                 if (sc_if1 && (status & SK_ISR_MAC2) &&
 2170                     (ifp1->if_flags & IFF_RUNNING)) {
 2171                         if (SK_IS_GENESIS(sc))
sk_intr_xmac(sc_if1);
 2173                         else
sk_intr_yukon(sc_if1);
 2176                 }
 2178                 if (status & SK_ISR_EXTERNAL_REG) {
 2179                         if (sc_if0 != NULL &&
sc_if0->sk_phytype == SK_PHYTYPE_BCOM)
sk_intr_bcom(sc_if0);
 2183                         if (sc_if1 != NULL &&
sc_if1->sk_phytype == SK_PHYTYPE_BCOM)
sk_intr_bcom(sc_if1);
 2186                 }
status = CSR_READ_4(sc, SK_ISSR);
 2188         }
CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
 2192         if (ifp0 != NULL && !IFQ_IS_EMPTY(&ifp0->if_snd))
sk_start(ifp0);
 2194         if (ifp1 != NULL && !IFQ_IS_EMPTY(&ifp1->if_snd))
sk_start(ifp1);
 2197         return (claimed);
 2198 }
 2200 void
sk_init_xmac(struct sk_if_softc *sc_if)
 2202 {
 2203         struct sk_softc         *sc = sc_if->sk_softc;
 2204         struct ifnet            *ifp = &sc_if->arpcom.ac_if;
 2205         struct sk_bcom_hack     bhack[] = {
 2206         { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, { 0x17, 0x0013 },
 2207         { 0x15, 0x0404 }, { 0x17, 0x8006 }, { 0x15, 0x0132 }, { 0x17, 0x8006 },
 2208         { 0x15, 0x0232 }, { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
 2209         { 0, 0 } };
DPRINTFN(2, ("sk_init_xmac\n"));
 2213         /* Unreset the XMAC. */
SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL, SK_TXMACCTL_XMAC_UNRESET);
DELAY(1000);
 2217         /* Reset the XMAC's internal state. */
SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
 2220         /* Save the XMAC II revision */
sc_if->sk_xmac_rev = XM_XMAC_REV(SK_XM_READ_4(sc_if, XM_DEVID));
 2223         /*
 2224          * Perform additional initialization for external PHYs,
 2225          * namely for the 1000baseTX cards that use the XMAC's
 2226          * GMII mode.
 2227          */
 2228         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
 2229                 int                     i = 0;
u_int32_t               val;
 2232                 /* Take PHY out of reset. */
val = sk_win_read_4(sc, SK_GPIO);
 2234                 if (sc_if->sk_port == SK_PORT_A)
val |= SK_GPIO_DIR0|SK_GPIO_DAT0;
 2236                 else
val |= SK_GPIO_DIR2|SK_GPIO_DAT2;
sk_win_write_4(sc, SK_GPIO, val);
 2240                 /* Enable GMII mode on the XMAC. */
SK_XM_SETBIT_2(sc_if, XM_HWCFG, XM_HWCFG_GMIIMODE);
sk_xmac_miibus_writereg((struct device *)sc_if,
SK_PHYADDR_BCOM, BRGPHY_MII_BMCR, BRGPHY_BMCR_RESET);
DELAY(10000);
sk_xmac_miibus_writereg((struct device *)sc_if,
SK_PHYADDR_BCOM, BRGPHY_MII_IMR, 0xFFF0);
 2249                 /*
 2250                  * Early versions of the BCM5400 apparently have
 2251                  * a bug that requires them to have their reserved
 2252                  * registers initialized to some magic values. I don't
 2253                  * know what the numbers do, I'm just the messenger.
 2254                  */
 2255                 if (sk_xmac_miibus_readreg((struct device *)sc_if,
SK_PHYADDR_BCOM, 0x03) == 0x6041) {
 2257                         while(bhack[i].reg) {
sk_xmac_miibus_writereg((struct device *)sc_if,
SK_PHYADDR_BCOM, bhack[i].reg,
bhack[i].val);
i++;
 2262                         }
 2263                 }
 2264         }
 2266         /* Set station address */
SK_XM_WRITE_2(sc_if, XM_PAR0,
letoh16(*(u_int16_t *)(&sc_if->arpcom.ac_enaddr[0])));
SK_XM_WRITE_2(sc_if, XM_PAR1,
letoh16(*(u_int16_t *)(&sc_if->arpcom.ac_enaddr[2])));
SK_XM_WRITE_2(sc_if, XM_PAR2,
letoh16(*(u_int16_t *)(&sc_if->arpcom.ac_enaddr[4])));
SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_USE_STATION);
 2275         if (ifp->if_flags & IFF_BROADCAST)
SK_XM_CLRBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
 2277         else
SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_NOBROAD);
 2280         /* We don't need the FCS appended to the packet. */
SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_STRIPFCS);
 2283         /* We want short frames padded to 60 bytes. */
SK_XM_SETBIT_2(sc_if, XM_TXCMD, XM_TXCMD_AUTOPAD);
 2286         /*
 2287          * Enable the reception of all error frames. This is
 2288          * a necessary evil due to the design of the XMAC. The
 2289          * XMAC's receive FIFO is only 8K in size, however jumbo
 2290          * frames can be up to 9000 bytes in length. When bad
 2291          * frame filtering is enabled, the XMAC's RX FIFO operates
 2292          * in 'store and forward' mode. For this to work, the
 2293          * entire frame has to fit into the FIFO, but that means
 2294          * that jumbo frames larger than 8192 bytes will be
 2295          * truncated. Disabling all bad frame filtering causes
 2296          * the RX FIFO to operate in streaming mode, in which
 2297          * case the XMAC will start transfering frames out of the
 2298          * RX FIFO as soon as the FIFO threshold is reached.
 2299          */
SK_XM_SETBIT_4(sc_if, XM_MODE, XM_MODE_RX_BADFRAMES|
XM_MODE_RX_GIANTS|XM_MODE_RX_RUNTS|XM_MODE_RX_CRCERRS|
XM_MODE_RX_INRANGELEN);
SK_XM_SETBIT_2(sc_if, XM_RXCMD, XM_RXCMD_BIGPKTOK);
 2306         /*
 2307          * Bump up the transmit threshold. This helps hold off transmit
 2308          * underruns when we're blasting traffic from both ports at once.
 2309          */
SK_XM_WRITE_2(sc_if, XM_TX_REQTHRESH, SK_XM_TX_FIFOTHRESH);
 2312         /* Set promiscuous mode */
sk_setpromisc(sc_if);
 2315         /* Set multicast filter */
sk_setmulti(sc_if);
 2318         /* Clear and enable interrupts */
SK_XM_READ_2(sc_if, XM_ISR);
 2320         if (sc_if->sk_phytype == SK_PHYTYPE_XMAC)
SK_XM_WRITE_2(sc_if, XM_IMR, XM_INTRS);
 2322         else
SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
 2325         /* Configure MAC arbiter */
 2326         switch(sc_if->sk_xmac_rev) {
 2327         case XM_XMAC_REV_B2:
sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_B2);
sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_B2);
sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_B2);
sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_B2);
sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_B2);
sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_B2);
sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_B2);
sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_B2);
sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
 2337                 break;
 2338         case XM_XMAC_REV_C1:
sk_win_write_1(sc, SK_RCINIT_RX1, SK_RCINIT_XMAC_C1);
sk_win_write_1(sc, SK_RCINIT_TX1, SK_RCINIT_XMAC_C1);
sk_win_write_1(sc, SK_RCINIT_RX2, SK_RCINIT_XMAC_C1);
sk_win_write_1(sc, SK_RCINIT_TX2, SK_RCINIT_XMAC_C1);
sk_win_write_1(sc, SK_MINIT_RX1, SK_MINIT_XMAC_C1);
sk_win_write_1(sc, SK_MINIT_TX1, SK_MINIT_XMAC_C1);
sk_win_write_1(sc, SK_MINIT_RX2, SK_MINIT_XMAC_C1);
sk_win_write_1(sc, SK_MINIT_TX2, SK_MINIT_XMAC_C1);
sk_win_write_1(sc, SK_RECOVERY_CTL, SK_RECOVERY_XMAC_B2);
 2348                 break;
 2349         default:
 2350                 break;
 2351         }
sk_win_write_2(sc, SK_MACARB_CTL,
SK_MACARBCTL_UNRESET|SK_MACARBCTL_FASTOE_OFF);
sc_if->sk_link = 1;
 2356 }
 2358 void sk_init_yukon(struct sk_if_softc *sc_if)
 2359 {
u_int32_t               phy, v;
u_int16_t               reg;
 2362         struct sk_softc         *sc;
 2363         int                     i;
sc = sc_if->sk_softc;
DPRINTFN(2, ("sk_init_yukon: start: sk_csr=%#x\n",
CSR_READ_4(sc_if->sk_softc, SK_CSR)));
 2370         if (sc->sk_type == SK_YUKON_LITE &&
sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
 2372                 /*
 2373                  * Workaround code for COMA mode, set PHY reset.
 2374                  * Otherwise it will not correctly take chip out of
 2375                  * powerdown (coma)
 2376                  */
v = sk_win_read_4(sc, SK_GPIO);
v |= SK_GPIO_DIR9 | SK_GPIO_DAT9;
sk_win_write_4(sc, SK_GPIO, v);
 2380         }
DPRINTFN(6, ("sk_init_yukon: 1\n"));
 2384         /* GMAC and GPHY Reset */
SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, SK_GPHY_RESET_SET);
SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_RESET_SET);
DELAY(1000);
DPRINTFN(6, ("sk_init_yukon: 2\n"));
 2391         if (sc->sk_type == SK_YUKON_LITE &&
sc->sk_rev >= SK_YUKON_LITE_REV_A3) {
 2393                 /*
 2394                  * Workaround code for COMA mode, clear PHY reset
 2395                  */
v = sk_win_read_4(sc, SK_GPIO);
v |= SK_GPIO_DIR9;
v &= ~SK_GPIO_DAT9;
sk_win_write_4(sc, SK_GPIO, v);
 2400         }
phy = SK_GPHY_INT_POL_HI | SK_GPHY_DIS_FC | SK_GPHY_DIS_SLEEP |
SK_GPHY_ENA_XC | SK_GPHY_ANEG_ALL | SK_GPHY_ENA_PAUSE;
 2405         if (sc->sk_coppertype)
phy |= SK_GPHY_COPPER;
 2407         else
phy |= SK_GPHY_FIBER;
DPRINTFN(3, ("sk_init_yukon: phy=%#x\n", phy));
SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_SET);
DELAY(1000);
SK_IF_WRITE_4(sc_if, 0, SK_GPHY_CTRL, phy | SK_GPHY_RESET_CLEAR);
SK_IF_WRITE_4(sc_if, 0, SK_GMAC_CTRL, SK_GMAC_LOOP_OFF |
SK_GMAC_PAUSE_ON | SK_GMAC_RESET_CLEAR);
DPRINTFN(3, ("sk_init_yukon: gmac_ctrl=%#x\n",
SK_IF_READ_4(sc_if, 0, SK_GMAC_CTRL)));
DPRINTFN(6, ("sk_init_yukon: 3\n"));
 2423         /* unused read of the interrupt source register */
DPRINTFN(6, ("sk_init_yukon: 4\n"));
SK_IF_READ_2(sc_if, 0, SK_GMAC_ISR);
DPRINTFN(6, ("sk_init_yukon: 4a\n"));
reg = SK_YU_READ_2(sc_if, YUKON_PAR);
DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg));
 2431         /* MIB Counter Clear Mode set */
reg |= YU_PAR_MIB_CLR;
DPRINTFN(6, ("sk_init_yukon: YUKON_PAR=%#x\n", reg));
DPRINTFN(6, ("sk_init_yukon: 4b\n"));
SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
 2437         /* MIB Counter Clear Mode clear */
DPRINTFN(6, ("sk_init_yukon: 5\n"));
reg &= ~YU_PAR_MIB_CLR;
SK_YU_WRITE_2(sc_if, YUKON_PAR, reg);
 2442         /* receive control reg */
DPRINTFN(6, ("sk_init_yukon: 7\n"));
SK_YU_WRITE_2(sc_if, YUKON_RCR, YU_RCR_CRCR);
 2446         /* transmit parameter register */
DPRINTFN(6, ("sk_init_yukon: 8\n"));
SK_YU_WRITE_2(sc_if, YUKON_TPR, YU_TPR_JAM_LEN(0x3) |
YU_TPR_JAM_IPG(0xb) | YU_TPR_JAM2DATA_IPG(0x1a) );
 2451         /* serial mode register */
DPRINTFN(6, ("sk_init_yukon: 9\n"));
SK_YU_WRITE_2(sc_if, YUKON_SMR, YU_SMR_DATA_BLIND(0x1c) |
YU_SMR_MFL_VLAN | YU_SMR_MFL_JUMBO |
YU_SMR_IPG_DATA(0x1e));
DPRINTFN(6, ("sk_init_yukon: 10\n"));
 2458         /* Setup Yukon's address */
 2459         for (i = 0; i < 3; i++) {
 2460                 /* Write Source Address 1 (unicast filter) */
SK_YU_WRITE_2(sc_if, YUKON_SAL1 + i * 4, 
sc_if->arpcom.ac_enaddr[i * 2] |
sc_if->arpcom.ac_enaddr[i * 2 + 1] << 8);
 2464         }
 2466         for (i = 0; i < 3; i++) {
reg = sk_win_read_2(sc_if->sk_softc,
SK_MAC1_0 + i * 2 + sc_if->sk_port * 8);
SK_YU_WRITE_2(sc_if, YUKON_SAL2 + i * 4, reg);
 2470         }
 2472         /* Set promiscuous mode */
sk_setpromisc(sc_if);
 2475         /* Set multicast filter */
DPRINTFN(6, ("sk_init_yukon: 11\n"));
sk_setmulti(sc_if);
 2479         /* enable interrupt mask for counter overflows */
DPRINTFN(6, ("sk_init_yukon: 12\n"));
SK_YU_WRITE_2(sc_if, YUKON_TIMR, 0);
SK_YU_WRITE_2(sc_if, YUKON_RIMR, 0);
SK_YU_WRITE_2(sc_if, YUKON_TRIMR, 0);
 2485         /* Configure RX MAC FIFO Flush Mask */
v = YU_RXSTAT_FOFL | YU_RXSTAT_CRCERR | YU_RXSTAT_MIIERR |
YU_RXSTAT_BADFC | YU_RXSTAT_GOODFC | YU_RXSTAT_RUNT |
YU_RXSTAT_JABBER;
SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_MASK, v);
 2491         /* Disable RX MAC FIFO Flush for YUKON-Lite Rev. A0 only */
 2492         if (sc->sk_type == SK_YUKON_LITE && sc->sk_rev == SK_YUKON_LITE_REV_A0)
v = SK_TFCTL_OPERATION_ON;
 2494         else
v = SK_TFCTL_OPERATION_ON | SK_RFCTL_FIFO_FLUSH_ON;
 2496         /* Configure RX MAC FIFO */
SK_IF_WRITE_1(sc_if, 0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_CLEAR);
SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_CTRL_TEST, v);
 2500         /* Increase flush threshould to 64 bytes */
SK_IF_WRITE_2(sc_if, 0, SK_RXMF1_FLUSH_THRESHOLD,
SK_RFCTL_FIFO_THRESHOLD + 1);
 2504         /* Configure TX MAC FIFO */
SK_IF_WRITE_1(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_CLEAR);
SK_IF_WRITE_2(sc_if, 0, SK_TXMF1_CTRL_TEST, SK_TFCTL_OPERATION_ON);
DPRINTFN(6, ("sk_init_yukon: end\n"));
 2509 }
 2511 /*
 2512  * Note that to properly initialize any part of the GEnesis chip,
 2513  * you first have to take it out of reset mode.
 2514  */
 2515 void
sk_init(void *xsc_if)
 2517 {
 2518         struct sk_if_softc      *sc_if = xsc_if;
 2519         struct sk_softc         *sc = sc_if->sk_softc;
 2520         struct ifnet            *ifp = &sc_if->arpcom.ac_if;
 2521         struct mii_data         *mii = &sc_if->sk_mii;
 2522         int                     s;
DPRINTFN(2, ("sk_init\n"));
s = splnet();
 2528         /* Cancel pending I/O and free all RX/TX buffers. */
sk_stop(sc_if);
 2531         if (SK_IS_GENESIS(sc)) {
 2532                 /* Configure LINK_SYNC LED */
SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_ON);
SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL,
SK_LINKLED_LINKSYNC_ON);
 2537                 /* Configure RX LED */
SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL,
SK_RXLEDCTL_COUNTER_START);
 2541                 /* Configure TX LED */
SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL,
SK_TXLEDCTL_COUNTER_START);
 2544         }
 2546         /*
 2547          * Configure descriptor poll timer
 2548          *
 2549          * SK-NET GENESIS data sheet says that possibility of losing Start
 2550          * transmit command due to CPU/cache related interim storage problems
 2551          * under certain conditions. The document recommends a polling
 2552          * mechanism to send a Start transmit command to initiate transfer
 2553          * of ready descriptors regulary. To cope with this issue sk(4) now
 2554          * enables descriptor poll timer to initiate descriptor processing
 2555          * periodically as defined by SK_DPT_TIMER_MAX. However sk(4) still
 2556          * issue SK_TXBMU_TX_START to Tx BMU to get fast execution of Tx
 2557          * command instead of waiting for next descriptor polling time.
 2558          * The same rule may apply to Rx side too but it seems that is not
 2559          * needed at the moment.
 2560          * Since sk(4) uses descriptor polling as a last resort there is no
 2561          * need to set smaller polling time than maximum allowable one.
 2562          */
SK_IF_WRITE_4(sc_if, 0, SK_DPT_INIT, SK_DPT_TIMER_MAX);
 2565         /* Configure I2C registers */
 2567         /* Configure XMAC(s) */
 2568         switch (sc->sk_type) {
 2569         case SK_GENESIS:
sk_init_xmac(sc_if);
 2571                 break;
 2572         case SK_YUKON:
 2573         case SK_YUKON_LITE:
 2574         case SK_YUKON_LP:
sk_init_yukon(sc_if);
 2576                 break;
 2577         }
mii_mediachg(mii);
 2580         if (SK_IS_GENESIS(sc)) {
 2581                 /* Configure MAC FIFOs */
SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_UNRESET);
SK_IF_WRITE_4(sc_if, 0, SK_RXF1_END, SK_FIFO_END);
SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_ON);
SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_UNRESET);
SK_IF_WRITE_4(sc_if, 0, SK_TXF1_END, SK_FIFO_END);
SK_IF_WRITE_4(sc_if, 0, SK_TXF1_CTL, SK_FIFO_ON);
 2589         }
 2591         /* Configure transmit arbiter(s) */
SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL,
SK_TXARCTL_ON|SK_TXARCTL_FSYNC_ON);
 2595         /* Configure RAMbuffers */
SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_UNRESET);
SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_START, sc_if->sk_rx_ramstart);
SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_WR_PTR, sc_if->sk_rx_ramstart);
SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_RD_PTR, sc_if->sk_rx_ramstart);
SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_END, sc_if->sk_rx_ramend);
SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_ON);
SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_UNRESET);
SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_STORENFWD_ON);
SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_START, sc_if->sk_tx_ramstart);
SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_WR_PTR, sc_if->sk_tx_ramstart);
SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_RD_PTR, sc_if->sk_tx_ramstart);
SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_END, sc_if->sk_tx_ramend);
SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_ON);
 2611         /* Configure BMUs */
SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_ONLINE);
SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_LO,
SK_RX_RING_ADDR(sc_if, 0));
SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_CURADDR_HI, 0);
SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_ONLINE);
SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_LO,
SK_TX_RING_ADDR(sc_if, 0));
SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_CURADDR_HI, 0);
 2622         /* Init descriptors */
 2623         if (sk_init_rx_ring(sc_if) == ENOBUFS) {
printf("%s: initialization failed: no "
 2625                     "memory for rx buffers\n", sc_if->sk_dev.dv_xname);
sk_stop(sc_if);
splx(s);
 2628                 return;
 2629         }
 2631         if (sk_init_tx_ring(sc_if) == ENOBUFS) {
printf("%s: initialization failed: no "
 2633                     "memory for tx buffers\n", sc_if->sk_dev.dv_xname);
sk_stop(sc_if);
splx(s);
 2636                 return;
 2637         }
 2639         /* Configure interrupt handling */
CSR_READ_4(sc, SK_ISSR);
 2641         if (sc_if->sk_port == SK_PORT_A)
sc->sk_intrmask |= SK_INTRS1;
 2643         else
sc->sk_intrmask |= SK_INTRS2;
sc->sk_intrmask |= SK_ISR_EXTERNAL_REG;
CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
 2650         /* Start BMUs. */
SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_START);
 2653         if (SK_IS_GENESIS(sc)) {
 2654                 /* Enable XMACs TX and RX state machines */
SK_XM_CLRBIT_2(sc_if, XM_MMUCMD, XM_MMUCMD_IGNPAUSE);
SK_XM_SETBIT_2(sc_if, XM_MMUCMD,
XM_MMUCMD_TX_ENB|XM_MMUCMD_RX_ENB);
 2658         }
 2660         if (SK_IS_YUKON(sc)) {
u_int16_t reg = SK_YU_READ_2(sc_if, YUKON_GPCR);
reg |= YU_GPCR_TXEN | YU_GPCR_RXEN;
SK_YU_WRITE_2(sc_if, YUKON_GPCR, reg);
 2664         }
 2666         /* Activate descriptor polling timer */
SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_START);
 2668         /* start transfer of Tx descriptors */
CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_START);
ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
 2674         if (SK_IS_YUKON(sc))
timeout_add(&sc_if->sk_tick_ch, hz);
splx(s);
 2678 }
 2680 void
sk_stop(struct sk_if_softc *sc_if)
 2682 {
 2683         struct sk_softc         *sc = sc_if->sk_softc;
 2684         struct ifnet            *ifp = &sc_if->arpcom.ac_if;
 2685         struct sk_txmap_entry   *dma;
 2686         int                     i;
u_int32_t               val;
DPRINTFN(2, ("sk_stop\n"));
timeout_del(&sc_if->sk_tick_ch);
ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
 2695         /* stop Tx descriptor polling timer */
SK_IF_WRITE_4(sc_if, 0, SK_DPT_TIMER_CTRL, SK_DPT_TCTL_STOP);
 2697         /* stop transfer of Tx descriptors */
CSR_WRITE_4(sc, sc_if->sk_tx_bmu, SK_TXBMU_TX_STOP);
 2699         for (i = 0; i < SK_TIMEOUT; i++) {
val = CSR_READ_4(sc, sc_if->sk_tx_bmu);
 2701                 if (!(val & SK_TXBMU_TX_STOP))
 2702                         break;
DELAY(1);
 2704         }
 2705         if (i == SK_TIMEOUT)
printf("%s: cannot stop transfer of Tx descriptors\n",
sc_if->sk_dev.dv_xname);
 2708         /* stop transfer of Rx descriptors */
SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_RX_STOP);
 2710         for (i = 0; i < SK_TIMEOUT; i++) {
val = SK_IF_READ_4(sc_if, 0, SK_RXQ1_BMU_CSR);
 2712                 if (!(val & SK_RXBMU_RX_STOP))
 2713                         break;
DELAY(1);
 2715         }
 2716         if (i == SK_TIMEOUT)
printf("%s: cannot stop transfer of Rx descriptors\n",
sc_if->sk_dev.dv_xname);
 2720         if (sc_if->sk_phytype == SK_PHYTYPE_BCOM) {
u_int32_t               val;
 2723                 /* Put PHY back into reset. */
val = sk_win_read_4(sc, SK_GPIO);
 2725                 if (sc_if->sk_port == SK_PORT_A) {
val |= SK_GPIO_DIR0;
val &= ~SK_GPIO_DAT0;
 2728                 } else {
val |= SK_GPIO_DIR2;
val &= ~SK_GPIO_DAT2;
 2731                 }
sk_win_write_4(sc, SK_GPIO, val);
 2733         }
 2735         /* Turn off various components of this interface. */
SK_XM_SETBIT_2(sc_if, XM_GPIO, XM_GPIO_RESETMAC);
 2737         switch (sc->sk_type) {
 2738         case SK_GENESIS:
SK_IF_WRITE_2(sc_if, 0, SK_TXF1_MACCTL,
SK_TXMACCTL_XMAC_RESET);
SK_IF_WRITE_4(sc_if, 0, SK_RXF1_CTL, SK_FIFO_RESET);
 2742                 break;
 2743         case SK_YUKON:
 2744         case SK_YUKON_LITE:
 2745         case SK_YUKON_LP:
SK_IF_WRITE_1(sc_if,0, SK_RXMF1_CTRL_TEST, SK_RFCTL_RESET_SET);
SK_IF_WRITE_1(sc_if,0, SK_TXMF1_CTRL_TEST, SK_TFCTL_RESET_SET);
 2748                 break;
 2749         }
SK_IF_WRITE_4(sc_if, 0, SK_RXQ1_BMU_CSR, SK_RXBMU_OFFLINE);
SK_IF_WRITE_4(sc_if, 0, SK_RXRB1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
SK_IF_WRITE_4(sc_if, 1, SK_TXQS1_BMU_CSR, SK_TXBMU_OFFLINE);
SK_IF_WRITE_4(sc_if, 1, SK_TXRBS1_CTLTST, SK_RBCTL_RESET|SK_RBCTL_OFF);
SK_IF_WRITE_1(sc_if, 0, SK_TXAR1_COUNTERCTL, SK_TXARCTL_OFF);
SK_IF_WRITE_1(sc_if, 0, SK_RXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
SK_IF_WRITE_1(sc_if, 0, SK_TXLED1_CTL, SK_RXLEDCTL_COUNTER_STOP);
SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_OFF);
SK_IF_WRITE_1(sc_if, 0, SK_LINKLED1_CTL, SK_LINKLED_LINKSYNC_OFF);
 2760         /* Disable interrupts */
 2761         if (sc_if->sk_port == SK_PORT_A)
sc->sk_intrmask &= ~SK_INTRS1;
 2763         else
sc->sk_intrmask &= ~SK_INTRS2;
CSR_WRITE_4(sc, SK_IMR, sc->sk_intrmask);
SK_XM_READ_2(sc_if, XM_ISR);
SK_XM_WRITE_2(sc_if, XM_IMR, 0xFFFF);
 2770         /* Free RX and TX mbufs still in the queues. */
 2771         for (i = 0; i < SK_RX_RING_CNT; i++) {
 2772                 if (sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf != NULL) {
m_freem(sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf);
sc_if->sk_cdata.sk_rx_chain[i].sk_mbuf = NULL;
 2775                 }
 2776         }
 2778         for (i = 0; i < SK_TX_RING_CNT; i++) {
 2779                 if (sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf != NULL) {
m_freem(sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf);
sc_if->sk_cdata.sk_tx_chain[i].sk_mbuf = NULL;
SIMPLEQ_INSERT_HEAD(&sc_if->sk_txmap_head,
sc_if->sk_cdata.sk_tx_map[i], link);
sc_if->sk_cdata.sk_tx_map[i] = 0;
 2785                 }
 2786         }
 2788         while ((dma = SIMPLEQ_FIRST(&sc_if->sk_txmap_head))) {
SIMPLEQ_REMOVE_HEAD(&sc_if->sk_txmap_head, link);
bus_dmamap_destroy(sc->sc_dmatag, dma->dmamap);
free(dma, M_DEVBUF);
 2792         }
 2793 }
 2795 struct cfattach skc_ca = {
 2796         sizeof(struct sk_softc), skc_probe, skc_attach,
 2797 };
 2799 struct cfdriver skc_cd = {
 2800         0, "skc", DV_DULL
 2801 };
 2803 struct cfattach sk_ca = {
 2804         sizeof(struct sk_if_softc), sk_probe, sk_attach,
 2805 };
 2807 struct cfdriver sk_cd = {
 2808         0, "sk", DV_IFNET
 2809 };
 2811 #ifdef SK_DEBUG
 2812 void
sk_dump_txdesc(struct sk_tx_desc *desc, int idx)
 2814 {
 2815 #define DESC_PRINT(X)                                   \
 2816         if (X)                                  \
printf("txdesc[%d]." #X "=%#x\n",       \
idx, X);
DESC_PRINT(letoh32(desc->sk_ctl));
DESC_PRINT(letoh32(desc->sk_next));
DESC_PRINT(letoh32(desc->sk_data_lo));
DESC_PRINT(letoh32(desc->sk_data_hi));
DESC_PRINT(letoh32(desc->sk_xmac_txstat));
DESC_PRINT(letoh16(desc->sk_rsvd0));
DESC_PRINT(letoh16(desc->sk_csum_startval));
DESC_PRINT(letoh16(desc->sk_csum_startpos));
DESC_PRINT(letoh16(desc->sk_csum_writepos));
DESC_PRINT(letoh16(desc->sk_rsvd1));
 2830 #undef PRINT
 2831 }
 2833 void
sk_dump_bytes(const char *data, int len)
 2835 {
 2836         int c, i, j;
 2838         for (i = 0; i < len; i += 16) {
printf("%08x  ", i);
c = len - i;
 2841                 if (c > 16) c = 16;
 2843                 for (j = 0; j < c; j++) {
printf("%02x ", data[i + j] & 0xff);
 2845                         if ((j & 0xf) == 7 && j > 0)
printf(" ");
 2847                 }
 2849                 for (; j < 16; j++)
printf("   ");
printf("  ");
 2853                 for (j = 0; j < c; j++) {
 2854                         int ch = data[i + j] & 0xff;
printf("%c", ' ' <= ch && ch <= '~' ? ch : ' ');
 2856                 }
printf("\n");
 2860                 if (c < 16)
 2861                         break;
 2862         }
 2863 }
 2865 void
sk_dump_mbuf(struct mbuf *m)
 2867 {
 2868         int count = m->m_pkthdr.len;
printf("m=%#lx, m->m_pkthdr.len=%#d\n", m, m->m_pkthdr.len);
 2872         while (count > 0 && m) {
printf("m=%#lx, m->m_data=%#lx, m->m_len=%d\n",
m, m->m_data, m->m_len);
sk_dump_bytes(mtod(m, char *), m->m_len);
count -= m->m_len;
m = m->m_next;
 2879         }
 2880 }
 2881 #endif