root/dev/pci/if_skreg.h

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    1 /*      $OpenBSD: if_skreg.h,v 1.44 2007/02/26 20:27:17 kettenis Exp $  */
    2 
    3 /*
    4  * Copyright (c) 1997, 1998, 1999, 2000
    5  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. All advertising materials mentioning features or use of this software
   16  *    must display the following acknowledgement:
   17  *      This product includes software developed by Bill Paul.
   18  * 4. Neither the name of the author nor the names of any co-contributors
   19  *    may be used to endorse or promote products derived from this software
   20  *    without specific prior written permission.
   21  *
   22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   32  * THE POSSIBILITY OF SUCH DAMAGE.
   33  *
   34  * $FreeBSD: /c/ncvs/src/sys/pci/if_skreg.h,v 1.9 2000/04/22 02:16:37 wpaul Exp $
   35  * $FreeBSD: /c/ncvs/src/sys/pci/xmaciireg.h,v 1.3 2000/04/22 02:16:37 wpaul Exp $
   36  */
   37 
   38 /*
   39  * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
   40  *
   41  * Permission to use, copy, modify, and distribute this software for any
   42  * purpose with or without fee is hereby granted, provided that the above
   43  * copyright notice and this permission notice appear in all copies.
   44  *
   45  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   46  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   47  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
   48  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
   49  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
   50  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
   51  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
   52  */
   53 
   54 /*
   55  * GEnesis registers. The GEnesis chip has a 256-byte I/O window
   56  * but internally it has a 16K register space. This 16K space is
   57  * divided into 128-byte blocks. The first 128 bytes of the I/O
   58  * window represent the first block, which is permanently mapped
   59  * at the start of the window. The other 127 blocks can be mapped
   60  * to the second 128 bytes of the I/O window by setting the desired
   61  * block value in the RAP register in block 0. Not all of the 127
   62  * blocks are actually used. Most registers are 32 bits wide, but
   63  * there are a few 16-bit and 8-bit ones as well.
   64  */
   65 
   66 /* Start of remappable register window. */
   67 #define SK_WIN_BASE             0x0080
   68 
   69 /* Size of a window */
   70 #define SK_WIN_LEN              0x80
   71 
   72 #define SK_WIN_MASK             0x3F80
   73 #define SK_REG_MASK             0x7F
   74 
   75 /* Compute the window of a given register (for the RAP register) */
   76 #define SK_WIN(reg)             (((reg) & SK_WIN_MASK) / SK_WIN_LEN)
   77 
   78 /* Compute the relative offset of a register within the window */
   79 #define SK_REG(reg)             ((reg) & SK_REG_MASK)
   80 
   81 #define SK_PORT_A       0
   82 #define SK_PORT_B       1
   83 
   84 /*
   85  * Compute offset of port-specific register. Since there are two
   86  * ports, there are two of some GEnesis modules (e.g. two sets of
   87  * DMA queues, two sets of FIFO control registers, etc...). Normally,
   88  * the block for port 0 is at offset 0x0 and the block for port 1 is
   89  * at offset 0x80 (i.e. the next page over). However for the transmit
   90  * BMUs and RAMbuffers, there are two blocks for each port: one for
   91  * the sync transmit queue and one for the async queue (which we don't
   92  * use). However instead of ordering them like this:
   93  * TX sync 1 / TX sync 2 / TX async 1 / TX async 2
   94  * SysKonnect has instead ordered them like this:
   95  * TX sync 1 / TX async 1 / TX sync 2 / TX async 2
   96  * This means that when referencing the TX BMU and RAMbuffer registers,
   97  * we have to double the block offset (0x80 * 2) in order to reach the
   98  * second queue. This prevents us from using the same formula
   99  * (sk_port * 0x80) to compute the offsets for all of the port-specific
  100  * blocks: we need an extra offset for the BMU and RAMbuffer registers.
  101  * The simplest thing is to provide an extra argument to these macros:
  102  * the 'skip' parameter. The 'skip' value is the number of extra pages
  103  * for skip when computing the port0/port1 offsets. For most registers,
  104  * the skip value is 0; for the BMU and RAMbuffer registers, it's 1.
  105  */
  106 #define SK_IF_READ_4(sc_if, skip, reg)          \
  107         sk_win_read_4(sc_if->sk_softc, reg +    \
  108         ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN))
  109 #define SK_IF_READ_2(sc_if, skip, reg)          \
  110         sk_win_read_2(sc_if->sk_softc, reg +    \
  111         ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN))
  112 #define SK_IF_READ_1(sc_if, skip, reg)          \
  113         sk_win_read_1(sc_if->sk_softc, reg +    \
  114         ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN))
  115 
  116 #define SK_IF_WRITE_4(sc_if, skip, reg, val)    \
  117         sk_win_write_4(sc_if->sk_softc,         \
  118         reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
  119 #define SK_IF_WRITE_2(sc_if, skip, reg, val)    \
  120         sk_win_write_2(sc_if->sk_softc,         \
  121         reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
  122 #define SK_IF_WRITE_1(sc_if, skip, reg, val)    \
  123         sk_win_write_1(sc_if->sk_softc,         \
  124         reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
  125 
  126 /* Block 0 registers, permanently mapped at iobase. */
  127 #define SK_RAP          0x0000
  128 #define SK_CSR          0x0004
  129 #define SK_LED          0x0006
  130 #define SK_ISR          0x0008  /* interrupt source */
  131 #define SK_IMR          0x000C  /* interrupt mask */
  132 #define SK_IESR         0x0010  /* interrupt hardware error source */
  133 #define SK_IEMR         0x0014  /* interrupt hardware error mask */
  134 #define SK_ISSR         0x0018  /* special interrupt source */
  135 #define SK_Y2_ISSR2     0x001C
  136 #define SK_Y2_ISSR3     0x0020
  137 #define SK_Y2_EISR      0x0024
  138 #define SK_Y2_LISR      0x0028
  139 #define SK_Y2_ICR       0x002C
  140 #define SK_XM_IMR0      0x0020
  141 #define SK_XM_ISR0      0x0028
  142 #define SK_XM_PHYADDR0  0x0030
  143 #define SK_XM_PHYDATA0  0x0034
  144 #define SK_XM_IMR1      0x0040
  145 #define SK_XM_ISR1      0x0048
  146 #define SK_XM_PHYADDR1  0x0050
  147 #define SK_XM_PHYDATA1  0x0054
  148 #define SK_BMU_RX_CSR0  0x0060
  149 #define SK_BMU_RX_CSR1  0x0064
  150 #define SK_BMU_TXS_CSR0 0x0068
  151 #define SK_BMU_TXA_CSR0 0x006C
  152 #define SK_BMU_TXS_CSR1 0x0070
  153 #define SK_BMU_TXA_CSR1 0x0074
  154 
  155 /* SK_CSR register */
  156 #define SK_CSR_SW_RESET                 0x0001
  157 #define SK_CSR_SW_UNRESET               0x0002
  158 #define SK_CSR_MASTER_RESET             0x0004
  159 #define SK_CSR_MASTER_UNRESET           0x0008
  160 #define SK_CSR_MASTER_STOP              0x0010
  161 #define SK_CSR_MASTER_DONE              0x0020
  162 #define SK_CSR_SW_IRQ_CLEAR             0x0040
  163 #define SK_CSR_SW_IRQ_SET               0x0080
  164 #define SK_CSR_SLOTSIZE                 0x0100 /* 1 == 64 bits, 0 == 32 */
  165 #define SK_CSR_BUSCLOCK                 0x0200 /* 1 == 33/66 MHz, = 33 */
  166 #define SK_CSR_ASF_OFF                  0x1000
  167 #define SK_CSR_ASF_ON                   0x2000
  168 
  169 /* SK_LED register */
  170 #define SK_LED_GREEN_OFF                0x01
  171 #define SK_LED_GREEN_ON                 0x02
  172 
  173 /* SK_ISR register */
  174 #define SK_ISR_TX2_AS_CHECK             0x00000001
  175 #define SK_ISR_TX2_AS_EOF               0x00000002
  176 #define SK_ISR_TX2_AS_EOB               0x00000004
  177 #define SK_ISR_TX2_S_CHECK              0x00000008
  178 #define SK_ISR_TX2_S_EOF                0x00000010
  179 #define SK_ISR_TX2_S_EOB                0x00000020
  180 #define SK_ISR_TX1_AS_CHECK             0x00000040
  181 #define SK_ISR_TX1_AS_EOF               0x00000080
  182 #define SK_ISR_TX1_AS_EOB               0x00000100
  183 #define SK_ISR_TX1_S_CHECK              0x00000200
  184 #define SK_ISR_TX1_S_EOF                0x00000400
  185 #define SK_ISR_TX1_S_EOB                0x00000800
  186 #define SK_ISR_RX2_CHECK                0x00001000
  187 #define SK_ISR_RX2_EOF                  0x00002000
  188 #define SK_ISR_RX2_EOB                  0x00004000
  189 #define SK_ISR_RX1_CHECK                0x00008000
  190 #define SK_ISR_RX1_EOF                  0x00010000
  191 #define SK_ISR_RX1_EOB                  0x00020000
  192 #define SK_ISR_LINK2_OFLOW              0x00040000
  193 #define SK_ISR_MAC2                     0x00080000
  194 #define SK_ISR_LINK1_OFLOW              0x00100000
  195 #define SK_ISR_MAC1                     0x00200000
  196 #define SK_ISR_TIMER                    0x00400000
  197 #define SK_ISR_EXTERNAL_REG             0x00800000
  198 #define SK_ISR_SW                       0x01000000
  199 #define SK_ISR_I2C_RDY                  0x02000000
  200 #define SK_ISR_TX2_TIMEO                0x04000000
  201 #define SK_ISR_TX1_TIMEO                0x08000000
  202 #define SK_ISR_RX2_TIMEO                0x10000000
  203 #define SK_ISR_RX1_TIMEO                0x20000000
  204 #define SK_ISR_RSVD                     0x40000000
  205 #define SK_ISR_HWERR                    0x80000000
  206 
  207 /* SK_IMR register */
  208 #define SK_IMR_TX2_AS_CHECK             0x00000001
  209 #define SK_IMR_TX2_AS_EOF               0x00000002
  210 #define SK_IMR_TX2_AS_EOB               0x00000004
  211 #define SK_IMR_TX2_S_CHECK              0x00000008
  212 #define SK_IMR_TX2_S_EOF                0x00000010
  213 #define SK_IMR_TX2_S_EOB                0x00000020
  214 #define SK_IMR_TX1_AS_CHECK             0x00000040
  215 #define SK_IMR_TX1_AS_EOF               0x00000080
  216 #define SK_IMR_TX1_AS_EOB               0x00000100
  217 #define SK_IMR_TX1_S_CHECK              0x00000200
  218 #define SK_IMR_TX1_S_EOF                0x00000400
  219 #define SK_IMR_TX1_S_EOB                0x00000800
  220 #define SK_IMR_RX2_CHECK                0x00001000
  221 #define SK_IMR_RX2_EOF                  0x00002000
  222 #define SK_IMR_RX2_EOB                  0x00004000
  223 #define SK_IMR_RX1_CHECK                0x00008000
  224 #define SK_IMR_RX1_EOF                  0x00010000
  225 #define SK_IMR_RX1_EOB                  0x00020000
  226 #define SK_IMR_LINK2_OFLOW              0x00040000
  227 #define SK_IMR_MAC2                     0x00080000
  228 #define SK_IMR_LINK1_OFLOW              0x00100000
  229 #define SK_IMR_MAC1                     0x00200000
  230 #define SK_IMR_TIMER                    0x00400000
  231 #define SK_IMR_EXTERNAL_REG             0x00800000
  232 #define SK_IMR_SW                       0x01000000
  233 #define SK_IMR_I2C_RDY                  0x02000000
  234 #define SK_IMR_TX2_TIMEO                0x04000000
  235 #define SK_IMR_TX1_TIMEO                0x08000000
  236 #define SK_IMR_RX2_TIMEO                0x10000000
  237 #define SK_IMR_RX1_TIMEO                0x20000000
  238 #define SK_IMR_RSVD                     0x40000000
  239 #define SK_IMR_HWERR                    0x80000000
  240 
  241 #define SK_INTRS1       \
  242         (SK_IMR_RX1_EOF|SK_IMR_TX1_S_EOF|SK_IMR_MAC1)
  243 
  244 #define SK_INTRS2       \
  245         (SK_IMR_RX2_EOF|SK_IMR_TX2_S_EOF|SK_IMR_MAC2)
  246 
  247 #define SK_Y2_IMR_TX1_AS_CHECK          0x00000001
  248 #define SK_Y2_IMR_TX1_S_CHECK           0x00000002
  249 #define SK_Y2_IMR_RX1_CHECK             0x00000004
  250 #define SK_Y2_IMR_MAC1                  0x00000008
  251 #define SK_Y2_IMR_PHY1                  0x00000010
  252 #define SK_Y2_IMR_TX2_AS_CHECK          0x00000100
  253 #define SK_Y2_IMR_TX2_S_CHECK           0x00000200
  254 #define SK_Y2_IMR_RX2_CHECK             0x00000400
  255 #define SK_Y2_IMR_MAC2                  0x00000800
  256 #define SK_Y2_IMR_PHY2                  0x00001000
  257 #define SK_Y2_IMR_TIMER                 0x01000000
  258 #define SK_Y2_IMR_SW                    0x02000000
  259 #define SK_Y2_IMR_ASF                   0x20000000
  260 #define SK_Y2_IMR_BMU                   0x40000000
  261 #define SK_Y2_IMR_HWERR                 0x80000000
  262 
  263 #define SK_Y2_INTRS1    \
  264         (SK_Y2_IMR_RX1_CHECK|SK_Y2_IMR_TX1_AS_CHECK \
  265         |SK_Y2_IMR_MAC1|SK_Y2_IMR_PHY1)
  266 
  267 #define SK_Y2_INTRS2    \
  268         (SK_Y2_IMR_RX2_CHECK|SK_Y2_IMR_TX2_AS_CHECK \
  269         |SK_Y2_IMR_MAC2|SK_Y2_IMR_PHY2)
  270 
  271 /* SK_IESR register */
  272 #define SK_IESR_PAR_RX2                 0x00000001
  273 #define SK_IESR_PAR_RX1                 0x00000002
  274 #define SK_IESR_PAR_MAC2                0x00000004
  275 #define SK_IESR_PAR_MAC1                0x00000008
  276 #define SK_IESR_PAR_WR_RAM              0x00000010
  277 #define SK_IESR_PAR_RD_RAM              0x00000020
  278 #define SK_IESR_NO_TSTAMP_MAC2          0x00000040
  279 #define SK_IESR_NO_TSTAMO_MAC1          0x00000080
  280 #define SK_IESR_NO_STS_MAC2             0x00000100
  281 #define SK_IESR_NO_STS_MAC1             0x00000200
  282 #define SK_IESR_IRQ_STS                 0x00000400
  283 #define SK_IESR_MASTERERR               0x00000800
  284 
  285 /* SK_IEMR register */
  286 #define SK_IEMR_PAR_RX2                 0x00000001
  287 #define SK_IEMR_PAR_RX1                 0x00000002
  288 #define SK_IEMR_PAR_MAC2                0x00000004
  289 #define SK_IEMR_PAR_MAC1                0x00000008
  290 #define SK_IEMR_PAR_WR_RAM              0x00000010
  291 #define SK_IEMR_PAR_RD_RAM              0x00000020
  292 #define SK_IEMR_NO_TSTAMP_MAC2          0x00000040
  293 #define SK_IEMR_NO_TSTAMO_MAC1          0x00000080
  294 #define SK_IEMR_NO_STS_MAC2             0x00000100
  295 #define SK_IEMR_NO_STS_MAC1             0x00000200
  296 #define SK_IEMR_IRQ_STS                 0x00000400
  297 #define SK_IEMR_MASTERERR               0x00000800
  298 
  299 /* Block 2 */
  300 #define SK_MAC0_0       0x0100
  301 #define SK_MAC0_1       0x0104
  302 #define SK_MAC1_0       0x0108
  303 #define SK_MAC1_1       0x010C
  304 #define SK_MAC2_0       0x0110
  305 #define SK_MAC2_1       0x0114
  306 #define SK_CONNTYPE     0x0118
  307 #define SK_PMDTYPE      0x0119
  308 #define SK_CONFIG       0x011A
  309 #define SK_CHIPVER      0x011B
  310 #define SK_EPROM0       0x011C
  311 #define SK_EPROM1       0x011D          /* yukon/genesis */
  312 #define SK_Y2_CLKGATE   0x011D          /* yukon 2 */
  313 #define SK_EPROM2       0x011E          /* yukon/genesis */
  314 #define SK_Y2_HWRES     0x011E          /* yukon 2 */
  315 #define SK_EPROM3       0x011F
  316 #define SK_EP_ADDR      0x0120
  317 #define SK_EP_DATA      0x0124
  318 #define SK_EP_LOADCTL   0x0128
  319 #define SK_EP_LOADTST   0x0129
  320 #define SK_TIMERINIT    0x0130
  321 #define SK_TIMER        0x0134
  322 #define SK_TIMERCTL     0x0138
  323 #define SK_TIMERTST     0x0139
  324 #define SK_IMTIMERINIT  0x0140
  325 #define SK_IMTIMER      0x0144
  326 #define SK_IMTIMERCTL   0x0148
  327 #define SK_IMTIMERTST   0x0149
  328 #define SK_IMMR         0x014C
  329 #define SK_IHWEMR       0x0150
  330 #define SK_TESTCTL1     0x0158
  331 #define SK_TESTCTL2     0x0159
  332 #define SK_GPIO         0x015C
  333 #define SK_I2CHWCTL     0x0160
  334 #define SK_I2CHWDATA    0x0164
  335 #define SK_I2CHWIRQ     0x0168
  336 #define SK_I2CSW        0x016C
  337 #define SK_BLNKINIT     0x0170
  338 #define SK_BLNKCOUNT    0x0174
  339 #define SK_BLNKCTL      0x0178
  340 #define SK_BLNKSTS      0x0179
  341 #define SK_BLNKTST      0x017A
  342 
  343 /* Values for SK_CHIPVER */
  344 #define SK_GENESIS              0x0A
  345 #define SK_YUKON                0xB0
  346 #define SK_YUKON_LITE           0xB1
  347 #define SK_YUKON_LP             0xB2
  348 #define SK_YUKON_XL             0xB3
  349 #define SK_YUKON_EC_U           0xB4
  350 #define SK_YUKON_EX             0xB5
  351 #define SK_YUKON_EC             0xB6
  352 #define SK_YUKON_FE             0xB7
  353 
  354 #define SK_IS_GENESIS(sc) \
  355     ((sc)->sk_type == SK_GENESIS)
  356 #define SK_IS_YUKON(sc) \
  357     ((sc)->sk_type >= SK_YUKON && (sc)->sk_type <= SK_YUKON_LP)
  358 #define SK_IS_YUKON2(sc) \
  359     ((sc)->sk_type >= SK_YUKON_XL && (sc)->sk_type <= SK_YUKON_FE)
  360 
  361 /* Known revisions in SK_CONFIG */
  362 #define SK_YUKON_LITE_REV_A0    0x0 /* invented, see test in skc_attach */
  363 #define SK_YUKON_LITE_REV_A1    0x3
  364 #define SK_YUKON_LITE_REV_A3    0x7
  365 
  366 #define SK_YUKON_XL_REV_A0      0x0
  367 #define SK_YUKON_XL_REV_A1      0x1
  368 #define SK_YUKON_XL_REV_A2      0x2
  369 #define SK_YUKON_XL_REV_A3      0x3
  370 
  371 #define SK_YUKON_EC_REV_A1      0x0
  372 #define SK_YUKON_EC_REV_A2      0x1
  373 #define SK_YUKON_EC_REV_A3      0x2
  374 
  375 #define SK_YUKON_EC_U_REV_A0    0x1
  376 #define SK_YUKON_EC_U_REV_A1    0x2
  377 
  378 #define SK_IMCTL_IRQ_CLEAR      0x01
  379 #define SK_IMCTL_STOP           0x02
  380 #define SK_IMCTL_START          0x04
  381 
  382 /* Number of ticks per usec for interrupt moderation */
  383 #define SK_IMTIMER_TICKS_GENESIS        53
  384 #define SK_IMTIMER_TICKS_YUKON          78
  385 #define SK_IMTIMER_TICKS_YUKON_EC       125
  386 #define SK_IM_USECS(x)          ((x) * imtimer_ticks)
  387 
  388 /*
  389  * The SK_EPROM0 register contains a byte that describes the
  390  * amount of SRAM mounted on the NIC. The value also tells if
  391  * the chips are 64K or 128K. This affects the RAMbuffer address
  392  * offset that we need to use.
  393  */
  394 #define SK_RAMSIZE_512K_64      0x1
  395 #define SK_RAMSIZE_1024K_128    0x2
  396 #define SK_RAMSIZE_1024K_64     0x3
  397 #define SK_RAMSIZE_2048K_128    0x4
  398 
  399 #define SK_RBOFF_0              0x0
  400 #define SK_RBOFF_80000          0x80000
  401 
  402 /*
  403  * SK_EEPROM1 contains the PHY type, which may be XMAC for
  404  * fiber-based cards or BCOM for 1000baseT cards with a Broadcom
  405  * PHY.
  406  */
  407 #define SK_PHYTYPE_XMAC         0       /* integeated XMAC II PHY */
  408 #define SK_PHYTYPE_BCOM         1       /* Broadcom BCM5400 */
  409 #define SK_PHYTYPE_LONE         2       /* Level One LXT1000 */
  410 #define SK_PHYTYPE_NAT          3       /* National DP83891 */
  411 #define SK_PHYTYPE_MARV_COPPER  4       /* Marvell 88E1011S */
  412 #define SK_PHYTYPE_MARV_FIBER   5       /* Marvell 88E1011S (fiber) */
  413 
  414 /*
  415  * PHY addresses.
  416  */
  417 #define SK_PHYADDR_XMAC         0x0
  418 #define SK_PHYADDR_BCOM         0x1
  419 #define SK_PHYADDR_LONE         0x3
  420 #define SK_PHYADDR_NAT          0x0
  421 #define SK_PHYADDR_MARV         0x0
  422 
  423 #define SK_CONFIG_SINGLEMAC     0x01
  424 #define SK_CONFIG_DIS_DSL_CLK   0x02
  425 
  426 #define SK_PMD_1000BASETX_ALT   0x31
  427 #define SK_PMD_1000BASECX       0x43
  428 #define SK_PMD_1000BASELX       0x4C
  429 #define SK_PMD_1000BASESX       0x53
  430 #define SK_PMD_1000BASETX       0x54
  431 
  432 /* GPIO bits */
  433 #define SK_GPIO_DAT0            0x00000001
  434 #define SK_GPIO_DAT1            0x00000002
  435 #define SK_GPIO_DAT2            0x00000004
  436 #define SK_GPIO_DAT3            0x00000008
  437 #define SK_GPIO_DAT4            0x00000010
  438 #define SK_GPIO_DAT5            0x00000020
  439 #define SK_GPIO_DAT6            0x00000040
  440 #define SK_GPIO_DAT7            0x00000080
  441 #define SK_GPIO_DAT8            0x00000100
  442 #define SK_GPIO_DAT9            0x00000200
  443 #define SK_GPIO_DIR0            0x00010000
  444 #define SK_GPIO_DIR1            0x00020000
  445 #define SK_GPIO_DIR2            0x00040000
  446 #define SK_GPIO_DIR3            0x00080000
  447 #define SK_GPIO_DIR4            0x00100000
  448 #define SK_GPIO_DIR5            0x00200000
  449 #define SK_GPIO_DIR6            0x00400000
  450 #define SK_GPIO_DIR7            0x00800000
  451 #define SK_GPIO_DIR8            0x01000000
  452 #define SK_GPIO_DIR9           0x02000000
  453 
  454 #define SK_Y2_CLKGATE_LINK2_INACTIVE    0x80    /* port 2 inactive */
  455 #define SK_Y2_CLKGATE_LINK2_GATE_DIS    0x40    /* disable clock gate, 2 */
  456 #define SK_Y2_CLKGATE_LINK2_CORE_DIS    0x20    /* disable core clock, 2 */
  457 #define SK_Y2_CLKGATE_LINK2_PCI_DIS     0x10    /* disable pci clock, 2 */
  458 #define SK_Y2_CLKGATE_LINK1_INACTIVE    0x08    /* port 1 inactive */
  459 #define SK_Y2_CLKGATE_LINK1_GATE_DIS    0x04    /* disable clock gate, 1 */
  460 #define SK_Y2_CLKGATE_LINK1_CORE_DIS    0x02    /* disable core clock, 1 */
  461 #define SK_Y2_CLKGATE_LINK1_PCI_DIS     0x01    /* disable pci clock, 1 */
  462 
  463 #define SK_Y2_HWRES_LINK_1      0x01
  464 #define SK_Y2_HWRES_LINK_2      0x02
  465 #define SK_Y2_HWRES_LINK_MASK   (SK_Y2_HWRES_LINK_1 | SK_Y2_HWRES_LINK_2)
  466 #define SK_Y2_HWRES_LINK_DUAL   (SK_Y2_HWRES_LINK_1 | SK_Y2_HWRES_LINK_2)
  467 
  468 /* Block 3 Ram interface and MAC arbiter registers */
  469 #define SK_RAMADDR      0x0180
  470 #define SK_RAMDATA0     0x0184
  471 #define SK_RAMDATA1     0x0188
  472 #define SK_TO0          0x0190
  473 #define SK_TO1          0x0191
  474 #define SK_TO2          0x0192
  475 #define SK_TO3          0x0193
  476 #define SK_TO4          0x0194
  477 #define SK_TO5          0x0195
  478 #define SK_TO6          0x0196
  479 #define SK_TO7          0x0197
  480 #define SK_TO8          0x0198
  481 #define SK_TO9          0x0199
  482 #define SK_TO10         0x019A
  483 #define SK_TO11         0x019B
  484 #define SK_RITIMEO_TMR  0x019C
  485 #define SK_RAMCTL       0x01A0
  486 #define SK_RITIMER_TST  0x01A2
  487 
  488 #define SK_RAMCTL_RESET         0x0001
  489 #define SK_RAMCTL_UNRESET       0x0002
  490 #define SK_RAMCTL_CLR_IRQ_WPAR  0x0100
  491 #define SK_RAMCTL_CLR_IRQ_RPAR  0x0200
  492 
  493 /* Mac arbiter registers */
  494 #define SK_MINIT_RX1    0x01B0
  495 #define SK_MINIT_RX2    0x01B1
  496 #define SK_MINIT_TX1    0x01B2
  497 #define SK_MINIT_TX2    0x01B3
  498 #define SK_MTIMEO_RX1   0x01B4
  499 #define SK_MTIMEO_RX2   0x01B5
  500 #define SK_MTIMEO_TX1   0x01B6
  501 #define SK_MTIEMO_TX2   0x01B7
  502 #define SK_MACARB_CTL   0x01B8
  503 #define SK_MTIMER_TST   0x01BA
  504 #define SK_RCINIT_RX1   0x01C0
  505 #define SK_RCINIT_RX2   0x01C1
  506 #define SK_RCINIT_TX1   0x01C2
  507 #define SK_RCINIT_TX2   0x01C3
  508 #define SK_RCTIMEO_RX1  0x01C4
  509 #define SK_RCTIMEO_RX2  0x01C5
  510 #define SK_RCTIMEO_TX1  0x01C6
  511 #define SK_RCTIMEO_TX2  0x01C7
  512 #define SK_RECOVERY_CTL 0x01C8
  513 #define SK_RCTIMER_TST  0x01CA
  514 
  515 /* Packet arbiter registers */
  516 #define SK_RXPA1_TINIT  0x01D0
  517 #define SK_RXPA2_TINIT  0x01D4
  518 #define SK_TXPA1_TINIT  0x01D8
  519 #define SK_TXPA2_TINIT  0x01DC
  520 #define SK_RXPA1_TIMEO  0x01E0
  521 #define SK_RXPA2_TIMEO  0x01E4
  522 #define SK_TXPA1_TIMEO  0x01E8
  523 #define SK_TXPA2_TIMEO  0x01EC
  524 #define SK_PKTARB_CTL   0x01F0
  525 #define SK_PKTATB_TST   0x01F2
  526 
  527 #define SK_PKTARB_TIMEOUT       0x2000
  528 
  529 #define SK_PKTARBCTL_RESET              0x0001
  530 #define SK_PKTARBCTL_UNRESET            0x0002
  531 #define SK_PKTARBCTL_RXTO1_OFF          0x0004
  532 #define SK_PKTARBCTL_RXTO1_ON           0x0008
  533 #define SK_PKTARBCTL_RXTO2_OFF          0x0010
  534 #define SK_PKTARBCTL_RXTO2_ON           0x0020
  535 #define SK_PKTARBCTL_TXTO1_OFF          0x0040
  536 #define SK_PKTARBCTL_TXTO1_ON           0x0080
  537 #define SK_PKTARBCTL_TXTO2_OFF          0x0100
  538 #define SK_PKTARBCTL_TXTO2_ON           0x0200
  539 #define SK_PKTARBCTL_CLR_IRQ_RXTO1      0x0400
  540 #define SK_PKTARBCTL_CLR_IRQ_RXTO2      0x0800
  541 #define SK_PKTARBCTL_CLR_IRQ_TXTO1      0x1000
  542 #define SK_PKTARBCTL_CLR_IRQ_TXTO2      0x2000
  543 
  544 #define SK_MINIT_XMAC_B2        54
  545 #define SK_MINIT_XMAC_C1        63
  546 
  547 #define SK_MACARBCTL_RESET      0x0001
  548 #define SK_MACARBCTL_UNRESET    0x0002
  549 #define SK_MACARBCTL_FASTOE_OFF 0x0004
  550 #define SK_MACARBCRL_FASTOE_ON  0x0008
  551 
  552 #define SK_RCINIT_XMAC_B2       54
  553 #define SK_RCINIT_XMAC_C1       0
  554 
  555 #define SK_RECOVERYCTL_RX1_OFF  0x0001
  556 #define SK_RECOVERYCTL_RX1_ON   0x0002
  557 #define SK_RECOVERYCTL_RX2_OFF  0x0004
  558 #define SK_RECOVERYCTL_RX2_ON   0x0008
  559 #define SK_RECOVERYCTL_TX1_OFF  0x0010
  560 #define SK_RECOVERYCTL_TX1_ON   0x0020
  561 #define SK_RECOVERYCTL_TX2_OFF  0x0040
  562 #define SK_RECOVERYCTL_TX2_ON   0x0080
  563 
  564 #define SK_RECOVERY_XMAC_B2                             \
  565         (SK_RECOVERYCTL_RX1_ON|SK_RECOVERYCTL_RX2_ON|   \
  566         SK_RECOVERYCTL_TX1_ON|SK_RECOVERYCTL_TX2_ON)
  567 
  568 #define SK_RECOVERY_XMAC_C1                             \
  569         (SK_RECOVERYCTL_RX1_OFF|SK_RECOVERYCTL_RX2_OFF| \
  570         SK_RECOVERYCTL_TX1_OFF|SK_RECOVERYCTL_TX2_OFF)
  571 
  572 /* Block 4 -- TX Arbiter MAC 1 */
  573 #define SK_TXAR1_TIMERINIT      0x0200
  574 #define SK_TXAR1_TIMERVAL       0x0204
  575 #define SK_TXAR1_LIMITINIT      0x0208
  576 #define SK_TXAR1_LIMITCNT       0x020C
  577 #define SK_TXAR1_COUNTERCTL     0x0210
  578 #define SK_TXAR1_COUNTERTST     0x0212
  579 #define SK_TXAR1_COUNTERSTS     0x0212
  580 
  581 /* Block 5 -- TX Arbiter MAC 2 */
  582 #define SK_TXAR2_TIMERINIT      0x0280
  583 #define SK_TXAR2_TIMERVAL       0x0284
  584 #define SK_TXAR2_LIMITINIT      0x0288
  585 #define SK_TXAR2_LIMITCNT       0x028C
  586 #define SK_TXAR2_COUNTERCTL     0x0290
  587 #define SK_TXAR2_COUNTERTST     0x0291
  588 #define SK_TXAR2_COUNTERSTS     0x0292
  589 
  590 #define SK_TXARCTL_OFF          0x01
  591 #define SK_TXARCTL_ON           0x02
  592 #define SK_TXARCTL_RATECTL_OFF  0x04
  593 #define SK_TXARCTL_RATECTL_ON   0x08
  594 #define SK_TXARCTL_ALLOC_OFF    0x10
  595 #define SK_TXARCTL_ALLOC_ON     0x20
  596 #define SK_TXARCTL_FSYNC_OFF    0x40
  597 #define SK_TXARCTL_FSYNC_ON     0x80
  598 
  599 /* Block 6 -- External registers */
  600 #define SK_EXTREG_BASE  0x300
  601 #define SK_EXTREG_END   0x37C
  602 
  603 /* Block 7 -- PCI config registers */
  604 #define SK_PCI_BASE     0x0380
  605 #define SK_PCI_END      0x03FC
  606 
  607 /* Compute offset of mirrored PCI register */
  608 #define SK_PCI_REG(reg)         ((reg) + SK_PCI_BASE)
  609 
  610 /* Block 8 -- RX queue 1 */
  611 #define SK_RXQ1_BUFCNT          0x0400
  612 #define SK_RXQ1_BUFCTL          0x0402
  613 #define SK_RXQ1_NEXTDESC        0x0404
  614 #define SK_RXQ1_RXBUF_LO        0x0408
  615 #define SK_RXQ1_RXBUF_HI        0x040C
  616 #define SK_RXQ1_RXSTAT          0x0410
  617 #define SK_RXQ1_TIMESTAMP       0x0414
  618 #define SK_RXQ1_CSUM1           0x0418
  619 #define SK_RXQ1_CSUM2           0x041A
  620 #define SK_RXQ1_CSUM1_START     0x041C
  621 #define SK_RXQ1_CSUM2_START     0x041E
  622 #define SK_RXQ1_CURADDR_LO      0x0420
  623 #define SK_RXQ1_CURADDR_HI      0x0424
  624 #define SK_RXQ1_CURCNT_LO       0x0428
  625 #define SK_RXQ1_CURCNT_HI       0x042C
  626 #define SK_RXQ1_CURBYTES        0x0430
  627 #define SK_RXQ1_BMU_CSR         0x0434
  628 #define SK_RXQ1_WATERMARK       0x0438
  629 #define SK_RXQ1_FLAG            0x043A
  630 #define SK_RXQ1_TEST1           0x043C
  631 #define SK_RXQ1_TEST2           0x0440
  632 #define SK_RXQ1_TEST3           0x0444
  633 /* yukon-2 only */
  634 #define SK_RXQ1_Y2_WM           0x0440
  635 #define SK_RXQ1_Y2_AL           0x0442
  636 #define SK_RXQ1_Y2_RSP          0x0444
  637 #define SK_RXQ1_Y2_RSL          0x0446
  638 #define SK_RXQ1_Y2_RP           0x0448
  639 #define SK_RXQ1_Y2_RL           0x044A
  640 #define SK_RXQ1_Y2_WP           0x044C
  641 #define SK_RXQ1_Y2_WSP          0x044D
  642 #define SK_RXQ1_Y2_WL           0x044E
  643 #define SK_RXQ1_Y2_WSL          0x044F
  644 /* yukon-2 only (prefetch unit) */
  645 #define SK_RXQ1_Y2_PREF_CSR     0x0450
  646 #define SK_RXQ1_Y2_PREF_LIDX    0x0454
  647 #define SK_RXQ1_Y2_PREF_ADDRLO  0x0458
  648 #define SK_RXQ1_Y2_PREF_ADDRHI  0x045C
  649 #define SK_RXQ1_Y2_PREF_GETIDX  0x0460
  650 #define SK_RXQ1_Y2_PREF_PUTIDX  0x0464
  651 #define SK_RXQ1_Y2_PREF_FIFOWP  0x0470
  652 #define SK_RXQ1_Y2_PREF_FIFORP  0x0474
  653 #define SK_RXQ1_Y2_PREF_FIFOWM  0x0478
  654 #define SK_RXQ1_Y2_PREF_FIFOLV  0x047C
  655 
  656 /* Block 9 -- RX queue 2 */
  657 #define SK_RXQ2_BUFCNT          0x0480
  658 #define SK_RXQ2_BUFCTL          0x0482
  659 #define SK_RXQ2_NEXTDESC        0x0484
  660 #define SK_RXQ2_RXBUF_LO        0x0488
  661 #define SK_RXQ2_RXBUF_HI        0x048C
  662 #define SK_RXQ2_RXSTAT          0x0490
  663 #define SK_RXQ2_TIMESTAMP       0x0494
  664 #define SK_RXQ2_CSUM1           0x0498
  665 #define SK_RXQ2_CSUM2           0x049A
  666 #define SK_RXQ2_CSUM1_START     0x049C
  667 #define SK_RXQ2_CSUM2_START     0x049E
  668 #define SK_RXQ2_CURADDR_LO      0x04A0
  669 #define SK_RXQ2_CURADDR_HI      0x04A4
  670 #define SK_RXQ2_CURCNT_LO       0x04A8
  671 #define SK_RXQ2_CURCNT_HI       0x04AC
  672 #define SK_RXQ2_CURBYTES        0x04B0
  673 #define SK_RXQ2_BMU_CSR         0x04B4
  674 #define SK_RXQ2_WATERMARK       0x04B8
  675 #define SK_RXQ2_FLAG            0x04BA
  676 #define SK_RXQ2_TEST1           0x04BC
  677 #define SK_RXQ2_TEST2           0x04C0
  678 #define SK_RXQ2_TEST3           0x04C4
  679 /* yukon-2 only */
  680 #define SK_RXQ2_Y2_WM           0x04C0
  681 #define SK_RXQ2_Y2_AL           0x04C2
  682 #define SK_RXQ2_Y2_RSP          0x04C4
  683 #define SK_RXQ2_Y2_RSL          0x04C6
  684 #define SK_RXQ2_Y2_RP           0x04C8
  685 #define SK_RXQ2_Y2_RL           0x04CA
  686 #define SK_RXQ2_Y2_WP           0x04CC
  687 #define SK_RXQ2_Y2_WSP          0x04CD
  688 #define SK_RXQ2_Y2_WL           0x04CE
  689 #define SK_RXQ2_Y2_WSL          0x04CF
  690 /* yukon-2 only (prefetch unit) */
  691 #define SK_RXQ2_Y2_PREF_CSR     0x04D0
  692 #define SK_RXQ2_Y2_PREF_LIDX    0x04D4
  693 #define SK_RXQ2_Y2_PREF_ADDRLO  0x04D8
  694 #define SK_RXQ2_Y2_PREF_ADDRHI  0x04DC
  695 #define SK_RXQ2_Y2_PREF_GETIDX  0x04E0
  696 #define SK_RXQ2_Y2_PREF_PUTIDX  0x04E4
  697 #define SK_RXQ2_Y2_PREF_FIFOWP  0x04F0
  698 #define SK_RXQ2_Y2_PREF_FIFORP  0x04F4
  699 #define SK_RXQ2_Y2_PREF_FIFOWM  0x04F8
  700 #define SK_RXQ2_Y2_PREF_FIFOLV  0x04FC
  701 
  702 #define SK_RXBMU_CLR_IRQ_ERR            0x00000001
  703 #define SK_RXBMU_CLR_IRQ_EOF            0x00000002
  704 #define SK_RXBMU_CLR_IRQ_EOB            0x00000004
  705 #define SK_RXBMU_CLR_IRQ_PAR            0x00000008
  706 #define SK_RXBMU_RX_START               0x00000010
  707 #define SK_RXBMU_RX_STOP                0x00000020
  708 #define SK_RXBMU_POLL_OFF               0x00000040
  709 #define SK_RXBMU_POLL_ON                0x00000080
  710 #define SK_RXBMU_TRANSFER_SM_RESET      0x00000100
  711 #define SK_RXBMU_TRANSFER_SM_UNRESET    0x00000200
  712 #define SK_RXBMU_DESCWR_SM_RESET        0x00000400
  713 #define SK_RXBMU_DESCWR_SM_UNRESET      0x00000800
  714 #define SK_RXBMU_DESCRD_SM_RESET        0x00001000
  715 #define SK_RXBMU_DESCRD_SM_UNRESET      0x00002000
  716 #define SK_RXBMU_SUPERVISOR_SM_RESET    0x00004000
  717 #define SK_RXBMU_SUPERVISOR_SM_UNRESET  0x00008000
  718 #define SK_RXBMU_PFI_SM_RESET           0x00010000
  719 #define SK_RXBMU_PFI_SM_UNRESET         0x00020000
  720 #define SK_RXBMU_FIFO_RESET             0x00040000
  721 #define SK_RXBMU_FIFO_UNRESET           0x00080000
  722 #define SK_RXBMU_DESC_RESET             0x00100000
  723 #define SK_RXBMU_DESC_UNRESET           0x00200000
  724 #define SK_RXBMU_SUPERVISOR_IDLE        0x01000000
  725 
  726 #define SK_RXBMU_ONLINE         \
  727         (SK_RXBMU_TRANSFER_SM_UNRESET|SK_RXBMU_DESCWR_SM_UNRESET|       \
  728         SK_RXBMU_DESCRD_SM_UNRESET|SK_RXBMU_SUPERVISOR_SM_UNRESET|      \
  729         SK_RXBMU_PFI_SM_UNRESET|SK_RXBMU_FIFO_UNRESET|                  \
  730         SK_RXBMU_DESC_UNRESET)
  731 
  732 #define SK_RXBMU_OFFLINE                \
  733         (SK_RXBMU_TRANSFER_SM_RESET|SK_RXBMU_DESCWR_SM_RESET|   \
  734         SK_RXBMU_DESCRD_SM_RESET|SK_RXBMU_SUPERVISOR_SM_RESET|  \
  735         SK_RXBMU_PFI_SM_RESET|SK_RXBMU_FIFO_RESET|              \
  736         SK_RXBMU_DESC_RESET)
  737 
  738 /* Block 12 -- TX sync queue 1 */
  739 #define SK_TXQS1_BUFCNT         0x0600
  740 #define SK_TXQS1_BUFCTL         0x0602
  741 #define SK_TXQS1_NEXTDESC       0x0604
  742 #define SK_TXQS1_RXBUF_LO       0x0608
  743 #define SK_TXQS1_RXBUF_HI       0x060C
  744 #define SK_TXQS1_RXSTAT         0x0610
  745 #define SK_TXQS1_CSUM_STARTVAL  0x0614
  746 #define SK_TXQS1_CSUM_STARTPOS  0x0618
  747 #define SK_TXQS1_CSUM_WRITEPOS  0x061A
  748 #define SK_TXQS1_CURADDR_LO     0x0620
  749 #define SK_TXQS1_CURADDR_HI     0x0624
  750 #define SK_TXQS1_CURCNT_LO      0x0628
  751 #define SK_TXQS1_CURCNT_HI      0x062C
  752 #define SK_TXQS1_CURBYTES       0x0630
  753 #define SK_TXQS1_BMU_CSR        0x0634
  754 #define SK_TXQS1_WATERMARK      0x0638
  755 #define SK_TXQS1_FLAG           0x063A
  756 #define SK_TXQS1_TEST1          0x063C
  757 #define SK_TXQS1_TEST2          0x0640
  758 #define SK_TXQS1_TEST3          0x0644
  759 /* yukon-2 only */
  760 #define SK_TXQS1_Y2_WM          0x0640
  761 #define SK_TXQS1_Y2_AL          0x0642
  762 #define SK_TXQS1_Y2_RSP         0x0644
  763 #define SK_TXQS1_Y2_RSL         0x0646
  764 #define SK_TXQS1_Y2_RP          0x0648
  765 #define SK_TXQS1_Y2_RL          0x064A
  766 #define SK_TXQS1_Y2_WP          0x064C
  767 #define SK_TXQS1_Y2_WSP         0x064D
  768 #define SK_TXQS1_Y2_WL          0x064E
  769 #define SK_TXQS1_Y2_WSL         0x064F
  770 /* yukon-2 only (prefetch unit) */
  771 #define SK_TXQS1_Y2_PREF_CSR    0x0650
  772 #define SK_TXQS1_Y2_PREF_LIDX   0x0654
  773 #define SK_TXQS1_Y2_PREF_ADDRLO 0x0658
  774 #define SK_TXQS1_Y2_PREF_ADDRHI 0x065C
  775 #define SK_TXQS1_Y2_PREF_GETIDX 0x0660
  776 #define SK_TXQS1_Y2_PREF_PUTIDX 0x0664
  777 #define SK_TXQS1_Y2_PREF_FIFOWP 0x0670
  778 #define SK_TXQS1_Y2_PREF_FIFORP 0x0674
  779 #define SK_TXQS1_Y2_PREF_FIFOWM 0x0678
  780 #define SK_TXQS1_Y2_PREF_FIFOLV 0x067C
  781 
  782 /* Block 13 -- TX async queue 1 */
  783 #define SK_TXQA1_BUFCNT         0x0680
  784 #define SK_TXQA1_BUFCTL         0x0682
  785 #define SK_TXQA1_NEXTDESC       0x0684
  786 #define SK_TXQA1_RXBUF_LO       0x0688
  787 #define SK_TXQA1_RXBUF_HI       0x068C
  788 #define SK_TXQA1_RXSTAT         0x0690
  789 #define SK_TXQA1_CSUM_STARTVAL  0x0694
  790 #define SK_TXQA1_CSUM_STARTPOS  0x0698
  791 #define SK_TXQA1_CSUM_WRITEPOS  0x069A
  792 #define SK_TXQA1_CURADDR_LO     0x06A0
  793 #define SK_TXQA1_CURADDR_HI     0x06A4
  794 #define SK_TXQA1_CURCNT_LO      0x06A8
  795 #define SK_TXQA1_CURCNT_HI      0x06AC
  796 #define SK_TXQA1_CURBYTES       0x06B0
  797 #define SK_TXQA1_BMU_CSR        0x06B4
  798 #define SK_TXQA1_WATERMARK      0x06B8
  799 #define SK_TXQA1_FLAG           0x06BA
  800 #define SK_TXQA1_TEST1          0x06BC
  801 #define SK_TXQA1_TEST2          0x06C0
  802 #define SK_TXQA1_TEST3          0x06C4
  803 /* yukon-2 only */
  804 #define SK_TXQA1_Y2_WM          0x06C0
  805 #define SK_TXQA1_Y2_AL          0x06C2
  806 #define SK_TXQA1_Y2_RSP         0x06C4
  807 #define SK_TXQA1_Y2_RSL         0x06C6
  808 #define SK_TXQA1_Y2_RP          0x06C8
  809 #define SK_TXQA1_Y2_RL          0x06CA
  810 #define SK_TXQA1_Y2_WP          0x06CC
  811 #define SK_TXQA1_Y2_WSP         0x06CD
  812 #define SK_TXQA1_Y2_WL          0x06CE
  813 #define SK_TXQA1_Y2_WSL         0x06CF
  814 /* yukon-2 only (prefetch unit) */
  815 #define SK_TXQA1_Y2_PREF_CSR    0x06D0
  816 #define SK_TXQA1_Y2_PREF_LIDX   0x06D4
  817 #define SK_TXQA1_Y2_PREF_ADDRLO 0x06D8
  818 #define SK_TXQA1_Y2_PREF_ADDRHI 0x06DC
  819 #define SK_TXQA1_Y2_PREF_GETIDX 0x06E0
  820 #define SK_TXQA1_Y2_PREF_PUTIDX 0x06E4
  821 #define SK_TXQA1_Y2_PREF_FIFOWP 0x06F0
  822 #define SK_TXQA1_Y2_PREF_FIFORP 0x06F4
  823 #define SK_TXQA1_Y2_PREF_FIFOWM 0x06F8
  824 #define SK_TXQA1_Y2_PREF_FIFOLV 0x06FC
  825 
  826 /* Block 14 -- TX sync queue 2 */
  827 #define SK_TXQS2_BUFCNT         0x0700
  828 #define SK_TXQS2_BUFCTL         0x0702
  829 #define SK_TXQS2_NEXTDESC       0x0704
  830 #define SK_TXQS2_RXBUF_LO       0x0708
  831 #define SK_TXQS2_RXBUF_HI       0x070C
  832 #define SK_TXQS2_RXSTAT         0x0710
  833 #define SK_TXQS2_CSUM_STARTVAL  0x0714
  834 #define SK_TXQS2_CSUM_STARTPOS  0x0718
  835 #define SK_TXQS2_CSUM_WRITEPOS  0x071A
  836 #define SK_TXQS2_CURADDR_LO     0x0720
  837 #define SK_TXQS2_CURADDR_HI     0x0724
  838 #define SK_TXQS2_CURCNT_LO      0x0728
  839 #define SK_TXQS2_CURCNT_HI      0x072C
  840 #define SK_TXQS2_CURBYTES       0x0730
  841 #define SK_TXQS2_BMU_CSR        0x0734
  842 #define SK_TXQS2_WATERMARK      0x0738
  843 #define SK_TXQS2_FLAG           0x073A
  844 #define SK_TXQS2_TEST1          0x073C
  845 #define SK_TXQS2_TEST2          0x0740
  846 #define SK_TXQS2_TEST3          0x0744
  847 /* yukon-2 only */
  848 #define SK_TXQS2_Y2_WM          0x0740
  849 #define SK_TXQS2_Y2_AL          0x0742
  850 #define SK_TXQS2_Y2_RSP         0x0744
  851 #define SK_TXQS2_Y2_RSL         0x0746
  852 #define SK_TXQS2_Y2_RP          0x0748
  853 #define SK_TXQS2_Y2_RL          0x074A
  854 #define SK_TXQS2_Y2_WP          0x074C
  855 #define SK_TXQS2_Y2_WSP         0x074D
  856 #define SK_TXQS2_Y2_WL          0x074E
  857 #define SK_TXQS2_Y2_WSL         0x074F
  858 /* yukon-2 only (prefetch unit) */
  859 #define SK_TXQS2_Y2_PREF_CSR    0x0750
  860 #define SK_TXQS2_Y2_PREF_LIDX   0x0754
  861 #define SK_TXQS2_Y2_PREF_ADDRLO 0x0758
  862 #define SK_TXQS2_Y2_PREF_ADDRHI 0x075C
  863 #define SK_TXQS2_Y2_PREF_GETIDX 0x0760
  864 #define SK_TXQS2_Y2_PREF_PUTIDX 0x0764
  865 #define SK_TXQS2_Y2_PREF_FIFOWP 0x0770
  866 #define SK_TXQS2_Y2_PREF_FIFORP 0x0774
  867 #define SK_TXQS2_Y2_PREF_FIFOWM 0x0778
  868 #define SK_TXQS2_Y2_PREF_FIFOLV 0x077C
  869 
  870 /* Block 15 -- TX async queue 2 */
  871 #define SK_TXQA2_BUFCNT         0x0780
  872 #define SK_TXQA2_BUFCTL         0x0782
  873 #define SK_TXQA2_NEXTDESC       0x0784
  874 #define SK_TXQA2_RXBUF_LO       0x0788
  875 #define SK_TXQA2_RXBUF_HI       0x078C
  876 #define SK_TXQA2_RXSTAT         0x0790
  877 #define SK_TXQA2_CSUM_STARTVAL  0x0794
  878 #define SK_TXQA2_CSUM_STARTPOS  0x0798
  879 #define SK_TXQA2_CSUM_WRITEPOS  0x079A
  880 #define SK_TXQA2_CURADDR_LO     0x07A0
  881 #define SK_TXQA2_CURADDR_HI     0x07A4
  882 #define SK_TXQA2_CURCNT_LO      0x07A8
  883 #define SK_TXQA2_CURCNT_HI      0x07AC
  884 #define SK_TXQA2_CURBYTES       0x07B0
  885 #define SK_TXQA2_BMU_CSR        0x07B4
  886 #define SK_TXQA2_WATERMARK      0x07B8
  887 #define SK_TXQA2_FLAG           0x07BA
  888 #define SK_TXQA2_TEST1          0x07BC
  889 #define SK_TXQA2_TEST2          0x07C0
  890 #define SK_TXQA2_TEST3          0x07C4
  891 /* yukon-2 only */
  892 #define SK_TXQA2_Y2_WM          0x07C0
  893 #define SK_TXQA2_Y2_AL          0x07C2
  894 #define SK_TXQA2_Y2_RSP         0x07C4
  895 #define SK_TXQA2_Y2_RSL         0x07C6
  896 #define SK_TXQA2_Y2_RP          0x07C8
  897 #define SK_TXQA2_Y2_RL          0x07CA
  898 #define SK_TXQA2_Y2_WP          0x07CC
  899 #define SK_TXQA2_Y2_WSP         0x07CD
  900 #define SK_TXQA2_Y2_WL          0x07CE
  901 #define SK_TXQA2_Y2_WSL         0x07CF
  902 /* yukon-2 only (prefetch unit) */
  903 #define SK_TXQA2_Y2_PREF_CSR    0x07D0
  904 #define SK_TXQA2_Y2_PREF_LIDX   0x07D4
  905 #define SK_TXQA2_Y2_PREF_ADDRLO 0x07D8
  906 #define SK_TXQA2_Y2_PREF_ADDRHI 0x07DC
  907 #define SK_TXQA2_Y2_PREF_GETIDX 0x07E0
  908 #define SK_TXQA2_Y2_PREF_PUTIDX 0x07E4
  909 #define SK_TXQA2_Y2_PREF_FIFOWP 0x07F0
  910 #define SK_TXQA2_Y2_PREF_FIFORP 0x07F4
  911 #define SK_TXQA2_Y2_PREF_FIFOWM 0x07F8
  912 #define SK_TXQA2_Y2_PREF_FIFOLV 0x07FC
  913 
  914 #define SK_TXBMU_CLR_IRQ_ERR            0x00000001
  915 #define SK_TXBMU_CLR_IRQ_EOF            0x00000002
  916 #define SK_TXBMU_CLR_IRQ_EOB            0x00000004
  917 #define SK_TXBMU_TX_START               0x00000010
  918 #define SK_TXBMU_TX_STOP                0x00000020
  919 #define SK_TXBMU_POLL_OFF               0x00000040
  920 #define SK_TXBMU_POLL_ON                0x00000080
  921 #define SK_TXBMU_TRANSFER_SM_RESET      0x00000100
  922 #define SK_TXBMU_TRANSFER_SM_UNRESET    0x00000200
  923 #define SK_TXBMU_DESCWR_SM_RESET        0x00000400
  924 #define SK_TXBMU_DESCWR_SM_UNRESET      0x00000800
  925 #define SK_TXBMU_DESCRD_SM_RESET        0x00001000
  926 #define SK_TXBMU_DESCRD_SM_UNRESET      0x00002000
  927 #define SK_TXBMU_SUPERVISOR_SM_RESET    0x00004000
  928 #define SK_TXBMU_SUPERVISOR_SM_UNRESET  0x00008000
  929 #define SK_TXBMU_PFI_SM_RESET           0x00010000
  930 #define SK_TXBMU_PFI_SM_UNRESET         0x00020000
  931 #define SK_TXBMU_FIFO_RESET             0x00040000
  932 #define SK_TXBMU_FIFO_UNRESET           0x00080000
  933 #define SK_TXBMU_DESC_RESET             0x00100000
  934 #define SK_TXBMU_DESC_UNRESET           0x00200000
  935 #define SK_TXBMU_SUPERVISOR_IDLE        0x01000000
  936 
  937 #define SK_TXBMU_ONLINE         \
  938         (SK_TXBMU_TRANSFER_SM_UNRESET|SK_TXBMU_DESCWR_SM_UNRESET|       \
  939         SK_TXBMU_DESCRD_SM_UNRESET|SK_TXBMU_SUPERVISOR_SM_UNRESET|      \
  940         SK_TXBMU_PFI_SM_UNRESET|SK_TXBMU_FIFO_UNRESET|                  \
  941         SK_TXBMU_DESC_UNRESET|SK_TXBMU_POLL_ON)
  942 
  943 #define SK_TXBMU_OFFLINE                \
  944         (SK_TXBMU_TRANSFER_SM_RESET|SK_TXBMU_DESCWR_SM_RESET|   \
  945         SK_TXBMU_DESCRD_SM_RESET|SK_TXBMU_SUPERVISOR_SM_RESET|  \
  946         SK_TXBMU_PFI_SM_RESET|SK_TXBMU_FIFO_RESET|              \
  947         SK_TXBMU_DESC_RESET|SK_TXBMU_POLL_OFF)
  948 
  949 /* Block 16 -- Receive RAMbuffer 1 */
  950 #define SK_RXRB1_START          0x0800
  951 #define SK_RXRB1_END            0x0804
  952 #define SK_RXRB1_WR_PTR         0x0808
  953 #define SK_RXRB1_RD_PTR         0x080C
  954 #define SK_RXRB1_UTHR_PAUSE     0x0810
  955 #define SK_RXRB1_LTHR_PAUSE     0x0814
  956 #define SK_RXRB1_UTHR_HIPRIO    0x0818
  957 #define SK_RXRB1_UTHR_LOPRIO    0x081C
  958 #define SK_RXRB1_PKTCNT         0x0820
  959 #define SK_RXRB1_LVL            0x0824
  960 #define SK_RXRB1_CTLTST         0x0828
  961 
  962 /* Block 17 -- Receive RAMbuffer 2 */
  963 #define SK_RXRB2_START          0x0880
  964 #define SK_RXRB2_END            0x0884
  965 #define SK_RXRB2_WR_PTR         0x0888
  966 #define SK_RXRB2_RD_PTR         0x088C
  967 #define SK_RXRB2_UTHR_PAUSE     0x0890
  968 #define SK_RXRB2_LTHR_PAUSE     0x0894
  969 #define SK_RXRB2_UTHR_HIPRIO    0x0898
  970 #define SK_RXRB2_UTHR_LOPRIO    0x089C
  971 #define SK_RXRB2_PKTCNT         0x08A0
  972 #define SK_RXRB2_LVL            0x08A4
  973 #define SK_RXRB2_CTLTST         0x08A8
  974 
  975 /* Block 20 -- Sync. Transmit RAMbuffer 1 */
  976 #define SK_TXRBS1_START         0x0A00
  977 #define SK_TXRBS1_END           0x0A04
  978 #define SK_TXRBS1_WR_PTR        0x0A08
  979 #define SK_TXRBS1_RD_PTR        0x0A0C
  980 #define SK_TXRBS1_PKTCNT        0x0A20
  981 #define SK_TXRBS1_LVL           0x0A24
  982 #define SK_TXRBS1_CTLTST        0x0A28
  983 
  984 /* Block 21 -- Async. Transmit RAMbuffer 1 */
  985 #define SK_TXRBA1_START         0x0A80
  986 #define SK_TXRBA1_END           0x0A84
  987 #define SK_TXRBA1_WR_PTR        0x0A88
  988 #define SK_TXRBA1_RD_PTR        0x0A8C
  989 #define SK_TXRBA1_PKTCNT        0x0AA0
  990 #define SK_TXRBA1_LVL           0x0AA4
  991 #define SK_TXRBA1_CTLTST        0x0AA8
  992 
  993 /* Block 22 -- Sync. Transmit RAMbuffer 2 */
  994 #define SK_TXRBS2_START         0x0B00
  995 #define SK_TXRBS2_END           0x0B04
  996 #define SK_TXRBS2_WR_PTR        0x0B08
  997 #define SK_TXRBS2_RD_PTR        0x0B0C
  998 #define SK_TXRBS2_PKTCNT        0x0B20
  999 #define SK_TXRBS2_LVL           0x0B24
 1000 #define SK_TXRBS2_CTLTST        0x0B28
 1001 
 1002 /* Block 23 -- Async. Transmit RAMbuffer 2 */
 1003 #define SK_TXRBA2_START         0x0B80
 1004 #define SK_TXRBA2_END           0x0B84
 1005 #define SK_TXRBA2_WR_PTR        0x0B88
 1006 #define SK_TXRBA2_RD_PTR        0x0B8C
 1007 #define SK_TXRBA2_PKTCNT        0x0BA0
 1008 #define SK_TXRBA2_LVL           0x0BA4
 1009 #define SK_TXRBA2_CTLTST        0x0BA8
 1010 
 1011 #define SK_RBCTL_RESET          0x00000001
 1012 #define SK_RBCTL_UNRESET        0x00000002
 1013 #define SK_RBCTL_OFF            0x00000004
 1014 #define SK_RBCTL_ON             0x00000008
 1015 #define SK_RBCTL_STORENFWD_OFF  0x00000010
 1016 #define SK_RBCTL_STORENFWD_ON   0x00000020
 1017 
 1018 /* Block 24 -- RX MAC FIFO 1 regisrers and LINK_SYNC counter */
 1019 #define SK_RXF1_END             0x0C00
 1020 #define SK_RXF1_WPTR            0x0C04
 1021 #define SK_RXF1_RPTR            0x0C0C
 1022 #define SK_RXF1_PKTCNT          0x0C10
 1023 #define SK_RXF1_LVL             0x0C14
 1024 #define SK_RXF1_MACCTL          0x0C18
 1025 #define SK_RXF1_CTL             0x0C1C
 1026 #define SK_RXLED1_CNTINIT       0x0C20
 1027 #define SK_RXLED1_COUNTER       0x0C24
 1028 #define SK_RXLED1_CTL           0x0C28
 1029 #define SK_RXLED1_TST           0x0C29
 1030 #define SK_LINK_SYNC1_CINIT     0x0C30
 1031 #define SK_LINK_SYNC1_COUNTER   0x0C34
 1032 #define SK_LINK_SYNC1_CTL       0x0C38
 1033 #define SK_LINK_SYNC1_TST       0x0C39
 1034 #define SK_LINKLED1_CTL         0x0C3C
 1035 
 1036 #define SK_FIFO_END             0x3F
 1037 
 1038 /* Receive MAC FIFO 1 (Yukon Only) */
 1039 #define SK_RXMF1_END            0x0C40
 1040 #define SK_RXMF1_THRESHOLD      0x0C44
 1041 #define SK_RXMF1_CTRL_TEST      0x0C48
 1042 #define SK_RXMF1_FLUSH_MASK     0x0C4C
 1043 #define SK_RXMF1_FLUSH_THRESHOLD        0x0C50
 1044 #define SK_RXMF1_WRITE_PTR      0x0C60
 1045 #define SK_RXMF1_WRITE_LEVEL    0x0C68
 1046 #define SK_RXMF1_READ_PTR       0x0C70
 1047 #define SK_RXMF1_READ_LEVEL     0x0C78
 1048 
 1049 /* Receive MAC FIFO 1 Control/Test */
 1050 #define SK_RFCTL_WR_PTR_TST_ON  0x00004000      /* Write pointer test on*/
 1051 #define SK_RFCTL_WR_PTR_TST_OFF 0x00002000      /* Write pointer test off */
 1052 #define SK_RFCTL_WR_PTR_STEP    0x00001000      /* Write pointer increment */
 1053 #define SK_RFCTL_RD_PTR_TST_ON  0x00000400      /* Read pointer test on */
 1054 #define SK_RFCTL_RD_PTR_TST_OFF 0x00000200      /* Read pointer test off */
 1055 #define SK_RFCTL_RD_PTR_STEP    0x00000100      /* Read pointer increment */
 1056 #define SK_RFCTL_FIFO_FLUSH_ON  0x00000080      /* RX FIFO Flush mode on */
 1057 #define SK_RFCTL_FIFO_FLUSH_OFF 0x00000040      /* RX FIFO Flush mode off */
 1058 #define SK_RFCTL_RX_FIFO_OVER   0x00000020      /* Clear IRQ RX FIFO Overrun */
 1059 #define SK_RFCTL_FRAME_RX_DONE  0x00000010      /* Clear IRQ Frame RX Done */
 1060 #define SK_RFCTL_OPERATION_ON   0x00000008      /* Operational mode on */
 1061 #define SK_RFCTL_OPERATION_OFF  0x00000004      /* Operational mode off */
 1062 #define SK_RFCTL_RESET_CLEAR    0x00000002      /* MAC FIFO Reset Clear */
 1063 #define SK_RFCTL_RESET_SET      0x00000001      /* MAC FIFO Reset Set */
 1064 
 1065 #define SK_RFCTL_FIFO_THRESHOLD 0x0a    /* flush threshold (default) */
 1066 
 1067 /* Block 25 -- RX MAC FIFO 2 regisrers and LINK_SYNC counter */
 1068 #define SK_RXF2_END             0x0C80
 1069 #define SK_RXF2_WPTR            0x0C84
 1070 #define SK_RXF2_RPTR            0x0C8C
 1071 #define SK_RXF2_PKTCNT          0x0C90
 1072 #define SK_RXF2_LVL             0x0C94
 1073 #define SK_RXF2_MACCTL          0x0C98
 1074 #define SK_RXF2_CTL             0x0C9C
 1075 #define SK_RXLED2_CNTINIT       0x0CA0
 1076 #define SK_RXLED2_COUNTER       0x0CA4
 1077 #define SK_RXLED2_CTL           0x0CA8
 1078 #define SK_RXLED2_TST           0x0CA9
 1079 #define SK_LINK_SYNC2_CINIT     0x0CB0
 1080 #define SK_LINK_SYNC2_COUNTER   0x0CB4
 1081 #define SK_LINK_SYNC2_CTL       0x0CB8
 1082 #define SK_LINK_SYNC2_TST       0x0CB9
 1083 #define SK_LINKLED2_CTL         0x0CBC
 1084 
 1085 #define SK_RXMACCTL_CLR_IRQ_NOSTS       0x00000001
 1086 #define SK_RXMACCTL_CLR_IRQ_NOTSTAMP    0x00000002
 1087 #define SK_RXMACCTL_TSTAMP_OFF          0x00000004
 1088 #define SK_RXMACCTL_RSTAMP_ON           0x00000008
 1089 #define SK_RXMACCTL_FLUSH_OFF           0x00000010
 1090 #define SK_RXMACCTL_FLUSH_ON            0x00000020
 1091 #define SK_RXMACCTL_PAUSE_OFF           0x00000040
 1092 #define SK_RXMACCTL_PAUSE_ON            0x00000080
 1093 #define SK_RXMACCTL_AFULL_OFF           0x00000100
 1094 #define SK_RXMACCTL_AFULL_ON            0x00000200
 1095 #define SK_RXMACCTL_VALIDTIME_PATCH_OFF 0x00000400
 1096 #define SK_RXMACCTL_VALIDTIME_PATCH_ON  0x00000800
 1097 #define SK_RXMACCTL_RXRDY_PATCH_OFF     0x00001000
 1098 #define SK_RXMACCTL_RXRDY_PATCH_ON      0x00002000
 1099 #define SK_RXMACCTL_STS_TIMEO           0x00FF0000
 1100 #define SK_RXMACCTL_TSTAMP_TIMEO        0xFF000000
 1101 
 1102 #define SK_RXLEDCTL_ENABLE              0x0001
 1103 #define SK_RXLEDCTL_COUNTER_STOP        0x0002
 1104 #define SK_RXLEDCTL_COUNTER_START       0x0004
 1105 
 1106 #define SK_LINKLED_OFF                  0x0001
 1107 #define SK_LINKLED_ON                   0x0002
 1108 #define SK_LINKLED_LINKSYNC_OFF         0x0004
 1109 #define SK_LINKLED_LINKSYNC_ON          0x0008
 1110 #define SK_LINKLED_BLINK_OFF            0x0010
 1111 #define SK_LINKLED_BLINK_ON             0x0020
 1112 
 1113 /* Block 26 -- TX MAC FIFO 1 regisrers  */
 1114 #define SK_TXF1_END             0x0D00
 1115 #define SK_TXF1_WPTR            0x0D04
 1116 #define SK_TXF1_RPTR            0x0D0C
 1117 #define SK_TXF1_PKTCNT          0x0D10
 1118 #define SK_TXF1_LVL             0x0D14
 1119 #define SK_TXF1_MACCTL          0x0D18
 1120 #define SK_TXF1_CTL             0x0D1C
 1121 #define SK_TXLED1_CNTINIT       0x0D20
 1122 #define SK_TXLED1_COUNTER       0x0D24
 1123 #define SK_TXLED1_CTL           0x0D28
 1124 #define SK_TXLED1_TST           0x0D29
 1125 
 1126 /* Transmit MAC FIFO 1 (Yukon Only) */
 1127 #define SK_TXMF1_END            0x0D40
 1128 #define SK_TXMF1_THRESHOLD      0x0D44
 1129 #define SK_TXMF1_CTRL_TEST      0x0D48
 1130 #define SK_TXMF1_WRITE_PTR      0x0D60
 1131 #define SK_TXMF1_WRITE_SHADOW   0x0D64
 1132 #define SK_TXMF1_WRITE_LEVEL    0x0D68
 1133 #define SK_TXMF1_READ_PTR       0x0D70
 1134 #define SK_TXMF1_RESTART_PTR    0x0D74
 1135 #define SK_TXMF1_READ_LEVEL     0x0D78
 1136 
 1137 /* Transmit MAC FIFO Control/Test */
 1138 #define SK_TFCTL_WR_PTR_TST_ON  0x00004000      /* Write pointer test on*/
 1139 #define SK_TFCTL_WR_PTR_TST_OFF 0x00002000      /* Write pointer test off */
 1140 #define SK_TFCTL_WR_PTR_STEP    0x00001000      /* Write pointer increment */
 1141 #define SK_TFCTL_RD_PTR_TST_ON  0x00000400      /* Read pointer test on */
 1142 #define SK_TFCTL_RD_PTR_TST_OFF 0x00000200      /* Read pointer test off */
 1143 #define SK_TFCTL_RD_PTR_STEP    0x00000100      /* Read pointer increment */
 1144 #define SK_TFCTL_TX_FIFO_UNDER  0x00000040      /* Clear IRQ TX FIFO Under */
 1145 #define SK_TFCTL_FRAME_TX_DONE  0x00000020      /* Clear IRQ Frame TX Done */
 1146 #define SK_TFCTL_IRQ_PARITY_ER  0x00000010      /* Clear IRQ Parity Error */
 1147 #define SK_TFCTL_OPERATION_ON   0x00000008      /* Operational mode on */
 1148 #define SK_TFCTL_OPERATION_OFF  0x00000004      /* Operational mode off */
 1149 #define SK_TFCTL_RESET_CLEAR    0x00000002      /* MAC FIFO Reset Clear */
 1150 #define SK_TFCTL_RESET_SET      0x00000001      /* MAC FIFO Reset Set */
 1151 
 1152 /* Block 27 -- TX MAC FIFO 2 regisrers  */
 1153 #define SK_TXF2_END             0x0D80
 1154 #define SK_TXF2_WPTR            0x0D84
 1155 #define SK_TXF2_RPTR            0x0D8C
 1156 #define SK_TXF2_PKTCNT          0x0D90
 1157 #define SK_TXF2_LVL             0x0D94
 1158 #define SK_TXF2_MACCTL          0x0D98
 1159 #define SK_TXF2_CTL             0x0D9C
 1160 #define SK_TXLED2_CNTINIT       0x0DA0
 1161 #define SK_TXLED2_COUNTER       0x0DA4
 1162 #define SK_TXLED2_CTL           0x0DA8
 1163 #define SK_TXLED2_TST           0x0DA9
 1164 
 1165 #define SK_TXMACCTL_XMAC_RESET          0x00000001
 1166 #define SK_TXMACCTL_XMAC_UNRESET        0x00000002
 1167 #define SK_TXMACCTL_LOOP_OFF            0x00000004
 1168 #define SK_TXMACCTL_LOOP_ON             0x00000008
 1169 #define SK_TXMACCTL_FLUSH_OFF           0x00000010
 1170 #define SK_TXMACCTL_FLUSH_ON            0x00000020
 1171 #define SK_TXMACCTL_WAITEMPTY_OFF       0x00000040
 1172 #define SK_TXMACCTL_WAITEMPTY_ON        0x00000080
 1173 #define SK_TXMACCTL_AFULL_OFF           0x00000100
 1174 #define SK_TXMACCTL_AFULL_ON            0x00000200
 1175 #define SK_TXMACCTL_TXRDY_PATCH_OFF     0x00000400
 1176 #define SK_TXMACCTL_RXRDY_PATCH_ON      0x00000800
 1177 #define SK_TXMACCTL_PKT_RECOVERY_OFF    0x00001000
 1178 #define SK_TXMACCTL_PKT_RECOVERY_ON     0x00002000
 1179 #define SK_TXMACCTL_CLR_IRQ_PERR        0x00008000
 1180 #define SK_TXMACCTL_WAITAFTERFLUSH      0x00010000
 1181 
 1182 #define SK_TXLEDCTL_ENABLE              0x0001
 1183 #define SK_TXLEDCTL_COUNTER_STOP        0x0002
 1184 #define SK_TXLEDCTL_COUNTER_START       0x0004
 1185 
 1186 #define SK_FIFO_RESET           0x00000001
 1187 #define SK_FIFO_UNRESET         0x00000002
 1188 #define SK_FIFO_OFF             0x00000004
 1189 #define SK_FIFO_ON              0x00000008
 1190 
 1191 /* Block 28 -- Descriptor Poll Timer */
 1192 #define SK_DPT_INIT             0x0e00  /* Initial value 24 bits */
 1193 #define SK_DPT_TIMER            0x0e04  /* Mul of 78.12MHz clk (24b) */
 1194 
 1195 #define SK_DPT_TIMER_MAX        0x00ffffffff    /* 214.75ms at 78.125MHz */
 1196 
 1197 #define SK_DPT_TIMER_CTRL       0x0e08  /* Timer Control 16 bits */
 1198 #define SK_DPT_TCTL_STOP        0x0001  /* Stop Timer */
 1199 #define SK_DPT_TCTL_START       0x0002  /* Start Timer */
 1200 
 1201 #define SK_DPT_TIMER_TEST       0x0e0a  /* Timer Test 16 bits */
 1202 #define SK_DPT_TTEST_STEP       0x0001  /* Timer Decrement */
 1203 #define SK_DPT_TTEST_OFF        0x0002  /* Test Mode Off */
 1204 #define SK_DPT_TTEST_ON         0x0004  /* Test Mode On */
 1205 
 1206 #define SK_TSTAMP_COUNT         0x0e14
 1207 #define SK_TSTAMP_CTL           0x0e18
 1208 
 1209 #define SK_TSTAMP_IRQ_CLEAR     0x01
 1210 #define SK_TSTAMP_STOP          0x02
 1211 #define SK_TSTAMP_START         0x04
 1212 
 1213 #define SK_Y2_ASF_CSR           0x0e68
 1214 
 1215 #define SK_Y2_ASF_RESET         0x08
 1216 
 1217 #define SK_Y2_LEV_ITIMERINIT    0x0eb0
 1218 #define SK_Y2_LEV_ITIMERCTL     0x0eb8
 1219 #define SK_Y2_TX_ITIMERINIT     0x0ec0
 1220 #define SK_Y2_TX_ITIMERCTL      0x0ec8
 1221 #define SK_Y2_ISR_ITIMERINIT    0x0ed0
 1222 #define SK_Y2_ISR_ITIMERCTL     0x0ed8
 1223 
 1224 /* Block 29 -- Status BMU (Yukon-2 only) */
 1225 #define SK_STAT_BMU_CSR         0x0e80
 1226 #define SK_STAT_BMU_LIDX        0x0e84
 1227 #define SK_STAT_BMU_ADDRLO      0x0e88
 1228 #define SK_STAT_BMU_ADDRHI      0x0e8c
 1229 #define SK_STAT_BMU_TXA1_RIDX   0x0e90
 1230 #define SK_STAT_BMU_TXS1_RIDX   0x0e92
 1231 #define SK_STAT_BMU_TXA2_RIDX   0x0e94
 1232 #define SK_STAT_BMU_TXS2_RIDX   0x0e96
 1233 #define SK_STAT_BMU_TX_THRESH   0x0e98
 1234 #define SK_STAT_BMU_PUTIDX      0x0e9c
 1235 #define SK_STAT_BMU_FIFOWP      0x0ea0
 1236 #define SK_STAT_BMU_FIFORP      0x0ea4
 1237 #define SK_STAT_BMU_FIFORSP     0x0ea6
 1238 #define SK_STAT_BMU_FIFOLV      0x0ea8
 1239 #define SK_STAT_BMU_FIFOSLV     0x0eaa
 1240 #define SK_STAT_BMU_FIFOWM      0x0eac
 1241 #define SK_STAT_BMU_FIFOIWM     0x0ead
 1242 
 1243 #define SK_STAT_BMU_RESET       0x00000001
 1244 #define SK_STAT_BMU_UNRESET     0x00000002
 1245 #define SK_STAT_BMU_OFF         0x00000004
 1246 #define SK_STAT_BMU_ON          0x00000008
 1247 #define SK_STAT_BMU_IRQ_CLEAR   0x00000010
 1248 
 1249 /* Block 30 -- GMAC/GPHY Control Registers (Yukon Only)*/
 1250 #define SK_GMAC_CTRL            0x0f00  /* GMAC Control Register */
 1251 #define SK_GPHY_CTRL            0x0f04  /* GPHY Control Register */
 1252 #define SK_GMAC_ISR             0x0f08  /* GMAC Interrupt Source Register */
 1253 #define SK_GMAC_IMR             0x0f0c  /* GMAC Interrupt Mask Register */
 1254 #define SK_LINK_CTRL            0x0f10  /* Link Control Register (LCR) */
 1255 #define SK_WOL_CTRL             0x0f20  /* Wake on LAN Control Register */
 1256 #define SK_MAC_ADDR_LOW         0x0f24  /* Mack Address Registers LOW */
 1257 #define SK_MAC_ADDR_HIGH        0x0f28  /* Mack Address Registers HIGH */
 1258 #define SK_PAT_READ_PTR         0x0f2c  /* Pattern Read Pointer Register */
 1259 #define SK_PAT_LEN_REG0         0x0f30  /* Pattern Length Register 0 */
 1260 #define SK_PAT_LEN0             0x0f30  /* Pattern Length 0 */
 1261 #define SK_PAT_LEN1             0x0f31  /* Pattern Length 1 */
 1262 #define SK_PAT_LEN2             0x0f32  /* Pattern Length 2 */
 1263 #define SK_PAT_LEN3             0x0f33  /* Pattern Length 3 */
 1264 #define SK_PAT_LEN_REG1         0x0f34  /* Pattern Length Register 1 */
 1265 #define SK_PAT_LEN4             0x0f34  /* Pattern Length 4 */
 1266 #define SK_PAT_LEN5             0x0f35  /* Pattern Length 5 */
 1267 #define SK_PAT_LEN6             0x0f36  /* Pattern Length 6 */
 1268 #define SK_PAT_LEN7             0x0f37  /* Pattern Length 7 */
 1269 #define SK_PAT_CTR_REG0         0x0f38  /* Pattern Counter Register 0 */
 1270 #define SK_PAT_CTR0             0x0f38  /* Pattern Counter 0 */
 1271 #define SK_PAT_CTR1             0x0f39  /* Pattern Counter 1 */
 1272 #define SK_PAT_CTR2             0x0f3a  /* Pattern Counter 2 */
 1273 #define SK_PAT_CTR3             0x0f3b  /* Pattern Counter 3 */
 1274 #define SK_PAT_CTR_REG1         0x0f3c  /* Pattern Counter Register 1 */
 1275 #define SK_PAT_CTR4             0x0f3c  /* Pattern Counter 4 */
 1276 #define SK_PAT_CTR5             0x0f3d  /* Pattern Counter 5 */
 1277 #define SK_PAT_CTR6             0x0f3e  /* Pattern Counter 6 */
 1278 #define SK_PAT_CTR7             0x0f3f  /* Pattern Counter 7 */
 1279 
 1280 #define SK_GMAC_LOOP_ON         0x00000020      /* Loopback mode for testing */
 1281 #define SK_GMAC_LOOP_OFF        0x00000010      /* purposes */
 1282 #define SK_GMAC_PAUSE_ON        0x00000008      /* enable forward of pause */
 1283 #define SK_GMAC_PAUSE_OFF       0x00000004      /* signal to GMAC */
 1284 #define SK_GMAC_RESET_CLEAR     0x00000002      /* Clear GMAC Reset */
 1285 #define SK_GMAC_RESET_SET       0x00000001      /* Set GMAC Reset */
 1286 
 1287 #define SK_GPHY_SEL_BDT         0x10000000      /* Select Bidirectional xfer */
 1288 #define SK_GPHY_INT_POL_HI      0x08000000      /* IRQ Polarity Active */
 1289 #define SK_GPHY_75_OHM          0x04000000      /* Use 75 Ohm Termination */
 1290 #define SK_GPHY_DIS_FC          0x02000000      /* Disable Auto Fiber/Copper */
 1291 #define SK_GPHY_DIS_SLEEP       0x01000000      /* Disable Energy Detect */
 1292 #define SK_GPHY_HWCFG_M_3       0x00800000      /* HWCFG_MODE[3] */
 1293 #define SK_GPHY_HWCFG_M_2       0x00400000      /* HWCFG_MODE[2] */
 1294 #define SK_GPHY_HWCFG_M_1       0x00200000      /* HWCFG_MODE[1] */
 1295 #define SK_GPHY_HWCFG_M_0       0x00100000      /* HWCFG_MODE[0] */
 1296 #define SK_GPHY_ANEG_0          0x00080000      /* ANEG[0] */
 1297 #define SK_GPHY_ENA_XC          0x00040000      /* Enable MDI Crossover */
 1298 #define SK_GPHY_DIS_125         0x00020000      /* Disable 125MHz Clock */
 1299 #define SK_GPHY_ANEG_3          0x00010000      /* ANEG[3] */
 1300 #define SK_GPHY_ANEG_2          0x00008000      /* ANEG[2] */
 1301 #define SK_GPHY_ANEG_1          0x00004000      /* ANEG[1] */
 1302 #define SK_GPHY_ENA_PAUSE       0x00002000      /* Enable Pause */
 1303 #define SK_GPHY_PHYADDR_4       0x00001000      /* Bit 4 of Phy Addr */
 1304 #define SK_GPHY_PHYADDR_3       0x00000800      /* Bit 3 of Phy Addr */
 1305 #define SK_GPHY_PHYADDR_2       0x00000400      /* Bit 2 of Phy Addr */
 1306 #define SK_GPHY_PHYADDR_1       0x00000200      /* Bit 1 of Phy Addr */
 1307 #define SK_GPHY_PHYADDR_0       0x00000100      /* Bit 0 of Phy Addr */
 1308 #define SK_GPHY_RESET_CLEAR     0x00000002      /* Clear GPHY Reset */
 1309 #define SK_GPHY_RESET_SET       0x00000001      /* Set GPHY Reset */
 1310 
 1311 #define SK_GPHY_COPPER          (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \
 1312                                  SK_GPHY_HWCFG_M_2 | SK_GPHY_HWCFG_M_3 )
 1313 #define SK_GPHY_FIBER           (SK_GPHY_HWCFG_M_0 | SK_GPHY_HWCFG_M_1 | \
 1314                                  SK_GPHY_HWCFG_M_2 )
 1315 #define SK_GPHY_ANEG_ALL        (SK_GPHY_ANEG_0 | SK_GPHY_ANEG_1 | \
 1316                                  SK_GPHY_ANEG_2 | SK_GPHY_ANEG_3 )
 1317 
 1318 #define SK_GMAC_INT_TX_OFLOW    0x20    /* Transmit Counter Overflow */
 1319 #define SK_GMAC_INT_RX_OFLOW    0x10    /* Receiver Overflow */
 1320 #define SK_GMAC_INT_TX_UNDER    0x08    /* Transmit FIFO Underrun */
 1321 #define SK_GMAC_INT_TX_DONE     0x04    /* Transmit Complete */
 1322 #define SK_GMAC_INT_RX_OVER     0x02    /* Receive FIFO Overrun */
 1323 #define SK_GMAC_INT_RX_DONE     0x01    /* Receive Complete */
 1324 
 1325 #define SK_LINK_RESET_CLEAR     0x0002  /* Link Reset Clear */
 1326 #define SK_LINK_RESET_SET       0x0001  /* Link Reset Set */
 1327 
 1328 /* Block 31 -- reserved */
 1329 
 1330 /* Block 32-33 -- Pattern Ram */
 1331 #define SK_WOL_PRAM             0x1000
 1332 
 1333 /* Block 0x22 - 0x37 -- reserved */
 1334 
 1335 /* Block 0x38 -- Y2 PCI config registers */
 1336 #define SK_Y2_PCI_BASE          0x1c00
 1337 
 1338 /* Compute offset of mirrored PCI register */
 1339 #define SK_Y2_PCI_REG(reg)      ((reg) + SK_Y2_PCI_BASE)
 1340 
 1341 /* Block 0x39 - 0x3f -- reserved */
 1342 
 1343 /* Block 0x40 to 0x4F -- XMAC 1 registers */
 1344 #define SK_XMAC1_BASE   0x2000
 1345 
 1346 /* Block 0x50 to 0x5F -- MARV 1 registers */
 1347 #define SK_MARV1_BASE   0x2800
 1348 
 1349 /* Block 0x60 to 0x6F -- XMAC 2 registers */
 1350 #define SK_XMAC2_BASE   0x3000
 1351 
 1352 /* Block 0x70 to 0x7F -- MARV 2 registers */
 1353 #define SK_MARV2_BASE   0x3800
 1354 
 1355 /* Compute relative offset of an XMAC register in the XMAC window(s). */
 1356 #define SK_XMAC_REG(sc, reg)    (((reg) * 2) + SK_XMAC1_BASE + \
 1357         (((sc)->sk_port) * (SK_XMAC2_BASE - SK_XMAC1_BASE)))
 1358 
 1359 #if 0
 1360 #define SK_XM_READ_4(sc, reg)                                           \
 1361         ((sk_win_read_2(sc->sk_softc,                                   \
 1362               SK_XMAC_REG(sc, reg)) & 0xFFFF) |         \
 1363          ((sk_win_read_2(sc->sk_softc,                                  \
 1364               SK_XMAC_REG(sc, reg + 2)) & 0xFFFF) << 16))
 1365 
 1366 #define SK_XM_WRITE_4(sc, reg, val)                                     \
 1367         sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg),              \
 1368                        ((val) & 0xFFFF));                               \
 1369         sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg + 2),          \
 1370                        ((val) >> 16) & 0xFFFF)
 1371 #else
 1372 #define SK_XM_READ_4(sc, reg)           \
 1373         sk_win_read_4(sc->sk_softc, SK_XMAC_REG(sc, reg))
 1374 
 1375 #define SK_XM_WRITE_4(sc, reg, val)     \
 1376         sk_win_write_4(sc->sk_softc, SK_XMAC_REG(sc, reg), (val))
 1377 #endif
 1378 
 1379 #define SK_XM_READ_2(sc, reg)           \
 1380         sk_win_read_2(sc->sk_softc, SK_XMAC_REG(sc, reg))
 1381 
 1382 #define SK_XM_WRITE_2(sc, reg, val)     \
 1383         sk_win_write_2(sc->sk_softc, SK_XMAC_REG(sc, reg), val)
 1384 
 1385 #define SK_XM_SETBIT_4(sc, reg, x)      \
 1386         SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) | (x))
 1387 
 1388 #define SK_XM_CLRBIT_4(sc, reg, x)      \
 1389         SK_XM_WRITE_4(sc, reg, (SK_XM_READ_4(sc, reg)) & ~(x))
 1390 
 1391 #define SK_XM_SETBIT_2(sc, reg, x)      \
 1392         SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) | (x))
 1393 
 1394 #define SK_XM_CLRBIT_2(sc, reg, x)      \
 1395         SK_XM_WRITE_2(sc, reg, (SK_XM_READ_2(sc, reg)) & ~(x))
 1396 
 1397 /* Compute relative offset of an MARV register in the MARV window(s). */
 1398 #define SK_YU_REG(sc, reg) \
 1399         ((reg) + SK_MARV1_BASE + \
 1400         (((sc)->sk_port) * (SK_MARV2_BASE - SK_MARV1_BASE)))
 1401 
 1402 #define SK_YU_READ_4(sc, reg)           \
 1403         sk_win_read_4((sc)->sk_softc, SK_YU_REG((sc), (reg)))
 1404 
 1405 #define SK_YU_READ_2(sc, reg)           \
 1406         sk_win_read_2((sc)->sk_softc, SK_YU_REG((sc), (reg)))
 1407 
 1408 #define SK_YU_WRITE_4(sc, reg, val)     \
 1409         sk_win_write_4((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val))
 1410 
 1411 #define SK_YU_WRITE_2(sc, reg, val)     \
 1412         sk_win_write_2((sc)->sk_softc, SK_YU_REG((sc), (reg)), (val))
 1413 
 1414 #define SK_YU_SETBIT_4(sc, reg, x)      \
 1415         SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) | (x))
 1416 
 1417 #define SK_YU_CLRBIT_4(sc, reg, x)      \
 1418         SK_YU_WRITE_4(sc, reg, (SK_YU_READ_4(sc, reg)) & ~(x))
 1419 
 1420 #define SK_YU_SETBIT_2(sc, reg, x)      \
 1421         SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) | (x))
 1422 
 1423 #define SK_YU_CLRBIT_2(sc, reg, x)      \
 1424         SK_YU_WRITE_2(sc, reg, (SK_YU_READ_2(sc, reg)) & ~(x))
 1425 
 1426 /*
 1427  * The default FIFO threshold on the XMAC II is 4 bytes. On
 1428  * dual port NICs, this often leads to transmit underruns, so we
 1429  * bump the threshold a little.
 1430  */
 1431 #define SK_XM_TX_FIFOTHRESH     512
 1432 
 1433 #define SK_PCI_VENDOR_ID        0x0000
 1434 #define SK_PCI_DEVICE_ID        0x0002
 1435 #define SK_PCI_COMMAND          0x0004
 1436 #define SK_PCI_STATUS           0x0006
 1437 #define SK_PCI_REVID            0x0008
 1438 #define SK_PCI_CLASSCODE        0x0009
 1439 #define SK_PCI_CACHELEN         0x000C
 1440 #define SK_PCI_LATENCY_TIMER    0x000D
 1441 #define SK_PCI_HEADER_TYPE      0x000E
 1442 #define SK_PCI_LOMEM            0x0010
 1443 #define SK_PCI_LOIO             0x0014
 1444 #define SK_PCI_SUBVEN_ID        0x002C
 1445 #define SK_PCI_SYBSYS_ID        0x002E
 1446 #define SK_PCI_BIOSROM          0x0030
 1447 #define SK_PCI_INTLINE          0x003C
 1448 #define SK_PCI_INTPIN           0x003D
 1449 #define SK_PCI_MINGNT           0x003E
 1450 #define SK_PCI_MINLAT           0x003F
 1451 
 1452 /* device specific PCI registers */
 1453 #define SK_PCI_OURREG1          0x0040
 1454 #define SK_PCI_OURREG2          0x0044
 1455 #define SK_PCI_CAPID            0x0048 /* 8 bits */
 1456 #define SK_PCI_NEXTPTR          0x0049 /* 8 bits */
 1457 #define SK_PCI_PWRMGMTCAP       0x004A /* 16 bits */
 1458 #define SK_PCI_PWRMGMTCTRL      0x004C /* 16 bits */
 1459 #define SK_PCI_PME_EVENT        0x004F
 1460 
 1461 #define SK_Y2_REG1_PHY1_COMA    0x10000000
 1462 #define SK_Y2_REG1_PHY2_COMA    0x20000000
 1463 
 1464 #define SK_PSTATE_MASK          0x0003
 1465 #define SK_PSTATE_D0            0x0000
 1466 #define SK_PSTATE_D1            0x0001
 1467 #define SK_PSTATE_D2            0x0002
 1468 #define SK_PSTATE_D3            0x0003
 1469 #define SK_PME_EN               0x0010
 1470 #define SK_PME_STATUS           0x8000
 1471 
 1472 #define CSR_WRITE_4(sc, reg, val) \
 1473         bus_space_write_4((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val))
 1474 #define CSR_WRITE_2(sc, reg, val) \
 1475         bus_space_write_2((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val))
 1476 #define CSR_WRITE_1(sc, reg, val) \
 1477         bus_space_write_1((sc)->sk_btag, (sc)->sk_bhandle, (reg), (val))
 1478 
 1479 #define CSR_READ_4(sc, reg) \
 1480         bus_space_read_4((sc)->sk_btag, (sc)->sk_bhandle, (reg))
 1481 #define CSR_READ_2(sc, reg) \
 1482         bus_space_read_2((sc)->sk_btag, (sc)->sk_bhandle, (reg))
 1483 #define CSR_READ_1(sc, reg) \
 1484         bus_space_read_1((sc)->sk_btag, (sc)->sk_bhandle, (reg))
 1485 
 1486 struct sk_type {
 1487         u_int16_t               sk_vid;
 1488         u_int16_t               sk_did;
 1489         char                    *sk_name;
 1490 };
 1491 
 1492 #define SK_ADDR_LO(x)   ((u_int64_t) (x) & 0xffffffff)
 1493 #define SK_ADDR_HI(x)   ((u_int64_t) (x) >> 32)
 1494 
 1495 #define SK_RING_ALIGN   64
 1496 
 1497 /* RX queue descriptor data structure */
 1498 struct sk_rx_desc {
 1499         u_int32_t               sk_ctl;
 1500         u_int32_t               sk_next;
 1501         u_int32_t               sk_data_lo;
 1502         u_int32_t               sk_data_hi;
 1503         u_int32_t               sk_xmac_rxstat;
 1504         u_int32_t               sk_timestamp;
 1505         u_int16_t               sk_csum2;
 1506         u_int16_t               sk_csum1;
 1507         u_int16_t               sk_csum2_start;
 1508         u_int16_t               sk_csum1_start;
 1509 };
 1510 
 1511 #define SK_OPCODE_DEFAULT       0x00550000
 1512 #define SK_OPCODE_CSUM          0x00560000
 1513 
 1514 #define SK_RXCTL_LEN            0x0000FFFF
 1515 #define SK_RXCTL_OPCODE         0x00FF0000
 1516 #define SK_RXCTL_TSTAMP_VALID   0x01000000
 1517 #define SK_RXCTL_STATUS_VALID   0x02000000
 1518 #define SK_RXCTL_DEV0           0x04000000
 1519 #define SK_RXCTL_EOF_INTR       0x08000000
 1520 #define SK_RXCTL_EOB_INTR       0x10000000
 1521 #define SK_RXCTL_LASTFRAG       0x20000000
 1522 #define SK_RXCTL_FIRSTFRAG      0x40000000
 1523 #define SK_RXCTL_OWN            0x80000000
 1524 
 1525 #define SK_RXSTAT       \
 1526         (SK_OPCODE_DEFAULT|SK_RXCTL_EOF_INTR|SK_RXCTL_LASTFRAG| \
 1527          SK_RXCTL_FIRSTFRAG|SK_RXCTL_OWN)
 1528 
 1529 struct sk_tx_desc {
 1530         u_int32_t               sk_ctl;
 1531         u_int32_t               sk_next;
 1532         u_int32_t               sk_data_lo;
 1533         u_int32_t               sk_data_hi;
 1534         u_int32_t               sk_xmac_txstat;
 1535         u_int16_t               sk_rsvd0;
 1536         u_int16_t               sk_csum_startval;
 1537         u_int16_t               sk_csum_startpos;
 1538         u_int16_t               sk_csum_writepos;
 1539         u_int32_t               sk_rsvd1;
 1540 };
 1541 
 1542 #define SK_TXCTL_LEN            0x0000FFFF
 1543 #define SK_TXCTL_OPCODE         0x00FF0000
 1544 #define SK_TXCTL_SW             0x01000000
 1545 #define SK_TXCTL_NOCRC          0x02000000
 1546 #define SK_TXCTL_STORENFWD      0x04000000
 1547 #define SK_TXCTL_EOF_INTR       0x08000000
 1548 #define SK_TXCTL_EOB_INTR       0x10000000
 1549 #define SK_TXCTL_LASTFRAG       0x20000000
 1550 #define SK_TXCTL_FIRSTFRAG      0x40000000
 1551 #define SK_TXCTL_OWN            0x80000000
 1552 
 1553 #define SK_TXSTAT       \
 1554         (SK_OPCODE_DEFAULT|SK_TXCTL_EOF_INTR|SK_TXCTL_LASTFRAG|SK_TXCTL_OWN)
 1555 
 1556 #define SK_RXBYTES(x)           ((x) & 0x0000FFFF);
 1557 #define SK_TXBYTES              SK_RXBYTES
 1558 
 1559 #define SK_TX_RING_CNT          512
 1560 #define SK_RX_RING_CNT          256
 1561 
 1562 struct msk_rx_desc {
 1563         u_int32_t               sk_addr;
 1564         u_int16_t               sk_len;
 1565         u_int8_t                sk_ctl;
 1566         u_int8_t                sk_opcode;
 1567 } __packed;
 1568 
 1569 #define SK_Y2_RXOPC_BUFFER      0x40
 1570 #define SK_Y2_RXOPC_PACKET      0x41
 1571 #define SK_Y2_RXOPC_OWN         0x80
 1572 
 1573 struct msk_tx_desc {
 1574         u_int32_t               sk_addr;
 1575         u_int16_t               sk_len;
 1576         u_int8_t                sk_ctl;
 1577         u_int8_t                sk_opcode;
 1578 } __packed;
 1579 
 1580 #define SK_Y2_TXCTL_LASTFRAG    0x80
 1581 
 1582 #define SK_Y2_TXOPC_BUFFER      0x40
 1583 #define SK_Y2_TXOPC_PACKET      0x41
 1584 #define SK_Y2_TXOPC_OWN         0x80
 1585 
 1586 struct msk_status_desc {
 1587         u_int32_t               sk_status;
 1588         u_int16_t               sk_len;
 1589         u_int8_t                sk_link;
 1590         u_int8_t                sk_opcode;
 1591 } __packed;
 1592 
 1593 #define SK_Y2_STOPC_RXSTAT      0x60
 1594 #define SK_Y2_STOPC_TXSTAT      0x68
 1595 #define SK_Y2_STOPC_OWN         0x80
 1596 
 1597 #define MSK_TX_RING_CNT         512
 1598 #define MSK_RX_RING_CNT         512
 1599 #define MSK_STATUS_RING_CNT     2048
 1600 
 1601 /*
 1602  * Jumbo buffer stuff. Note that we must allocate more jumbo
 1603  * buffers than there are descriptors in the receive ring. This
 1604  * is because we don't know how long it will take for a packet
 1605  * to be released after we hand it off to the upper protocol
 1606  * layers. To be safe, we allocate 1.5 times the number of
 1607  * receive descriptors.
 1608  */
 1609 #define SK_JUMBO_FRAMELEN       9018
 1610 #define SK_JUMBO_MTU            (SK_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
 1611 #define SK_MIN_FRAMELEN         (ETHER_MIN_LEN - ETHER_CRC_LEN)
 1612 #define SK_JSLOTS               ((SK_RX_RING_CNT / 2) * 3)
 1613 
 1614 #define SK_JRAWLEN      (SK_JUMBO_FRAMELEN + ETHER_ALIGN)
 1615 #define SK_JLEN         SK_JRAWLEN
 1616 #define SK_MCLBYTES     SK_JLEN
 1617 #define SK_JPAGESZ      PAGE_SIZE
 1618 #define SK_RESID        (SK_JPAGESZ - (SK_JLEN * SK_JSLOTS) % SK_JPAGESZ)
 1619 #define SK_JMEM         ((SK_JLEN * SK_JSLOTS) + SK_RESID)
 1620 
 1621 #define MSK_JSLOTS              ((MSK_RX_RING_CNT / 2) * 3)
 1622 
 1623 #define MSK_RESID       (SK_JPAGESZ - (SK_JLEN * MSK_JSLOTS) % SK_JPAGESZ)
 1624 #define MSK_JMEM        ((SK_JLEN * MSK_JSLOTS) + MSK_RESID)
 1625 
 1626 #define SK_MAXUNIT      256
 1627 #define SK_TIMEOUT      1000
 1628 
 1629 /* YUKON registers */
 1630 
 1631 /* General Purpose Status Register (GPSR) */
 1632 #define YUKON_GPSR              0x0000
 1633 
 1634 #define YU_GPSR_SPEED           0x8000  /* speed 0 - 10Mbps, 1 - 100Mbps */
 1635 #define YU_GPSR_DUPLEX          0x4000  /* 0 - half duplex, 1 - full duplex */
 1636 #define YU_GPSR_FCTL_TX         0x2000  /* Tx flow control, 1 - disabled */
 1637 #define YU_GPSR_LINK            0x1000  /* link status (down/up) */
 1638 #define YU_GPSR_PAUSE           0x0800  /* flow control enable/disable */
 1639 #define YU_GPSR_TX_IN_PROG      0x0400  /* transmit in progress */
 1640 #define YU_GPSR_EXCESS_COL      0x0200  /* excessive collisions occurred */
 1641 #define YU_GPSR_LATE_COL        0x0100  /* late collision occurred */
 1642 #define YU_GPSR_MII_PHY_STC     0x0020  /* MII PHY status change */
 1643 #define YU_GPSR_GIG_SPEED       0x0010  /* Gigabit Speed (0 - use speed bit) */
 1644 #define YU_GPSR_PARTITION       0x0008  /* partition mode */
 1645 #define YU_GPSR_FCTL_RX         0x0004  /* Rx flow control, 1 - disabled  */
 1646 #define YU_GPSR_PROMS_EN        0x0002  /* promiscuous mode, 1 - enabled */
 1647 
 1648 /* General Purpose Control Register (GPCR) */
 1649 #define YUKON_GPCR              0x0004
 1650 
 1651 #define YU_GPCR_FCTL_TX_DIS     0x2000  /* Disable Tx flow control 802.3x */
 1652 #define YU_GPCR_TXEN            0x1000  /* Transmit Enable */
 1653 #define YU_GPCR_RXEN            0x0800  /* Receive Enable */
 1654 #define YU_GPCR_BURSTEN         0x0400  /* Burst Mode Enable */
 1655 #define YU_GPCR_LPBK            0x0200  /* MAC Loopback Enable */
 1656 #define YU_GPCR_PAR             0x0100  /* Partition Enable */
 1657 #define YU_GPCR_GIG             0x0080  /* Gigabit Speed 1000Mbps */
 1658 #define YU_GPCR_FLP             0x0040  /* Force Link Pass */
 1659 #define YU_GPCR_DUPLEX          0x0020  /* Duplex Enable */
 1660 #define YU_GPCR_FCTL_RX_DIS     0x0010  /* Disable Rx flow control 802.3x */
 1661 #define YU_GPCR_SPEED           0x0008  /* Port Speed 100Mbps */
 1662 #define YU_GPCR_DPLX_DIS        0x0004  /* Disable Auto-Update for duplex */
 1663 #define YU_GPCR_FCTL_DIS        0x0002  /* Disable Auto-Update for 802.3x */
 1664 #define YU_GPCR_SPEED_DIS       0x0001  /* Disable Auto-Update for speed */
 1665 
 1666 /* Transmit Control Register (TCR) */
 1667 #define YUKON_TCR               0x0008
 1668 
 1669 #define YU_TCR_FJ               0x8000  /* force jam / flow control */
 1670 #define YU_TCR_CRCD             0x4000  /* insert CRC (0 - enable) */
 1671 #define YU_TCR_PADD             0x2000  /* pad packets to 64b (0 - enable) */
 1672 #define YU_TCR_COLTH            0x1c00  /* collision threshold */
 1673 
 1674 /* Receive Control Register (RCR) */
 1675 #define YUKON_RCR               0x000c
 1676 
 1677 #define YU_RCR_UFLEN            0x8000  /* unicast filter enable */
 1678 #define YU_RCR_MUFLEN           0x4000  /* multicast filter enable */
 1679 #define YU_RCR_CRCR             0x2000  /* remove CRC */
 1680 #define YU_RCR_PASSFC           0x1000  /* pass flow control packets */
 1681 
 1682 /* Transmit Flow Control Register (TFCR) */
 1683 #define YUKON_TFCR              0x0010  /* Pause Time */
 1684 
 1685 /* Transmit Parameter Register (TPR) */
 1686 #define YUKON_TPR               0x0014
 1687 
 1688 #define YU_TPR_JAM_LEN(x)       (((x) & 0x3) << 14)
 1689 #define YU_TPR_JAM_IPG(x)       (((x) & 0x1f) << 9)
 1690 #define YU_TPR_JAM2DATA_IPG(x)  (((x) & 0x1f) << 4)
 1691 
 1692 /* Serial Mode Register (SMR) */
 1693 #define YUKON_SMR               0x0018
 1694 
 1695 #define YU_SMR_DATA_BLIND(x)    (((x) & 0x1f) << 11)
 1696 #define YU_SMR_LIMIT4           0x0400  /* reset after 16 / 4 collisions */
 1697 #define YU_SMR_MFL_JUMBO        0x0100  /* max frame length for jumbo frames */
 1698 #define YU_SMR_MFL_VLAN         0x0200  /* max frame length + vlan tag */
 1699 #define YU_SMR_IPG_DATA(x)      ((x) & 0x1f)
 1700 
 1701 /* Source Address Low #1 (SAL1) */
 1702 #define YUKON_SAL1              0x001c  /* SA1[15:0] */
 1703 
 1704 /* Source Address Middle #1 (SAM1) */
 1705 #define YUKON_SAM1              0x0020  /* SA1[31:16] */
 1706 
 1707 /* Source Address High #1 (SAH1) */
 1708 #define YUKON_SAH1              0x0024  /* SA1[47:32] */
 1709 
 1710 /* Source Address Low #2 (SAL2) */
 1711 #define YUKON_SAL2              0x0028  /* SA2[15:0] */
 1712 
 1713 /* Source Address Middle #2 (SAM2) */
 1714 #define YUKON_SAM2              0x002c  /* SA2[31:16] */
 1715 
 1716 /* Source Address High #2 (SAH2) */
 1717 #define YUKON_SAH2              0x0030  /* SA2[47:32] */
 1718 
 1719 /* Multicatst Address Hash Register 1 (MCAH1) */
 1720 #define YUKON_MCAH1             0x0034
 1721 
 1722 /* Multicatst Address Hash Register 2 (MCAH2) */
 1723 #define YUKON_MCAH2             0x0038
 1724 
 1725 /* Multicatst Address Hash Register 3 (MCAH3) */
 1726 #define YUKON_MCAH3             0x003c
 1727 
 1728 /* Multicatst Address Hash Register 4 (MCAH4) */
 1729 #define YUKON_MCAH4             0x0040
 1730 
 1731 /* Transmit Interrupt Register (TIR) */
 1732 #define YUKON_TIR               0x0044
 1733 
 1734 #define YU_TIR_OUT_UNICAST      0x0001  /* Num Unicast Packets Transmitted */
 1735 #define YU_TIR_OUT_BROADCAST    0x0002  /* Num Broadcast Packets Transmitted */
 1736 #define YU_TIR_OUT_PAUSE        0x0004  /* Num Pause Packets Transmitted */
 1737 #define YU_TIR_OUT_MULTICAST    0x0008  /* Num Multicast Packets Transmitted */
 1738 #define YU_TIR_OUT_OCTETS       0x0030  /* Num Bytes Transmitted */
 1739 #define YU_TIR_OUT_64_OCTETS    0x0000  /* Num Packets Transmitted */
 1740 #define YU_TIR_OUT_127_OCTETS   0x0000  /* Num Packets Transmitted */
 1741 #define YU_TIR_OUT_255_OCTETS   0x0000  /* Num Packets Transmitted */
 1742 #define YU_TIR_OUT_511_OCTETS   0x0000  /* Num Packets Transmitted */
 1743 #define YU_TIR_OUT_1023_OCTETS  0x0000  /* Num Packets Transmitted */
 1744 #define YU_TIR_OUT_1518_OCTETS  0x0000  /* Num Packets Transmitted */
 1745 #define YU_TIR_OUT_MAX_OCTETS   0x0000  /* Num Packets Transmitted */
 1746 #define YU_TIR_OUT_SPARE        0x0000  /* Num Packets Transmitted */
 1747 #define YU_TIR_OUT_COLLISIONS   0x0000  /* Num Packets Transmitted */
 1748 #define YU_TIR_OUT_LATE         0x0000  /* Num Packets Transmitted */
 1749 
 1750 /* Receive Interrupt Register (RIR) */
 1751 #define YUKON_RIR               0x0048
 1752 
 1753 /* Transmit and Receive Interrupt Register (TRIR) */
 1754 #define YUKON_TRIR              0x004c
 1755 
 1756 /* Transmit Interrupt Mask Register (TIMR) */
 1757 #define YUKON_TIMR              0x0050
 1758 
 1759 /* Receive Interrupt Mask Register (RIMR) */
 1760 #define YUKON_RIMR              0x0054
 1761 
 1762 /* Transmit and Receive Interrupt Mask Register (TRIMR) */
 1763 #define YUKON_TRIMR             0x0058
 1764 
 1765 /* SMI Control Register (SMICR) */
 1766 #define YUKON_SMICR             0x0080
 1767 
 1768 #define YU_SMICR_PHYAD(x)       (((x) & 0x1f) << 11)
 1769 #define YU_SMICR_REGAD(x)       (((x) & 0x1f) << 6)
 1770 #define YU_SMICR_OPCODE         0x0020  /* opcode (0 - write, 1 - read) */
 1771 #define YU_SMICR_OP_READ        0x0020  /* opcode read */
 1772 #define YU_SMICR_OP_WRITE       0x0000  /* opcode write */
 1773 #define YU_SMICR_READ_VALID     0x0010  /* read valid */
 1774 #define YU_SMICR_BUSY           0x0008  /* busy (writing) */
 1775 
 1776 /* SMI Data Register (SMIDR) */
 1777 #define YUKON_SMIDR             0x0084
 1778 
 1779 /* PHY Addres Register (PAR) */
 1780 #define YUKON_PAR               0x0088
 1781 
 1782 #define YU_PAR_MIB_CLR          0x0020  /* MIB Counters Clear Mode */
 1783 #define YU_PAR_LOAD_TSTCNT      0x0010  /* Load count 0xfffffff0 into cntr */
 1784 
 1785 /* Receive status */
 1786 #define YU_RXSTAT_FOFL          0x00000001      /* Rx FIFO overflow */
 1787 #define YU_RXSTAT_CRCERR        0x00000002      /* CRC error */
 1788 #define YU_RXSTAT_FRAGMENT      0x00000008      /* fragment */
 1789 #define YU_RXSTAT_LONGERR       0x00000010      /* too long packet */
 1790 #define YU_RXSTAT_MIIERR        0x00000020      /* MII error */
 1791 #define YU_RXSTAT_BADFC         0x00000040      /* bad flow-control packet */
 1792 #define YU_RXSTAT_GOODFC        0x00000080      /* good flow-control packet */
 1793 #define YU_RXSTAT_RXOK          0x00000100      /* receice OK (Good packet) */
 1794 #define YU_RXSTAT_BROADCAST     0x00000200      /* broadcast packet */
 1795 #define YU_RXSTAT_MULTICAST     0x00000400      /* multicast packet */
 1796 #define YU_RXSTAT_RUNT          0x00000800      /* undersize packet */
 1797 #define YU_RXSTAT_JABBER        0x00001000      /* jabber packet */
 1798 #define YU_RXSTAT_VLAN          0x00002000      /* VLAN packet */
 1799 #define YU_RXSTAT_LENSHIFT      16
 1800 
 1801 #define YU_RXSTAT_BYTES(x)      ((x) >> YU_RXSTAT_LENSHIFT)
 1802 
 1803 /*
 1804  * Registers and data structures for the XaQti Corporation XMAC II
 1805  * Gigabit Ethernet MAC. Datasheet is available from http://www.xaqti.com.
 1806  * The XMAC can be programmed for 16-bit or 32-bit register access modes.
 1807  * The SysKonnect gigabit ethernet adapters use 16-bit mode, so that's
 1808  * how the registers are laid out here.
 1809  */
 1810 
 1811 #define XM_DEVICEID             0x00E0AE20
 1812 #define XM_XAQTI_OUI            0x00E0AE
 1813 
 1814 #define XM_XMAC_REV(x)          (((x) & 0x000000E0) >> 5)
 1815 
 1816 #define XM_XMAC_REV_B2          0x0
 1817 #define XM_XMAC_REV_C1          0x1
 1818 
 1819 #define XM_MMUCMD               0x0000
 1820 #define XM_POFF                 0x0008
 1821 #define XM_BURST                0x000C
 1822 #define XM_VLAN_TAGLEV1         0x0010
 1823 #define XM_VLAN_TAGLEV2         0x0014
 1824 #define XM_TXCMD                0x0020
 1825 #define XM_TX_RETRYLIMIT        0x0024
 1826 #define XM_TX_SLOTTIME          0x0028
 1827 #define XM_TX_IPG               0x003C
 1828 #define XM_RXCMD                0x0030
 1829 #define XM_PHY_ADDR             0x0034
 1830 #define XM_PHY_DATA             0x0038
 1831 #define XM_GPIO                 0x0040
 1832 #define XM_IMR                  0x0044
 1833 #define XM_ISR                  0x0048
 1834 #define XM_HWCFG                0x004C
 1835 #define XM_TX_LOWAT             0x0060
 1836 #define XM_TX_HIWAT             0x0062
 1837 #define XM_TX_REQTHRESH_LO      0x0064
 1838 #define XM_TX_REQTHRESH_HI      0x0066
 1839 #define XM_TX_REQTHRESH         XM_TX_REQTHRESH_LO
 1840 #define XM_PAUSEDST0            0x0068
 1841 #define XM_PAUSEDST1            0x006A
 1842 #define XM_PAUSEDST2            0x006C
 1843 #define XM_CTLPARM_LO           0x0070
 1844 #define XM_CTLPARM_HI           0x0072
 1845 #define XM_CTLPARM              XM_CTLPARM_LO
 1846 #define XM_OPCODE_PAUSE_TIMER   0x0074
 1847 #define XM_TXSTAT_LIFO          0x0078
 1848 
 1849 /*
 1850  * Perfect filter registers. The XMAC has a table of 16 perfect
 1851  * filter entries, spaced 8 bytes apart. This is in addition to
 1852  * the station address registers, which appear below.
 1853  */
 1854 #define XM_RXFILT_BASE          0x0080
 1855 #define XM_RXFILT_END           0x0107
 1856 #define XM_RXFILT_MAX           16
 1857 #define XM_RXFILT_ENTRY(ent)            (XM_RXFILT_BASE + ((ent * 8)))
 1858 
 1859 /* Primary station address. */
 1860 #define XM_PAR0                 0x0108
 1861 #define XM_PAR1                 0x010A
 1862 #define XM_PAR2                 0x010C
 1863 
 1864 /* 64-bit multicast hash table registers */
 1865 #define XM_MAR0                 0x0110
 1866 #define XM_MAR1                 0x0112
 1867 #define XM_MAR2                 0x0114
 1868 #define XM_MAR3                 0x0116
 1869 #define XM_RX_LOWAT             0x0118
 1870 #define XM_RX_HIWAT             0x011A
 1871 #define XM_RX_REQTHRESH_LO      0x011C
 1872 #define XM_RX_REQTHRESH_HI      0x011E
 1873 #define XM_RX_REQTHRESH         XM_RX_REQTHRESH_LO
 1874 #define XM_DEVID_LO             0x0120
 1875 #define XM_DEVID_HI             0x0122
 1876 #define XM_DEVID                XM_DEVID_LO
 1877 #define XM_MODE_LO              0x0124
 1878 #define XM_MODE_HI              0x0126
 1879 #define XM_MODE                 XM_MODE_LO
 1880 #define XM_LASTSRC0             0x0128
 1881 #define XM_LASTSRC1             0x012A
 1882 #define XM_LASTSRC2             0x012C
 1883 #define XM_TSTAMP_READ          0x0130
 1884 #define XM_TSTAMP_LOAD          0x0134
 1885 #define XM_STATS_CMD            0x0200
 1886 #define XM_RXCNT_EVENT_LO       0x0204
 1887 #define XM_RXCNT_EVENT_HI       0x0206
 1888 #define XM_RXCNT_EVENT          XM_RXCNT_EVENT_LO
 1889 #define XM_TXCNT_EVENT_LO       0x0208
 1890 #define XM_TXCNT_EVENT_HI       0x020A
 1891 #define XM_TXCNT_EVENT          XM_TXCNT_EVENT_LO
 1892 #define XM_RXCNT_EVMASK_LO      0x020C
 1893 #define XM_RXCNT_EVMASK_HI      0x020E
 1894 #define XM_RXCNT_EVMASK         XM_RXCNT_EVMASK_LO
 1895 #define XM_TXCNT_EVMASK_LO      0x0210
 1896 #define XM_TXCNT_EVMASK_HI      0x0212
 1897 #define XM_TXCNT_EVMASK         XM_TXCNT_EVMASK_LO
 1898 
 1899 /* Statistics command register */
 1900 #define XM_STATCMD_CLR_TX       0x0001
 1901 #define XM_STATCMD_CLR_RX       0x0002
 1902 #define XM_STATCMD_COPY_TX      0x0004
 1903 #define XM_STATCMD_COPY_RX      0x0008
 1904 #define XM_STATCMD_SNAP_TX      0x0010
 1905 #define XM_STATCMD_SNAP_RX      0x0020
 1906 
 1907 /* TX statistics registers */
 1908 #define XM_TXSTATS_PKTSOK       0x280
 1909 #define XM_TXSTATS_BYTESOK_HI   0x284
 1910 #define XM_TXSTATS_BYTESOK_LO   0x288
 1911 #define XM_TXSTATS_BCASTSOK     0x28C
 1912 #define XM_TXSTATS_MCASTSOK     0x290
 1913 #define XM_TXSTATS_UCASTSOK     0x294
 1914 #define XM_TXSTATS_GIANTS       0x298
 1915 #define XM_TXSTATS_BURSTCNT     0x29C
 1916 #define XM_TXSTATS_PAUSEPKTS    0x2A0
 1917 #define XM_TXSTATS_MACCTLPKTS   0x2A4
 1918 #define XM_TXSTATS_SINGLECOLS   0x2A8
 1919 #define XM_TXSTATS_MULTICOLS    0x2AC
 1920 #define XM_TXSTATS_EXCESSCOLS   0x2B0
 1921 #define XM_TXSTATS_LATECOLS     0x2B4
 1922 #define XM_TXSTATS_DEFER        0x2B8
 1923 #define XM_TXSTATS_EXCESSDEFER  0x2BC
 1924 #define XM_TXSTATS_UNDERRUN     0x2C0
 1925 #define XM_TXSTATS_CARRIERSENSE 0x2C4
 1926 #define XM_TXSTATS_UTILIZATION  0x2C8
 1927 #define XM_TXSTATS_64           0x2D0
 1928 #define XM_TXSTATS_65_127       0x2D4
 1929 #define XM_TXSTATS_128_255      0x2D8
 1930 #define XM_TXSTATS_256_511      0x2DC
 1931 #define XM_TXSTATS_512_1023     0x2E0
 1932 #define XM_TXSTATS_1024_MAX     0x2E4
 1933 
 1934 /* RX statistics registers */
 1935 #define XM_RXSTATS_PKTSOK       0x300
 1936 #define XM_RXSTATS_BYTESOK_HI   0x304
 1937 #define XM_RXSTATS_BYTESOK_LO   0x308
 1938 #define XM_RXSTATS_BCASTSOK     0x30C
 1939 #define XM_RXSTATS_MCASTSOK     0x310
 1940 #define XM_RXSTATS_UCASTSOK     0x314
 1941 #define XM_RXSTATS_PAUSEPKTS    0x318
 1942 #define XM_RXSTATS_MACCTLPKTS   0x31C
 1943 #define XM_RXSTATS_BADPAUSEPKTS 0x320
 1944 #define XM_RXSTATS_BADMACCTLPKTS        0x324
 1945 #define XM_RXSTATS_BURSTCNT     0x328
 1946 #define XM_RXSTATS_MISSEDPKTS   0x32C
 1947 #define XM_RXSTATS_FRAMEERRS    0x330
 1948 #define XM_RXSTATS_OVERRUN      0x334
 1949 #define XM_RXSTATS_JABBER       0x338
 1950 #define XM_RXSTATS_CARRLOSS     0x33C
 1951 #define XM_RXSTATS_INRNGLENERR  0x340
 1952 #define XM_RXSTATS_SYMERR       0x344
 1953 #define XM_RXSTATS_SHORTEVENT   0x348
 1954 #define XM_RXSTATS_RUNTS        0x34C
 1955 #define XM_RXSTATS_GIANTS       0x350
 1956 #define XM_RXSTATS_CRCERRS      0x354
 1957 #define XM_RXSTATS_CEXTERRS     0x35C
 1958 #define XM_RXSTATS_UTILIZATION  0x360
 1959 #define XM_RXSTATS_64           0x368
 1960 #define XM_RXSTATS_65_127       0x36C
 1961 #define XM_RXSTATS_128_255      0x370
 1962 #define XM_RXSTATS_256_511      0x374
 1963 #define XM_RXSTATS_512_1023     0x378
 1964 #define XM_RXSTATS_1024_MAX     0x37C
 1965 
 1966 #define XM_MMUCMD_TX_ENB        0x0001
 1967 #define XM_MMUCMD_RX_ENB        0x0002
 1968 #define XM_MMUCMD_GMIILOOP      0x0004
 1969 #define XM_MMUCMD_RATECTL       0x0008
 1970 #define XM_MMUCMD_GMIIFDX       0x0010
 1971 #define XM_MMUCMD_NO_MGMT_PRMB  0x0020
 1972 #define XM_MMUCMD_SIMCOL        0x0040
 1973 #define XM_MMUCMD_FORCETX       0x0080
 1974 #define XM_MMUCMD_LOOPENB       0x0200
 1975 #define XM_MMUCMD_IGNPAUSE      0x0400
 1976 #define XM_MMUCMD_PHYBUSY       0x0800
 1977 #define XM_MMUCMD_PHYDATARDY    0x1000
 1978 
 1979 #define XM_TXCMD_AUTOPAD        0x0001
 1980 #define XM_TXCMD_NOCRC          0x0002
 1981 #define XM_TXCMD_NOPREAMBLE     0x0004
 1982 #define XM_TXCMD_NOGIGAMODE     0x0008
 1983 #define XM_TXCMD_SAMPLELINE     0x0010
 1984 #define XM_TXCMD_ENCBYPASS      0x0020
 1985 #define XM_TXCMD_XMITBK2BK      0x0040
 1986 #define XM_TXCMD_FAIRSHARE      0x0080
 1987 
 1988 #define XM_RXCMD_DISABLE_CEXT   0x0001
 1989 #define XM_RXCMD_STRIPPAD       0x0002
 1990 #define XM_RXCMD_SAMPLELINE     0x0004
 1991 #define XM_RXCMD_SELFRX         0x0008
 1992 #define XM_RXCMD_STRIPFCS       0x0010
 1993 #define XM_RXCMD_TRANSPARENT    0x0020
 1994 #define XM_RXCMD_IPGCAPTURE     0x0040
 1995 #define XM_RXCMD_BIGPKTOK       0x0080
 1996 #define XM_RXCMD_LENERROK       0x0100
 1997 
 1998 #define XM_GPIO_GP0_SET         0x0001
 1999 #define XM_GPIO_RESETSTATS      0x0004
 2000 #define XM_GPIO_RESETMAC        0x0008
 2001 #define XM_GPIO_FORCEINT        0x0020
 2002 #define XM_GPIO_ANEGINPROG      0x0040
 2003 
 2004 #define XM_IMR_RX_EOF           0x0001
 2005 #define XM_IMR_TX_EOF           0x0002
 2006 #define XM_IMR_TX_UNDERRUN      0x0004
 2007 #define XM_IMR_RX_OVERRUN       0x0008
 2008 #define XM_IMR_TX_STATS_OFLOW   0x0010
 2009 #define XM_IMR_RX_STATS_OFLOW   0x0020
 2010 #define XM_IMR_TSTAMP_OFLOW     0x0040
 2011 #define XM_IMR_AUTONEG_DONE     0x0080
 2012 #define XM_IMR_NEXTPAGE_RDY     0x0100
 2013 #define XM_IMR_PAGE_RECEIVED    0x0200
 2014 #define XM_IMR_LP_REQCFG        0x0400
 2015 #define XM_IMR_GP0_SET          0x0800
 2016 #define XM_IMR_FORCEINTR        0x1000
 2017 #define XM_IMR_TX_ABORT         0x2000
 2018 #define XM_IMR_LINKEVENT        0x4000
 2019 
 2020 #define XM_INTRS        \
 2021         (~(XM_IMR_GP0_SET|XM_IMR_AUTONEG_DONE|XM_IMR_TX_UNDERRUN))
 2022 
 2023 #define XM_ISR_RX_EOF           0x0001
 2024 #define XM_ISR_TX_EOF           0x0002
 2025 #define XM_ISR_TX_UNDERRUN      0x0004
 2026 #define XM_ISR_RX_OVERRUN       0x0008
 2027 #define XM_ISR_TX_STATS_OFLOW   0x0010
 2028 #define XM_ISR_RX_STATS_OFLOW   0x0020
 2029 #define XM_ISR_TSTAMP_OFLOW     0x0040
 2030 #define XM_ISR_AUTONEG_DONE     0x0080
 2031 #define XM_ISR_NEXTPAGE_RDY     0x0100
 2032 #define XM_ISR_PAGE_RECEIVED    0x0200
 2033 #define XM_ISR_LP_REQCFG        0x0400
 2034 #define XM_ISR_GP0_SET          0x0800
 2035 #define XM_ISR_FORCEINTR        0x1000
 2036 #define XM_ISR_TX_ABORT         0x2000
 2037 #define XM_ISR_LINKEVENT        0x4000
 2038 
 2039 #define XM_HWCFG_GENEOP         0x0008
 2040 #define XM_HWCFG_SIGSTATCKH     0x0004
 2041 #define XM_HWCFG_GMIIMODE       0x0001
 2042 
 2043 #define XM_MODE_FLUSH_RXFIFO    0x00000001
 2044 #define XM_MODE_FLUSH_TXFIFO    0x00000002
 2045 #define XM_MODE_BIGENDIAN       0x00000004
 2046 #define XM_MODE_RX_PROMISC      0x00000008
 2047 #define XM_MODE_RX_NOBROAD      0x00000010
 2048 #define XM_MODE_RX_NOMULTI      0x00000020
 2049 #define XM_MODE_RX_NOUNI        0x00000040
 2050 #define XM_MODE_RX_BADFRAMES    0x00000080
 2051 #define XM_MODE_RX_CRCERRS      0x00000100
 2052 #define XM_MODE_RX_GIANTS       0x00000200
 2053 #define XM_MODE_RX_INRANGELEN   0x00000400
 2054 #define XM_MODE_RX_RUNTS        0x00000800
 2055 #define XM_MODE_RX_MACCTL       0x00001000
 2056 #define XM_MODE_RX_USE_PERFECT  0x00002000
 2057 #define XM_MODE_RX_USE_STATION  0x00004000
 2058 #define XM_MODE_RX_USE_HASH     0x00008000
 2059 #define XM_MODE_RX_ADDRPAIR     0x00010000
 2060 #define XM_MODE_PAUSEONHI       0x00020000
 2061 #define XM_MODE_PAUSEONLO       0x00040000
 2062 #define XM_MODE_TIMESTAMP       0x00080000
 2063 #define XM_MODE_SENDPAUSE       0x00100000
 2064 #define XM_MODE_SENDCONTINUOUS  0x00200000
 2065 #define XM_MODE_LE_STATUSWORD   0x00400000
 2066 #define XM_MODE_AUTOFIFOPAUSE   0x00800000
 2067 #define XM_MODE_EXPAUSEGEN      0x02000000
 2068 #define XM_MODE_RX_INVERSE      0x04000000
 2069 
 2070 #define XM_RXSTAT_MACCTL        0x00000001
 2071 #define XM_RXSTAT_ERRFRAME      0x00000002
 2072 #define XM_RXSTAT_CRCERR        0x00000004
 2073 #define XM_RXSTAT_GIANT         0x00000008
 2074 #define XM_RXSTAT_RUNT          0x00000010
 2075 #define XM_RXSTAT_FRAMEERR      0x00000020
 2076 #define XM_RXSTAT_INRANGEERR    0x00000040
 2077 #define XM_RXSTAT_CARRIERERR    0x00000080
 2078 #define XM_RXSTAT_COLLERR       0x00000100
 2079 #define XM_RXSTAT_802_3         0x00000200
 2080 #define XM_RXSTAT_CARREXTERR    0x00000400
 2081 #define XM_RXSTAT_BURSTMODE     0x00000800
 2082 #define XM_RXSTAT_UNICAST       0x00002000
 2083 #define XM_RXSTAT_MULTICAST     0x00004000
 2084 #define XM_RXSTAT_BROADCAST     0x00008000
 2085 #define XM_RXSTAT_VLAN_LEV1     0x00010000
 2086 #define XM_RXSTAT_VLAN_LEV2     0x00020000
 2087 #define XM_RXSTAT_LEN           0xFFFC0000
 2088 #define XM_RXSTAT_LENSHIFT      18
 2089 
 2090 #define XM_RXSTAT_BYTES(x)      ((x) >> XM_RXSTAT_LENSHIFT)
 2091 
 2092 /*
 2093  * XMAC PHY registers, indirectly accessed through
 2094  * XM_PHY_ADDR and XM_PHY_REG.
 2095  */
 2096 
 2097 #define XM_PHY_BMCR             0x0000  /* control */
 2098 #define XM_PHY_BMSR             0x0001  /* status */
 2099 #define XM_PHY_VENID            0x0002  /* vendor id */
 2100 #define XM_PHY_DEVID            0x0003  /* device id */
 2101 #define XM_PHY_ANAR             0x0004  /* autoneg advertisenemt */
 2102 #define XM_PHY_LPAR             0x0005  /* link partner ability */
 2103 #define XM_PHY_ANEXP            0x0006  /* autoneg expansion */
 2104 #define XM_PHY_NEXTP            0x0007  /* nextpage */
 2105 #define XM_PHY_LPNEXTP          0x0008  /* link partner's nextpage */
 2106 #define XM_PHY_EXTSTS           0x000F  /* extented status */
 2107 #define XM_PHY_RESAB            0x0010  /* resolved ability */
 2108 
 2109 #define XM_BMCR_DUPLEX          0x0100
 2110 #define XM_BMCR_RENEGOTIATE     0x0200
 2111 #define XM_BMCR_AUTONEGENBL     0x1000
 2112 #define XM_BMCR_LOOPBACK        0x4000
 2113 #define XM_BMCR_RESET           0x8000
 2114 
 2115 #define XM_BMSR_EXTCAP          0x0001
 2116 #define XM_BMSR_LINKSTAT        0x0004
 2117 #define XM_BMSR_AUTONEGABLE     0x0008
 2118 #define XM_BMSR_REMFAULT        0x0010
 2119 #define XM_BMSR_AUTONEGDONE     0x0020
 2120 #define XM_BMSR_EXTSTAT         0x0100
 2121 
 2122 #define XM_VENID_XAQTI          0xD14C
 2123 #define XM_DEVID_XMAC           0x0002
 2124 
 2125 #define XM_ANAR_FULLDUPLEX      0x0020
 2126 #define XM_ANAR_HALFDUPLEX      0x0040
 2127 #define XM_ANAR_PAUSEBITS       0x0180
 2128 #define XM_ANAR_REMFAULTBITS    0x1800
 2129 #define XM_ANAR_ACK             0x4000
 2130 #define XM_ANAR_NEXTPAGE        0x8000
 2131 
 2132 #define XM_LPAR_FULLDUPLEX      0x0020
 2133 #define XM_LPAR_HALFDUPLEX      0x0040
 2134 #define XM_LPAR_PAUSEBITS       0x0180
 2135 #define XM_LPAR_REMFAULTBITS    0x1800
 2136 #define XM_LPAR_ACK             0x4000
 2137 #define XM_LPAR_NEXTPAGE        0x8000
 2138 
 2139 #define XM_PAUSE_NOPAUSE        0x0000
 2140 #define XM_PAUSE_SYMPAUSE       0x0080
 2141 #define XM_PAUSE_ASYMPAUSE      0x0100
 2142 #define XM_PAUSE_BOTH           0x0180
 2143 
 2144 #define XM_REMFAULT_LINKOK      0x0000
 2145 #define XM_REMFAULT_LINKFAIL    0x0800
 2146 #define XM_REMFAULT_OFFLINE     0x1000
 2147 #define XM_REMFAULT_ANEGERR     0x1800
 2148 
 2149 #define XM_ANEXP_GOTPAGE        0x0002
 2150 #define XM_ANEXP_NEXTPAGE_SELF  0x0004
 2151 #define XM_ANEXP_NEXTPAGE_LP    0x0008
 2152 
 2153 #define XM_NEXTP_MESSAGE        0x07FF
 2154 #define XM_NEXTP_TOGGLE         0x0800
 2155 #define XM_NEXTP_ACK2           0x1000
 2156 #define XM_NEXTP_MPAGE          0x2000
 2157 #define XM_NEXTP_ACK1           0x4000
 2158 #define XM_NEXTP_NPAGE          0x8000
 2159 
 2160 #define XM_LPNEXTP_MESSAGE      0x07FF
 2161 #define XM_LPNEXTP_TOGGLE       0x0800
 2162 #define XM_LPNEXTP_ACK2         0x1000
 2163 #define XM_LPNEXTP_MPAGE        0x2000
 2164 #define XM_LPNEXTP_ACK1         0x4000
 2165 #define XM_LPNEXTP_NPAGE        0x8000
 2166 
 2167 #define XM_EXTSTS_HALFDUPLEX    0x4000
 2168 #define XM_EXTSTS_FULLDUPLEX    0x8000
 2169 
 2170 #define XM_RESAB_PAUSEMISMATCH  0x0008
 2171 #define XM_RESAB_ABLMISMATCH    0x0010
 2172 #define XM_RESAB_FDMODESEL      0x0020
 2173 #define XM_RESAB_HDMODESEL      0x0040
 2174 #define XM_RESAB_PAUSEBITS      0x0180
 2175 
 2176 #define SK_HASH_BITS            6
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