CSR_WRITE_2 1109 dev/ic/acx.c CSR_WRITE_2(sc, ACXREG_INTR_ACK, ACXRV_INTR_ALL); CSR_WRITE_2 1123 dev/ic/acx.c CSR_WRITE_2(sc, ACXREG_INTR_MASK, sc->chip_intr_disable); CSR_WRITE_2 1124 dev/ic/acx.c CSR_WRITE_2(sc, ACXREG_EVENT_MASK, 0); CSR_WRITE_2 1131 dev/ic/acx.c CSR_WRITE_2(sc, ACXREG_INTR_MASK, ~sc->chip_intr_enable); CSR_WRITE_2 1132 dev/ic/acx.c CSR_WRITE_2(sc, ACXREG_EVENT_MASK, ACXRV_EVENT_DISABLE); CSR_WRITE_2 1435 dev/ic/acx.c CSR_WRITE_2(sc, ACXREG_SOFT_RESET, reg | ACXRV_SOFT_RESET); CSR_WRITE_2 1437 dev/ic/acx.c CSR_WRITE_2(sc, ACXREG_SOFT_RESET, reg); CSR_WRITE_2 1544 dev/ic/acx.c CSR_WRITE_2(sc, ACXREG_ECPU_CTRL, ACXRV_ECPU_START); CSR_WRITE_2 1552 dev/ic/acx.c CSR_WRITE_2(sc, ACXREG_INTR_ACK, ACXRV_INTR_FCS_THRESH); CSR_WRITE_2 2315 dev/ic/acx.c CSR_WRITE_2(sc, ACXREG_INTR_TRIG, ACXRV_TRIG_TX_FINI); CSR_WRITE_2 2630 dev/ic/acx.c CSR_WRITE_2(sc, ACXREG_INTR_TRIG, ACXRV_TRIG_CMD_FINI); CSR_WRITE_2 2645 dev/ic/acx.c CSR_WRITE_2(sc, ACXREG_INTR_ACK, ACXRV_INTR_CMD_FINI); CSR_WRITE_2 94 dev/ic/acxvar.h CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (b)) CSR_WRITE_2 96 dev/ic/acxvar.h CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & (~(b))) CSR_WRITE_2 195 dev/ic/an.c CSR_WRITE_2(sc, AN_INT_EN, 0); CSR_WRITE_2 196 dev/ic/an.c CSR_WRITE_2(sc, AN_EVENT_ACK, 0xffff); CSR_WRITE_2 371 dev/ic/an.c CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX); CSR_WRITE_2 381 dev/ic/an.c CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX); CSR_WRITE_2 393 dev/ic/an.c CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX); CSR_WRITE_2 403 dev/ic/an.c CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX); CSR_WRITE_2 411 dev/ic/an.c CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX); CSR_WRITE_2 423 dev/ic/an.c CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX); CSR_WRITE_2 453 dev/ic/an.c CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_RX); CSR_WRITE_2 501 dev/ic/an.c CSR_WRITE_2(sc, AN_EVENT_ACK, status & (AN_EV_TX | AN_EV_TX_EXC)); CSR_WRITE_2 544 dev/ic/an.c CSR_WRITE_2(sc, AN_INT_EN, 0); CSR_WRITE_2 545 dev/ic/an.c CSR_WRITE_2(sc, AN_EVENT_ACK, ~0); CSR_WRITE_2 560 dev/ic/an.c CSR_WRITE_2(sc, AN_EVENT_ACK, status & ~(AN_INTRS)); CSR_WRITE_2 593 dev/ic/an.c CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_CLR_STUCK_BUSY); CSR_WRITE_2 596 dev/ic/an.c CSR_WRITE_2(sc, AN_PARAM0, val); CSR_WRITE_2 597 dev/ic/an.c CSR_WRITE_2(sc, AN_PARAM1, 0); CSR_WRITE_2 598 dev/ic/an.c CSR_WRITE_2(sc, AN_PARAM2, 0); CSR_WRITE_2 599 dev/ic/an.c CSR_WRITE_2(sc, AN_COMMAND, cmd); CSR_WRITE_2 616 dev/ic/an.c CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_CLR_STUCK_BUSY); CSR_WRITE_2 619 dev/ic/an.c CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_CMD); CSR_WRITE_2 669 dev/ic/an.c CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_LINKSTAT); CSR_WRITE_2 690 dev/ic/an.c CSR_WRITE_2(sc, AN_COMMAND, AN_CMD_NOOP2); CSR_WRITE_2 696 dev/ic/an.c CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_CMD); CSR_WRITE_2 747 dev/ic/an.c CSR_WRITE_2(sc, AN_SEL0, id); CSR_WRITE_2 748 dev/ic/an.c CSR_WRITE_2(sc, AN_OFF0, off); CSR_WRITE_2 832 dev/ic/an.c CSR_WRITE_2(sc, AN_EVENT_ACK, AN_EV_ALLOC); CSR_WRITE_2 963 dev/ic/an.c CSR_WRITE_2(sc, AN_SW0, AN_MAGIC); CSR_WRITE_2 1082 dev/ic/an.c CSR_WRITE_2(sc, AN_INT_EN, AN_INTRS); CSR_WRITE_2 1248 dev/ic/an.c CSR_WRITE_2(sc, AN_INT_EN, 0); CSR_WRITE_2 221 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); CSR_WRITE_2 223 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); CSR_WRITE_2 225 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); CSR_WRITE_2 238 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); CSR_WRITE_2 241 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); CSR_WRITE_2 246 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); CSR_WRITE_2 250 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); CSR_WRITE_2 255 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); CSR_WRITE_2 262 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); CSR_WRITE_2 267 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); CSR_WRITE_2 270 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); CSR_WRITE_2 585 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); CSR_WRITE_2 595 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); CSR_WRITE_2 596 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, CSR_WRITE_2 599 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); CSR_WRITE_2 607 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); CSR_WRITE_2 608 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, CSR_WRITE_2 613 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); CSR_WRITE_2 616 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); CSR_WRITE_2 636 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); CSR_WRITE_2 646 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); CSR_WRITE_2 647 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, CSR_WRITE_2 650 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); CSR_WRITE_2 662 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); CSR_WRITE_2 663 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, CSR_WRITE_2 666 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); CSR_WRITE_2 675 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, CSR_WRITE_2 681 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); CSR_WRITE_2 685 dev/ic/fxp.c CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); CSR_WRITE_2 461 dev/ic/if_wi.c CSR_WRITE_2(sc, WI_INT_EN, mode); CSR_WRITE_2 468 dev/ic/if_wi.c CSR_WRITE_2(sc, WI_EVENT_ACK, mode); CSR_WRITE_2 483 dev/ic/if_wi.c CSR_WRITE_2(sc, WI_INT_EN, 0); CSR_WRITE_2 484 dev/ic/if_wi.c CSR_WRITE_2(sc, WI_EVENT_ACK, 0xffff); CSR_WRITE_2 489 dev/ic/if_wi.c CSR_WRITE_2(sc, WI_INT_EN, 0); CSR_WRITE_2 492 dev/ic/if_wi.c CSR_WRITE_2(sc, WI_EVENT_ACK, ~WI_INTRS); CSR_WRITE_2 496 dev/ic/if_wi.c CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_RX); CSR_WRITE_2 501 dev/ic/if_wi.c CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_TX); CSR_WRITE_2 507 dev/ic/if_wi.c CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_ALLOC); CSR_WRITE_2 514 dev/ic/if_wi.c CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_INFO); CSR_WRITE_2 519 dev/ic/if_wi.c CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_TX_EXC); CSR_WRITE_2 523 dev/ic/if_wi.c CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_INFO_DROP); CSR_WRITE_2 527 dev/ic/if_wi.c CSR_WRITE_2(sc, WI_INT_EN, WI_INTRS); CSR_WRITE_2 959 dev/ic/if_wi.c CSR_WRITE_2(sc, WI_PARAM0, val0); CSR_WRITE_2 960 dev/ic/if_wi.c CSR_WRITE_2(sc, WI_PARAM1, val1); CSR_WRITE_2 961 dev/ic/if_wi.c CSR_WRITE_2(sc, WI_PARAM2, val2); CSR_WRITE_2 962 dev/ic/if_wi.c CSR_WRITE_2(sc, WI_COMMAND, cmd); CSR_WRITE_2 973 dev/ic/if_wi.c CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_CMD); CSR_WRITE_2 1260 dev/ic/if_wi.c CSR_WRITE_2(sc, WI_DATA1, ltv->wi_len); CSR_WRITE_2 1261 dev/ic/if_wi.c CSR_WRITE_2(sc, WI_DATA1, ltv->wi_type); CSR_WRITE_2 1294 dev/ic/if_wi.c CSR_WRITE_2(sc, selreg, id); CSR_WRITE_2 1295 dev/ic/if_wi.c CSR_WRITE_2(sc, offreg, off); CSR_WRITE_2 1349 dev/ic/if_wi.c CSR_WRITE_2(sc, WI_DATA0, 0x1234); CSR_WRITE_2 1350 dev/ic/if_wi.c CSR_WRITE_2(sc, WI_DATA0, 0x5678); CSR_WRITE_2 1387 dev/ic/if_wi.c CSR_WRITE_2(sc, WI_EVENT_ACK, WI_EV_ALLOC); CSR_WRITE_2 1393 dev/ic/if_wi.c CSR_WRITE_2(sc, WI_DATA0, 0); CSR_WRITE_2 290 dev/ic/mtd8xx.c CSR_WRITE_2(MTD_PHYCSR + (reg << 1), val); CSR_WRITE_2 494 dev/ic/re.c CSR_WRITE_2(sc, re8139_reg, data); CSR_WRITE_2 687 dev/ic/re.c CSR_WRITE_2(sc, RL_ISR, RL_INTRS); CSR_WRITE_2 703 dev/ic/re.c CSR_WRITE_2(sc, RL_ISR, 0xFFFF); CSR_WRITE_2 717 dev/ic/re.c CSR_WRITE_2(sc, RL_ISR, status); CSR_WRITE_2 1492 dev/ic/re.c CSR_WRITE_2(sc, RL_ISR, status); CSR_WRITE_2 1812 dev/ic/re.c CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB| CSR_WRITE_2 1896 dev/ic/re.c CSR_WRITE_2(sc, RL_IMR, 0); CSR_WRITE_2 1898 dev/ic/re.c CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); CSR_WRITE_2 1899 dev/ic/re.c CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); CSR_WRITE_2 1925 dev/ic/re.c CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); CSR_WRITE_2 2091 dev/ic/re.c CSR_WRITE_2(sc, RL_IMR, 0x0000); CSR_WRITE_2 2092 dev/ic/re.c CSR_WRITE_2(sc, RL_ISR, 0xFFFF); CSR_WRITE_2 339 dev/ic/rtl81x9.c CSR_WRITE_2(sc, RL_MII, 0); CSR_WRITE_2 707 dev/ic/rtl81x9.c CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); CSR_WRITE_2 811 dev/ic/rtl81x9.c CSR_WRITE_2(sc, RL_IMR, 0x0000); CSR_WRITE_2 819 dev/ic/rtl81x9.c CSR_WRITE_2(sc, RL_ISR, status); CSR_WRITE_2 836 dev/ic/rtl81x9.c CSR_WRITE_2(sc, RL_IMR, RL_INTRS); CSR_WRITE_2 1036 dev/ic/rtl81x9.c CSR_WRITE_2(sc, RL_IMR, RL_INTRS); CSR_WRITE_2 1196 dev/ic/rtl81x9.c CSR_WRITE_2(sc, RL_IMR, 0x0000); CSR_WRITE_2 1451 dev/ic/rtl81x9.c CSR_WRITE_2(sc, rl8139_reg, val); CSR_WRITE_2 795 dev/ic/rtl81x9reg.h CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) CSR_WRITE_2 798 dev/ic/rtl81x9reg.h CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) CSR_WRITE_2 253 dev/ic/xl.c CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ CSR_WRITE_2 257 dev/ic/xl.c CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ CSR_WRITE_2 327 dev/ic/xl.c CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); CSR_WRITE_2 540 dev/ic/xl.c CSR_WRITE_2(sc, XL_W0_EE_CMD, CSR_WRITE_2 543 dev/ic/xl.c CSR_WRITE_2(sc, XL_W0_EE_CMD, CSR_WRITE_2 577 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); CSR_WRITE_2 586 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); CSR_WRITE_2 611 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); CSR_WRITE_2 619 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i); CSR_WRITE_2 630 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|XL_HASH_SET|h); CSR_WRITE_2 640 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); CSR_WRITE_2 659 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); CSR_WRITE_2 707 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); CSR_WRITE_2 789 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); CSR_WRITE_2 791 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); CSR_WRITE_2 794 dev/ic/xl.c CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); CSR_WRITE_2 805 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | CSR_WRITE_2 832 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); CSR_WRITE_2 835 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); CSR_WRITE_2 841 dev/ic/xl.c CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc, CSR_WRITE_2 1300 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); CSR_WRITE_2 1306 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); CSR_WRITE_2 1373 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); CSR_WRITE_2 1438 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); CSR_WRITE_2 1472 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, CSR_WRITE_2 1475 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, CSR_WRITE_2 1478 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); CSR_WRITE_2 1479 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); CSR_WRITE_2 1481 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); CSR_WRITE_2 1482 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); CSR_WRITE_2 1507 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, CSR_WRITE_2 1803 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); CSR_WRITE_2 1823 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); CSR_WRITE_2 1952 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); CSR_WRITE_2 1955 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); CSR_WRITE_2 1968 dev/ic/xl.c CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); CSR_WRITE_2 1971 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); CSR_WRITE_2 1973 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); CSR_WRITE_2 2001 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); CSR_WRITE_2 2013 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, CSR_WRITE_2 2024 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); CSR_WRITE_2 2039 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); CSR_WRITE_2 2059 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); CSR_WRITE_2 2063 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); CSR_WRITE_2 2070 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); CSR_WRITE_2 2075 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); CSR_WRITE_2 2085 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); CSR_WRITE_2 2087 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); CSR_WRITE_2 2097 dev/ic/xl.c CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); CSR_WRITE_2 2106 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); CSR_WRITE_2 2111 dev/ic/xl.c CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); CSR_WRITE_2 2112 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); CSR_WRITE_2 2117 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); CSR_WRITE_2 2118 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS); CSR_WRITE_2 2119 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); CSR_WRITE_2 2125 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); CSR_WRITE_2 2126 dev/ic/xl.c CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); CSR_WRITE_2 2129 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); CSR_WRITE_2 2131 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); CSR_WRITE_2 2437 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); CSR_WRITE_2 2438 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); CSR_WRITE_2 2439 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); CSR_WRITE_2 2440 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); CSR_WRITE_2 2442 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); CSR_WRITE_2 2443 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); CSR_WRITE_2 2447 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); CSR_WRITE_2 2449 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); CSR_WRITE_2 2453 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); CSR_WRITE_2 2454 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); CSR_WRITE_2 2455 dev/ic/xl.c CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); CSR_WRITE_2 2559 dev/ic/xl.c CSR_WRITE_2(sc, 12, n); CSR_WRITE_2 2730 dev/ic/xl.c CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); CSR_WRITE_2 649 dev/ic/xlreg.h CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_WINSEL | x) CSR_WRITE_2 308 dev/pci/if_ipwreg.h CSR_WRITE_2((sc), IPW_CSR_INDIRECT_DATA, (val)); \ CSR_WRITE_2 460 dev/pci/if_iwireg.h CSR_WRITE_2((sc), IWI_CSR_INDIRECT_DATA, (val)); \ CSR_WRITE_2 1292 dev/pci/if_lge.c CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); CSR_WRITE_2 247 dev/pci/if_msk.c CSR_WRITE_2(sc, reg, x); CSR_WRITE_2 857 dev/pci/if_msk.c CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); CSR_WRITE_2 858 dev/pci/if_msk.c CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_SET); CSR_WRITE_2 860 dev/pci/if_msk.c CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); CSR_WRITE_2 861 dev/pci/if_msk.c CSR_WRITE_2(sc, SK_LINK_CTRL + SK_WIN_LEN, SK_LINK_RESET_CLEAR); CSR_WRITE_2 871 dev/pci/if_msk.c CSR_WRITE_2(sc, SK_CSR, SK_CSR_ASF_OFF); CSR_WRITE_2 1385 dev/pci/if_msk.c CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); CSR_WRITE_2 1581 dev/pci/if_msk.c CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); CSR_WRITE_2 238 dev/pci/if_sk.c CSR_WRITE_2(sc, reg, x); CSR_WRITE_2 968 dev/pci/if_sk.c CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); CSR_WRITE_2 969 dev/pci/if_sk.c CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); CSR_WRITE_2 971 dev/pci/if_sk.c CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); CSR_WRITE_2 974 dev/pci/if_sk.c CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); CSR_WRITE_2 976 dev/pci/if_sk.c CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); CSR_WRITE_2 978 dev/pci/if_sk.c CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); CSR_WRITE_2 1506 dev/pci/if_sk.c CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); CSR_WRITE_2 1695 dev/pci/if_sk.c CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); CSR_WRITE_2 130 dev/pci/if_ste.c CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x) CSR_WRITE_2 133 dev/pci/if_ste.c CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x) CSR_WRITE_2 214 dev/pci/if_ste.c CSR_WRITE_2(sc, STE_PHYCTL, 0); CSR_WRITE_2 490 dev/pci/if_ste.c CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); CSR_WRITE_2 524 dev/pci/if_ste.c CSR_WRITE_2(sc, STE_MAR0, 0); CSR_WRITE_2 525 dev/pci/if_ste.c CSR_WRITE_2(sc, STE_MAR1, 0); CSR_WRITE_2 526 dev/pci/if_ste.c CSR_WRITE_2(sc, STE_MAR2, 0); CSR_WRITE_2 527 dev/pci/if_ste.c CSR_WRITE_2(sc, STE_MAR3, 0); CSR_WRITE_2 544 dev/pci/if_ste.c CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); CSR_WRITE_2 545 dev/pci/if_ste.c CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); CSR_WRITE_2 546 dev/pci/if_ste.c CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); CSR_WRITE_2 547 dev/pci/if_ste.c CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); CSR_WRITE_2 603 dev/pci/if_ste.c CSR_WRITE_2(sc, STE_IMR, STE_INTRS); CSR_WRITE_2 743 dev/pci/if_ste.c CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); CSR_WRITE_2 744 dev/pci/if_ste.c CSR_WRITE_2(sc, STE_TX_RECLAIM_THRESH, CSR_WRITE_2 748 dev/pci/if_ste.c CSR_WRITE_2(sc, STE_TX_STATUS, txstat); CSR_WRITE_2 1130 dev/pci/if_ste.c CSR_WRITE_2(sc, STE_TX_STARTTHRESH, sc->ste_tx_thresh); CSR_WRITE_2 1175 dev/pci/if_ste.c CSR_WRITE_2(sc, STE_MACCTL0, 0); CSR_WRITE_2 1176 dev/pci/if_ste.c CSR_WRITE_2(sc, STE_MACCTL1, 0); CSR_WRITE_2 1184 dev/pci/if_ste.c CSR_WRITE_2(sc, STE_ISR, 0xFFFF); CSR_WRITE_2 1185 dev/pci/if_ste.c CSR_WRITE_2(sc, STE_IMR, STE_INTRS); CSR_WRITE_2 1188 dev/pci/if_ste.c CSR_WRITE_2(sc, STE_MAX_FRAMELEN, CSR_WRITE_2 1216 dev/pci/if_ste.c CSR_WRITE_2(sc, STE_IMR, 0); CSR_WRITE_2 872 dev/pci/if_stge.c CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); CSR_WRITE_2 1280 dev/pci/if_stge.c CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh); CSR_WRITE_2 1287 dev/pci/if_stge.c CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff); CSR_WRITE_2 1308 dev/pci/if_stge.c CSR_WRITE_2(sc, STGE_IntStatus, 0xffff); CSR_WRITE_2 1309 dev/pci/if_stge.c CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); CSR_WRITE_2 1323 dev/pci/if_stge.c CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16); CSR_WRITE_2 1324 dev/pci/if_stge.c CSR_WRITE_2(sc, STGE_FlowOffThresh, 0); CSR_WRITE_2 1330 dev/pci/if_stge.c CSR_WRITE_2(sc, STGE_MaxFrameSize, STGE_JUMBO_FRAMELEN); CSR_WRITE_2 1332 dev/pci/if_stge.c CSR_WRITE_2(sc, STGE_MaxFrameSize, ETHER_MAX_LEN); CSR_WRITE_2 1348 dev/pci/if_stge.c CSR_WRITE_2(sc, STGE_DebugCtrl, CSR_WRITE_2 1352 dev/pci/if_stge.c CSR_WRITE_2(sc, STGE_DebugCtrl, CSR_WRITE_2 1355 dev/pci/if_stge.c CSR_WRITE_2(sc, STGE_DebugCtrl, CSR_WRITE_2 1432 dev/pci/if_stge.c CSR_WRITE_2(sc, STGE_IntEnable, 0); CSR_WRITE_2 1491 dev/pci/if_stge.c CSR_WRITE_2(sc, STGE_EepromCtrl, CSR_WRITE_2 1629 dev/pci/if_stge.c CSR_WRITE_2(sc, STGE_ReceiveMode, sc->sc_ReceiveMode); CSR_WRITE_2 310 dev/pci/if_tl.c CSR_WRITE_2(sc, TL_DIO_ADDR, reg); CSR_WRITE_2 318 dev/pci/if_tl.c CSR_WRITE_2(sc, TL_DIO_ADDR, reg); CSR_WRITE_2 326 dev/pci/if_tl.c CSR_WRITE_2(sc, TL_DIO_ADDR, reg); CSR_WRITE_2 335 dev/pci/if_tl.c CSR_WRITE_2(sc, TL_DIO_ADDR, reg); CSR_WRITE_2 345 dev/pci/if_tl.c CSR_WRITE_2(sc, TL_DIO_ADDR, reg); CSR_WRITE_2 346 dev/pci/if_tl.c CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), val); CSR_WRITE_2 355 dev/pci/if_tl.c CSR_WRITE_2(sc, TL_DIO_ADDR, reg); CSR_WRITE_2 367 dev/pci/if_tl.c CSR_WRITE_2(sc, TL_DIO_ADDR, reg); CSR_WRITE_2 382 dev/pci/if_tl.c CSR_WRITE_2(sc, TL_DIO_ADDR, reg); CSR_WRITE_2 397 dev/pci/if_tl.c CSR_WRITE_2(sc, TL_DIO_ADDR, reg); CSR_WRITE_2 400 dev/pci/if_tl.c CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); CSR_WRITE_2 412 dev/pci/if_tl.c CSR_WRITE_2(sc, TL_DIO_ADDR, reg); CSR_WRITE_2 415 dev/pci/if_tl.c CSR_WRITE_2(sc, TL_DIO_DATA + (reg & 3), f); CSR_WRITE_2 1351 dev/pci/if_tl.c CSR_WRITE_2(sc, TL_HOST_INT, ints); CSR_WRITE_2 1424 dev/pci/if_tl.c CSR_WRITE_2(sc, TL_DIO_ADDR, TL_TXGOODFRAMES|TL_DIO_ADDR_INC); CSR_WRITE_2 365 dev/pci/if_vge.c CSR_WRITE_2(sc, VGE_MIIDATA, data); CSR_WRITE_2 1121 dev/pci/if_vge.c CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); CSR_WRITE_2 1472 dev/pci/if_vge.c CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); CSR_WRITE_2 1552 dev/pci/if_vge.c CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); CSR_WRITE_2 1556 dev/pci/if_vge.c CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); CSR_WRITE_2 1557 dev/pci/if_vge.c CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); CSR_WRITE_2 1564 dev/pci/if_vge.c CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); CSR_WRITE_2 1607 dev/pci/if_vge.c CSR_WRITE_2(sc, VGE_SSTIMER, 400); CSR_WRITE_2 1851 dev/pci/if_vge.c CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); CSR_WRITE_2 115 dev/pci/if_vgevar.h CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) CSR_WRITE_2 122 dev/pci/if_vgevar.h CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) CSR_WRITE_2 163 dev/pci/if_vr.c CSR_WRITE_2(sc, reg, \ CSR_WRITE_2 167 dev/pci/if_vr.c CSR_WRITE_2(sc, reg, \ CSR_WRITE_2 413 dev/pci/if_vr.c CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); CSR_WRITE_2 1178 dev/pci/if_vr.c CSR_WRITE_2(sc, VR_IMR, 0x0000); CSR_WRITE_2 1184 dev/pci/if_vr.c CSR_WRITE_2(sc, VR_ISR, status); CSR_WRITE_2 1255 dev/pci/if_vr.c CSR_WRITE_2(sc, VR_IMR, VR_INTRS); CSR_WRITE_2 1474 dev/pci/if_vr.c CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| CSR_WRITE_2 1484 dev/pci/if_vr.c CSR_WRITE_2(sc, VR_ISR, 0xFFFF); CSR_WRITE_2 1485 dev/pci/if_vr.c CSR_WRITE_2(sc, VR_IMR, VR_INTRS); CSR_WRITE_2 1648 dev/pci/if_vr.c CSR_WRITE_2(sc, VR_IMR, 0x0000); CSR_WRITE_2 391 dev/pci/if_wi_pci.c CSR_WRITE_2(sc, WI_SW0, WI_DRVR_MAGIC); CSR_WRITE_2 508 dev/pci/if_wi_pci.c CSR_WRITE_2(sc, WI_INT_EN, 0); CSR_WRITE_2 509 dev/pci/if_wi_pci.c CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF); CSR_WRITE_2 416 dev/pcmcia/if_wi_pcmcia.c CSR_WRITE_2(sc, WI_INT_EN, 0); CSR_WRITE_2 417 dev/pcmcia/if_wi_pcmcia.c CSR_WRITE_2(sc, WI_EVENT_ACK, 0xffff);