1 /* $OpenBSD: if_vgevar.h,v 1.3 2006/05/28 00:20:21 brad Exp $ */
2 /* $FreeBSD: if_vgevar.h,v 1.1 2004/09/10 20:57:45 wpaul Exp $ */
3 /*
4 * Copyright (c) 2004
5 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 #define VGE_JUMBO_MTU 9000
36
37 #define VGE_IFQ_MAXLEN 64
38
39 #define VGE_TX_DESC_CNT 256
40 #define VGE_RX_DESC_CNT 256 /* Must be a multiple of 4!! */
41 #define VGE_RING_ALIGN 256
42 #define VGE_RX_LIST_SZ (VGE_RX_DESC_CNT * sizeof(struct vge_rx_desc))
43 #define VGE_TX_LIST_SZ (VGE_TX_DESC_CNT * sizeof(struct vge_tx_desc))
44 #define VGE_TX_DESC_INC(x) (x = (x + 1) % VGE_TX_DESC_CNT)
45 #define VGE_RX_DESC_INC(x) (x = (x + 1) % VGE_RX_DESC_CNT)
46 #define VGE_ADDR_LO(y) ((u_int64_t) (y) & 0xFFFFFFFF)
47 #define VGE_ADDR_HI(y) ((u_int64_t) (y) >> 32)
48 #define VGE_BUFLEN(y) ((y) & 0x7FFF)
49 #define VGE_OWN(x) (letoh32((x)->vge_sts) & VGE_RDSTS_OWN)
50 #define VGE_RXBYTES(x) ((letoh32((x)->vge_sts) & \
51 VGE_RDSTS_BUFSIZ) >> 16)
52 #define VGE_MIN_FRAMELEN 60
53
54 #define MAX_NUM_MULTICAST_ADDRESSES 128
55
56 struct vge_softc;
57
58 struct vge_list_data {
59 struct mbuf *vge_tx_mbuf[VGE_TX_DESC_CNT];
60 struct mbuf *vge_rx_mbuf[VGE_RX_DESC_CNT];
61 int vge_tx_prodidx;
62 int vge_rx_prodidx;
63 int vge_tx_considx;
64 int vge_tx_free;
65 bus_dmamap_t vge_tx_dmamap[VGE_TX_DESC_CNT];
66 bus_dmamap_t vge_rx_dmamap[VGE_RX_DESC_CNT];
67 bus_dma_tag_t vge_mtag; /* mbuf mapping tag */
68 bus_dma_segment_t vge_rx_listseg;
69 bus_dmamap_t vge_rx_list_map;
70 struct vge_rx_desc *vge_rx_list;
71 bus_dma_segment_t vge_tx_listseg;
72 bus_dmamap_t vge_tx_list_map;
73 struct vge_tx_desc *vge_tx_list;
74 };
75
76 struct vge_softc {
77 struct device vge_dev;
78 struct arpcom arpcom; /* interface info */
79 bus_space_handle_t vge_bhandle; /* bus space handle */
80 bus_space_tag_t vge_btag; /* bus space tag */
81 void *vge_intrhand;
82 bus_dma_tag_t sc_dmat;
83 struct mii_data sc_mii;
84 int vge_if_flags;
85 int vge_rx_consumed;
86 int vge_link;
87 int vge_camidx;
88 struct timeout timer_handle;
89 struct mbuf *vge_head;
90 struct mbuf *vge_tail;
91
92 struct vge_list_data vge_ldata;
93 };
94
95 /*
96 * register space access macros
97 */
98 #define CSR_WRITE_4(sc, reg, val) \
99 bus_space_write_4(sc->vge_btag, sc->vge_bhandle, reg, val)
100 #define CSR_WRITE_2(sc, reg, val) \
101 bus_space_write_2(sc->vge_btag, sc->vge_bhandle, reg, val)
102 #define CSR_WRITE_1(sc, reg, val) \
103 bus_space_write_1(sc->vge_btag, sc->vge_bhandle, reg, val)
104
105 #define CSR_READ_4(sc, reg) \
106 bus_space_read_4(sc->vge_btag, sc->vge_bhandle, reg)
107 #define CSR_READ_2(sc, reg) \
108 bus_space_read_2(sc->vge_btag, sc->vge_bhandle, reg)
109 #define CSR_READ_1(sc, reg) \
110 bus_space_read_1(sc->vge_btag, sc->vge_bhandle, reg)
111
112 #define CSR_SETBIT_1(sc, reg, x) \
113 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
114 #define CSR_SETBIT_2(sc, reg, x) \
115 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
116 #define CSR_SETBIT_4(sc, reg, x) \
117 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
118
119 #define CSR_CLRBIT_1(sc, reg, x) \
120 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
121 #define CSR_CLRBIT_2(sc, reg, x) \
122 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
123 #define CSR_CLRBIT_4(sc, reg, x) \
124 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
125
126 #define VGE_TIMEOUT 10000